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arm_gicv3_cpuif.c
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arm_gicv3_cpuif.c
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/*
* ARM Generic Interrupt Controller v3 (emulation)
*
* Copyright (c) 2016 Linaro Limited
* Written by Peter Maydell
*
* This code is licensed under the GPL, version 2 or (at your option)
* any later version.
*/
/* This file contains the code for the system register interface
* portions of the GICv3.
*/
#include "qemu/osdep.h"
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "trace.h"
#include "gicv3_internal.h"
#include "hw/irq.h"
#include "cpu.h"
/*
* Special case return value from hppvi_index(); must be larger than
* the architecturally maximum possible list register index (which is 15)
*/
#define HPPVI_INDEX_VLPI 16
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
{
return env->gicv3state;
}
static bool gicv3_use_ns_bank(CPUARMState *env)
{
/* Return true if we should use the NonSecure bank for a banked GIC
* CPU interface register. Note that this differs from the
* access_secure_reg() function because GICv3 banked registers are
* banked even for AArch64, unlike the other CPU system registers.
*/
return !arm_is_secure_below_el3(env);
}
/* The minimum BPR for the virtual interface is a configurable property */
static inline int icv_min_vbpr(GICv3CPUState *cs)
{
return 7 - cs->vprebits;
}
/* Simple accessor functions for LR fields */
static uint32_t ich_lr_vintid(uint64_t lr)
{
return extract64(lr, ICH_LR_EL2_VINTID_SHIFT, ICH_LR_EL2_VINTID_LENGTH);
}
static uint32_t ich_lr_pintid(uint64_t lr)
{
return extract64(lr, ICH_LR_EL2_PINTID_SHIFT, ICH_LR_EL2_PINTID_LENGTH);
}
static uint32_t ich_lr_prio(uint64_t lr)
{
return extract64(lr, ICH_LR_EL2_PRIORITY_SHIFT, ICH_LR_EL2_PRIORITY_LENGTH);
}
static int ich_lr_state(uint64_t lr)
{
return extract64(lr, ICH_LR_EL2_STATE_SHIFT, ICH_LR_EL2_STATE_LENGTH);
}
static bool icv_access(CPUARMState *env, int hcr_flags)
{
/* Return true if this ICC_ register access should really be
* directed to an ICV_ access. hcr_flags is a mask of
* HCR_EL2 bits to check: we treat this as an ICV_ access
* if we are in NS EL1 and at least one of the specified
* HCR_EL2 bits is set.
*
* ICV registers fall into four categories:
* * access if NS EL1 and HCR_EL2.FMO == 1:
* all ICV regs with '0' in their name
* * access if NS EL1 and HCR_EL2.IMO == 1:
* all ICV regs with '1' in their name
* * access if NS EL1 and either IMO or FMO == 1:
* CTLR, DIR, PMR, RPR
*/
uint64_t hcr_el2 = arm_hcr_el2_eff(env);
bool flagmatch = hcr_el2 & hcr_flags & (HCR_IMO | HCR_FMO);
return flagmatch && arm_current_el(env) == 1
&& !arm_is_secure_below_el3(env);
}
static int read_vbpr(GICv3CPUState *cs, int grp)
{
/* Read VBPR value out of the VMCR field (caller must handle
* VCBPR effects if required)
*/
if (grp == GICV3_G0) {
return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT,
ICH_VMCR_EL2_VBPR0_LENGTH);
} else {
return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT,
ICH_VMCR_EL2_VBPR1_LENGTH);
}
}
static void write_vbpr(GICv3CPUState *cs, int grp, int value)
{
/* Write new VBPR1 value, handling the "writing a value less than
* the minimum sets it to the minimum" semantics.
*/
int min = icv_min_vbpr(cs);
if (grp != GICV3_G0) {
min++;
}
value = MAX(value, min);
if (grp == GICV3_G0) {
cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT,
ICH_VMCR_EL2_VBPR0_LENGTH, value);
} else {
cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT,
ICH_VMCR_EL2_VBPR1_LENGTH, value);
}
}
static uint32_t icv_fullprio_mask(GICv3CPUState *cs)
{
/* Return a mask word which clears the unimplemented priority bits
* from a priority value for a virtual interrupt. (Not to be confused
* with the group priority, whose mask depends on the value of VBPR
* for the interrupt group.)
*/
return ~0U << (8 - cs->vpribits);
}
static int ich_highest_active_virt_prio(GICv3CPUState *cs)
{
/* Calculate the current running priority based on the set bits
* in the ICH Active Priority Registers.
*/
int i;
int aprmax = 1 << (cs->vprebits - 5);
assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0]));
for (i = 0; i < aprmax; i++) {
uint32_t apr = cs->ich_apr[GICV3_G0][i] |
cs->ich_apr[GICV3_G1NS][i];
if (!apr) {
continue;
}
return (i * 32 + ctz32(apr)) << (icv_min_vbpr(cs) + 1);
}
/* No current active interrupts: return idle priority */
return 0xff;
}
static int hppvi_index(GICv3CPUState *cs)
{
/*
* Return the list register index of the highest priority pending
* virtual interrupt, as per the HighestPriorityVirtualInterrupt
* pseudocode. If no pending virtual interrupts, return -1.
* If the highest priority pending virtual interrupt is a vLPI,
* return HPPVI_INDEX_VLPI.
* (The pseudocode handles checking whether the vLPI is higher
* priority than the highest priority list register at every
* callsite of HighestPriorityVirtualInterrupt; we check it here.)
*/
ARMCPU *cpu = ARM_CPU(cs->cpu);
CPUARMState *env = &cpu->env;
int idx = -1;
int i;
/* Note that a list register entry with a priority of 0xff will
* never be reported by this function; this is the architecturally
* correct behaviour.
*/
int prio = 0xff;
if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) {
/* Both groups disabled, definitely nothing to do */
return idx;
}
for (i = 0; i < cs->num_list_regs; i++) {
uint64_t lr = cs->ich_lr_el2[i];
int thisprio;
if (ich_lr_state(lr) != ICH_LR_EL2_STATE_PENDING) {
/* Not Pending */
continue;
}
/* Ignore interrupts if relevant group enable not set */
if (lr & ICH_LR_EL2_GROUP) {
if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
continue;
}
} else {
if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
continue;
}
}
thisprio = ich_lr_prio(lr);
if (thisprio < prio) {
prio = thisprio;
idx = i;
}
}
/*
* "no pending vLPI" is indicated with prio = 0xff, which always
* fails the priority check here. vLPIs are only considered
* when we are in Non-Secure state.
*/
if (cs->hppvlpi.prio < prio && !arm_is_secure(env)) {
if (cs->hppvlpi.grp == GICV3_G0) {
if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0) {
return HPPVI_INDEX_VLPI;
}
} else {
if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1) {
return HPPVI_INDEX_VLPI;
}
}
}
return idx;
}
static uint32_t icv_gprio_mask(GICv3CPUState *cs, int group)
{
/* Return a mask word which clears the subpriority bits from
* a priority value for a virtual interrupt in the specified group.
* This depends on the VBPR value.
* If using VBPR0 then:
* a BPR of 0 means the group priority bits are [7:1];
* a BPR of 1 means they are [7:2], and so on down to
* a BPR of 7 meaning no group priority bits at all.
* If using VBPR1 then:
* a BPR of 0 is impossible (the minimum value is 1)
* a BPR of 1 means the group priority bits are [7:1];
* a BPR of 2 means they are [7:2], and so on down to
* a BPR of 7 meaning the group priority is [7].
*
* Which BPR to use depends on the group of the interrupt and
* the current ICH_VMCR_EL2.VCBPR settings.
*
* This corresponds to the VGroupBits() pseudocode.
*/
int bpr;
if (group == GICV3_G1NS && cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) {
group = GICV3_G0;
}
bpr = read_vbpr(cs, group);
if (group == GICV3_G1NS) {
assert(bpr > 0);
bpr--;
}
return ~0U << (bpr + 1);
}
static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
{
/* Return true if we can signal this virtual interrupt defined by
* the given list register value; see the pseudocode functions
* CanSignalVirtualInterrupt and CanSignalVirtualInt.
* Compare also icc_hppi_can_preempt() which is the non-virtual
* equivalent of these checks.
*/
int grp;
uint32_t mask, prio, rprio, vpmr;
if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) {
/* Virtual interface disabled */
return false;
}
/* We don't need to check that this LR is in Pending state because
* that has already been done in hppvi_index().
*/
prio = ich_lr_prio(lr);
vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
ICH_VMCR_EL2_VPMR_LENGTH);
if (prio >= vpmr) {
/* Priority mask masks this interrupt */
return false;
}
rprio = ich_highest_active_virt_prio(cs);
if (rprio == 0xff) {
/* No running interrupt so we can preempt */
return true;
}
grp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
mask = icv_gprio_mask(cs, grp);
/* We only preempt a running interrupt if the pending interrupt's
* group priority is sufficient (the subpriorities are not considered).
*/
if ((prio & mask) < (rprio & mask)) {
return true;
}
return false;
}
static bool icv_hppvlpi_can_preempt(GICv3CPUState *cs)
{
/*
* Return true if we can signal the highest priority pending vLPI.
* We can assume we're Non-secure because hppvi_index() already
* tested for that.
*/
uint32_t mask, rprio, vpmr;
if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) {
/* Virtual interface disabled */
return false;
}
vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
ICH_VMCR_EL2_VPMR_LENGTH);
if (cs->hppvlpi.prio >= vpmr) {
/* Priority mask masks this interrupt */
return false;
}
rprio = ich_highest_active_virt_prio(cs);
if (rprio == 0xff) {
/* No running interrupt so we can preempt */
return true;
}
mask = icv_gprio_mask(cs, cs->hppvlpi.grp);
/*
* We only preempt a running interrupt if the pending interrupt's
* group priority is sufficient (the subpriorities are not considered).
*/
if ((cs->hppvlpi.prio & mask) < (rprio & mask)) {
return true;
}
return false;
}
static uint32_t eoi_maintenance_interrupt_state(GICv3CPUState *cs,
uint32_t *misr)
{
/* Return a set of bits indicating the EOI maintenance interrupt status
* for each list register. The EOI maintenance interrupt status is
* 1 if LR.State == 0 && LR.HW == 0 && LR.EOI == 1
* (see the GICv3 spec for the ICH_EISR_EL2 register).
* If misr is not NULL then we should also collect the information
* about the MISR.EOI, MISR.NP and MISR.U bits.
*/
uint32_t value = 0;
int validcount = 0;
bool seenpending = false;
int i;
for (i = 0; i < cs->num_list_regs; i++) {
uint64_t lr = cs->ich_lr_el2[i];
if ((lr & (ICH_LR_EL2_STATE_MASK | ICH_LR_EL2_HW | ICH_LR_EL2_EOI))
== ICH_LR_EL2_EOI) {
value |= (1 << i);
}
if ((lr & ICH_LR_EL2_STATE_MASK)) {
validcount++;
}
if (ich_lr_state(lr) == ICH_LR_EL2_STATE_PENDING) {
seenpending = true;
}
}
if (misr) {
if (validcount < 2 && (cs->ich_hcr_el2 & ICH_HCR_EL2_UIE)) {
*misr |= ICH_MISR_EL2_U;
}
if (!seenpending && (cs->ich_hcr_el2 & ICH_HCR_EL2_NPIE)) {
*misr |= ICH_MISR_EL2_NP;
}
if (value) {
*misr |= ICH_MISR_EL2_EOI;
}
}
return value;
}
static uint32_t maintenance_interrupt_state(GICv3CPUState *cs)
{
/* Return a set of bits indicating the maintenance interrupt status
* (as seen in the ICH_MISR_EL2 register).
*/
uint32_t value = 0;
/* Scan list registers and fill in the U, NP and EOI bits */
eoi_maintenance_interrupt_state(cs, &value);
if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) &&
(cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) {
value |= ICH_MISR_EL2_LRENP;
}
if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) &&
(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
value |= ICH_MISR_EL2_VGRP0E;
}
if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0DIE) &&
!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
value |= ICH_MISR_EL2_VGRP0D;
}
if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1EIE) &&
(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
value |= ICH_MISR_EL2_VGRP1E;
}
if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1DIE) &&
!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
value |= ICH_MISR_EL2_VGRP1D;
}
return value;
}
void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs)
{
/*
* Tell the CPU about any pending virtual interrupts.
* This should only be called for changes that affect the
* vIRQ and vFIQ status and do not change the maintenance
* interrupt status. This means that unlike gicv3_cpuif_virt_update()
* this function won't recursively call back into the GIC code.
* The main use of this is when the redistributor has changed the
* highest priority pending virtual LPI.
*/
int idx;
int irqlevel = 0;
int fiqlevel = 0;
idx = hppvi_index(cs);
trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx,
cs->hppvlpi.irq, cs->hppvlpi.grp,
cs->hppvlpi.prio);
if (idx == HPPVI_INDEX_VLPI) {
if (icv_hppvlpi_can_preempt(cs)) {
if (cs->hppvlpi.grp == GICV3_G0) {
fiqlevel = 1;
} else {
irqlevel = 1;
}
}
} else if (idx >= 0) {
uint64_t lr = cs->ich_lr_el2[idx];
if (icv_hppi_can_preempt(cs, lr)) {
/* Virtual interrupts are simple: G0 are always FIQ, and G1 IRQ */
if (lr & ICH_LR_EL2_GROUP) {
irqlevel = 1;
} else {
fiqlevel = 1;
}
}
}
trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel);
qemu_set_irq(cs->parent_vfiq, fiqlevel);
qemu_set_irq(cs->parent_virq, irqlevel);
}
static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
{
/*
* Tell the CPU about any pending virtual interrupts or
* maintenance interrupts, following a change to the state
* of the CPU interface relevant to virtual interrupts.
*
* CAUTION: this function will call qemu_set_irq() on the
* CPU maintenance IRQ line, which is typically wired up
* to the GIC as a per-CPU interrupt. This means that it
* will recursively call back into the GIC code via
* gicv3_redist_set_irq() and thus into the CPU interface code's
* gicv3_cpuif_update(). It is therefore important that this
* function is only called as the final action of a CPU interface
* register write implementation, after all the GIC state
* fields have been updated. gicv3_cpuif_update() also must
* not cause this function to be called, but that happens
* naturally as a result of there being no architectural
* linkage between the physical and virtual GIC logic.
*/
ARMCPU *cpu = ARM_CPU(cs->cpu);
int maintlevel = 0;
gicv3_cpuif_virt_irq_fiq_update(cs);
if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) &&
maintenance_interrupt_state(cs) != 0) {
maintlevel = 1;
}
trace_gicv3_cpuif_virt_set_maint_irq(gicv3_redist_affid(cs), maintlevel);
qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel);
}
static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
uint64_t value = cs->ich_apr[grp][regno];
trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
return value;
}
static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
gicv3_cpuif_virt_update(cs);
return;
}
static uint64_t icv_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS;
uint64_t bpr;
bool satinc = false;
if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
/* reads return bpr0 + 1 saturated to 7, writes ignored */
grp = GICV3_G0;
satinc = true;
}
bpr = read_vbpr(cs, grp);
if (satinc) {
bpr++;
bpr = MIN(bpr, 7);
}
trace_gicv3_icv_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr);
return bpr;
}
static void icv_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS;
trace_gicv3_icv_bpr_write(ri->crm == 8 ? 0 : 1,
gicv3_redist_affid(cs), value);
if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
/* reads return bpr0 + 1 saturated to 7, writes ignored */
return;
}
write_vbpr(cs, grp, value);
gicv3_cpuif_virt_update(cs);
}
static uint64_t icv_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
uint64_t value;
value = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
ICH_VMCR_EL2_VPMR_LENGTH);
trace_gicv3_icv_pmr_read(gicv3_redist_affid(cs), value);
return value;
}
static void icv_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
GICv3CPUState *cs = icc_cs_from_env(env);
trace_gicv3_icv_pmr_write(gicv3_redist_affid(cs), value);
value &= icv_fullprio_mask(cs);
cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
ICH_VMCR_EL2_VPMR_LENGTH, value);
gicv3_cpuif_virt_update(cs);
}
static uint64_t icv_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int enbit;
uint64_t value;
enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT;
value = extract64(cs->ich_vmcr_el2, enbit, 1);
trace_gicv3_icv_igrpen_read(ri->opc2 & 1 ? 1 : 0,
gicv3_redist_affid(cs), value);
return value;
}
static void icv_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int enbit;
trace_gicv3_icv_igrpen_write(ri->opc2 & 1 ? 1 : 0,
gicv3_redist_affid(cs), value);
enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT;
cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, enbit, 1, value);
gicv3_cpuif_virt_update(cs);
}
static uint64_t icv_ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
uint64_t value;
/* Note that the fixed fields here (A3V, SEIS, IDbits, PRIbits)
* should match the ones reported in ich_vtr_read().
*/
value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
(7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) {
value |= ICC_CTLR_EL1_EOIMODE;
}
if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) {
value |= ICC_CTLR_EL1_CBPR;
}
trace_gicv3_icv_ctlr_read(gicv3_redist_affid(cs), value);
return value;
}
static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
GICv3CPUState *cs = icc_cs_from_env(env);
trace_gicv3_icv_ctlr_write(gicv3_redist_affid(cs), value);
cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT,
1, value & ICC_CTLR_EL1_CBPR ? 1 : 0);
cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT,
1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0);
gicv3_cpuif_virt_update(cs);
}
static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int prio = ich_highest_active_virt_prio(cs);
trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio);
return prio;
}
static uint64_t icv_hppir_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
int idx = hppvi_index(cs);
uint64_t value = INTID_SPURIOUS;
if (idx == HPPVI_INDEX_VLPI) {
if (cs->hppvlpi.grp == grp) {
value = cs->hppvlpi.irq;
}
} else if (idx >= 0) {
uint64_t lr = cs->ich_lr_el2[idx];
int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
if (grp == thisgrp) {
value = ich_lr_vintid(lr);
}
}
trace_gicv3_icv_hppir_read(ri->crm == 8 ? 0 : 1,
gicv3_redist_affid(cs), value);
return value;
}
static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp)
{
/* Activate the interrupt in the specified list register
* by moving it from Pending to Active state, and update the
* Active Priority Registers.
*/
uint32_t mask = icv_gprio_mask(cs, grp);
int prio = ich_lr_prio(cs->ich_lr_el2[idx]) & mask;
int aprbit = prio >> (8 - cs->vprebits);
int regno = aprbit / 32;
int regbit = aprbit % 32;
cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
cs->ich_lr_el2[idx] |= ICH_LR_EL2_STATE_ACTIVE_BIT;
cs->ich_apr[grp][regno] |= (1 << regbit);
}
static void icv_activate_vlpi(GICv3CPUState *cs)
{
uint32_t mask = icv_gprio_mask(cs, cs->hppvlpi.grp);
int prio = cs->hppvlpi.prio & mask;
int aprbit = prio >> (8 - cs->vprebits);
int regno = aprbit / 32;
int regbit = aprbit % 32;
cs->ich_apr[cs->hppvlpi.grp][regno] |= (1 << regbit);
gicv3_redist_vlpi_pending(cs, cs->hppvlpi.irq, 0);
}
static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
int idx = hppvi_index(cs);
uint64_t intid = INTID_SPURIOUS;
if (idx == HPPVI_INDEX_VLPI) {
if (cs->hppvlpi.grp == grp && icv_hppvlpi_can_preempt(cs)) {
intid = cs->hppvlpi.irq;
icv_activate_vlpi(cs);
}
} else if (idx >= 0) {
uint64_t lr = cs->ich_lr_el2[idx];
int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) {
intid = ich_lr_vintid(lr);
if (!gicv3_intid_is_special(intid)) {
icv_activate_irq(cs, idx, grp);
} else {
/* Interrupt goes from Pending to Invalid */
cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
/* We will now return the (bogus) ID from the list register,
* as per the pseudocode.
*/
}
}
}
trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1,
gicv3_redist_affid(cs), intid);
gicv3_cpuif_virt_update(cs);
return intid;
}
static int icc_highest_active_prio(GICv3CPUState *cs)
{
/* Calculate the current running priority based on the set bits
* in the Active Priority Registers.
*/
int i;
for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) {
uint32_t apr = cs->icc_apr[GICV3_G0][i] |
cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i];
if (!apr) {
continue;
}
return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1);
}
/* No current active interrupts: return idle priority */
return 0xff;
}
static uint32_t icc_gprio_mask(GICv3CPUState *cs, int group)
{
/* Return a mask word which clears the subpriority bits from
* a priority value for an interrupt in the specified group.
* This depends on the BPR value. For CBPR0 (S or NS):
* a BPR of 0 means the group priority bits are [7:1];
* a BPR of 1 means they are [7:2], and so on down to
* a BPR of 7 meaning no group priority bits at all.
* For CBPR1 NS:
* a BPR of 0 is impossible (the minimum value is 1)
* a BPR of 1 means the group priority bits are [7:1];
* a BPR of 2 means they are [7:2], and so on down to
* a BPR of 7 meaning the group priority is [7].
*
* Which BPR to use depends on the group of the interrupt and
* the current ICC_CTLR.CBPR settings.
*
* This corresponds to the GroupBits() pseudocode.
*/
int bpr;
if ((group == GICV3_G1 && cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR) ||
(group == GICV3_G1NS &&
cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) {
group = GICV3_G0;
}
bpr = cs->icc_bpr[group] & 7;
if (group == GICV3_G1NS) {
assert(bpr > 0);
bpr--;
}
return ~0U << (bpr + 1);
}
static bool icc_no_enabled_hppi(GICv3CPUState *cs)
{
/* Return true if there is no pending interrupt, or the
* highest priority pending interrupt is in a group which has been
* disabled at the CPU interface by the ICC_IGRPEN* register enable bits.
*/
return cs->hppi.prio == 0xff || (cs->icc_igrpen[cs->hppi.grp] == 0);
}
static bool icc_hppi_can_preempt(GICv3CPUState *cs)
{
/* Return true if we have a pending interrupt of sufficient
* priority to preempt.
*/
int rprio;
uint32_t mask;
if (icc_no_enabled_hppi(cs)) {
return false;
}
if (cs->hppi.prio >= cs->icc_pmr_el1) {
/* Priority mask masks this interrupt */
return false;
}
rprio = icc_highest_active_prio(cs);
if (rprio == 0xff) {
/* No currently running interrupt so we can preempt */
return true;
}
mask = icc_gprio_mask(cs, cs->hppi.grp);
/* We only preempt a running interrupt if the pending interrupt's
* group priority is sufficient (the subpriorities are not considered).
*/
if ((cs->hppi.prio & mask) < (rprio & mask)) {
return true;
}
return false;
}
void gicv3_cpuif_update(GICv3CPUState *cs)
{
/* Tell the CPU about its highest priority pending interrupt */
int irqlevel = 0;
int fiqlevel = 0;
ARMCPU *cpu = ARM_CPU(cs->cpu);
CPUARMState *env = &cpu->env;
g_assert(qemu_mutex_iothread_locked());
trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq,
cs->hppi.grp, cs->hppi.prio);
if (cs->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) {
/* If a Security-enabled GIC sends a G1S interrupt to a
* Security-disabled CPU, we must treat it as if it were G0.
*/
cs->hppi.grp = GICV3_G0;
}
if (icc_hppi_can_preempt(cs)) {
/* We have an interrupt: should we signal it as IRQ or FIQ?
* This is described in the GICv3 spec section 4.6.2.
*/
bool isfiq;
switch (cs->hppi.grp) {
case GICV3_G0:
isfiq = true;
break;
case GICV3_G1:
isfiq = (!arm_is_secure(env) ||
(arm_current_el(env) == 3 && arm_el_is_aa64(env, 3)));
break;
case GICV3_G1NS:
isfiq = arm_is_secure(env);
break;
default:
g_assert_not_reached();
}
if (isfiq) {
fiqlevel = 1;
} else {
irqlevel = 1;
}
}
trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel);
qemu_set_irq(cs->parent_fiq, fiqlevel);
qemu_set_irq(cs->parent_irq, irqlevel);
}
static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
uint32_t value = cs->icc_pmr_el1;
if (icv_access(env, HCR_FMO | HCR_IMO)) {
return icv_pmr_read(env, ri);
}
if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) &&
(env->cp15.scr_el3 & SCR_FIQ)) {
/* NS access and Group 0 is inaccessible to NS: return the
* NS view of the current priority
*/
if ((value & 0x80) == 0) {
/* Secure priorities not visible to NS */
value = 0;
} else if (value != 0xff) {
value = (value << 1) & 0xff;
}
}
trace_gicv3_icc_pmr_read(gicv3_redist_affid(cs), value);
return value;
}
static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
GICv3CPUState *cs = icc_cs_from_env(env);
if (icv_access(env, HCR_FMO | HCR_IMO)) {
return icv_pmr_write(env, ri, value);
}
trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value);
value &= 0xff;
if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) &&
(env->cp15.scr_el3 & SCR_FIQ)) {
/* NS access and Group 0 is inaccessible to NS: return the
* NS view of the current priority
*/
if (!(cs->icc_pmr_el1 & 0x80)) {
/* Current PMR in the secure range, don't allow NS to change it */
return;
}
value = (value >> 1) | 0x80;
}
cs->icc_pmr_el1 = value;
gicv3_cpuif_update(cs);
}
static void icc_activate_irq(GICv3CPUState *cs, int irq)
{