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tangyRiscVSOC.gprj
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tangyRiscVSOC.gprj
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2AR-18C" pn="GW2AR-LV18QN88C8/I7">gw2ar18c-000</Device>
<FileList>
<File path="src/picorv32.v" type="file.verilog" enable="1"/>
<File path="src/usb_hid_host.v" type="file.verilog" enable="1"/>
<File path="src/usb_hid_host_rom.v" type="file.verilog" enable="1"/>
<File path="src/InputSync.vhd" type="file.vhdl" enable="1"/>
<File path="src/SDRAM_controller_top_SIP/SDRAM_controller_top_SIP.vhd" type="file.vhdl" enable="1"/>
<File path="src/blitter.vhd" type="file.vhdl" enable="1"/>
<File path="src/clkdiv5/clkdiv5.vhd" type="file.vhdl" enable="1"/>
<File path="src/divider32s/divider32s.vhd" type="file.vhdl" enable="1"/>
<File path="src/dvi_tx/dvi_tx.vhd" type="file.vhdl" enable="1"/>
<File path="src/fontProm/fontProm.vhd" type="file.vhdl" enable="1"/>
<File path="src/fpAdd/fpAdd.vhd" type="file.vhdl" enable="1"/>
<File path="src/fpAlu.vhd" type="file.vhdl" enable="1"/>
<File path="src/fpDiv/fpDiv.vhd" type="file.vhdl" enable="1"/>
<File path="src/fpMult/fpMult.vhd" type="file.vhdl" enable="1"/>
<File path="src/fpSub/fpSub.vhd" type="file.vhdl" enable="1"/>
<File path="src/gfxBufRam/gfxBufRam.vhd" type="file.vhdl" enable="1"/>
<File path="src/gouraudEdge.vhd" type="file.vhdl" enable="1"/>
<File path="src/gouraudIterator.vhd" type="file.vhdl" enable="1"/>
<File path="src/gouraudIterator16.vhd" type="file.vhdl" enable="1"/>
<File path="src/gouraudWeight.vhd" type="file.vhdl" enable="1"/>
<File path="src/i2sController.vhd" type="file.vhdl" enable="1"/>
<File path="src/i2sControllerFifo/i2sControllerFifo.vhd" type="file.vhdl" enable="1"/>
<File path="src/keyboardFifo/keyboardFifo.vhd" type="file.vhdl" enable="1"/>
<File path="src/pixelAlpha.vhd" type="file.vhdl" enable="1"/>
<File path="src/pixelGenGfx.vhd" type="file.vhdl" enable="1"/>
<File path="src/pixelGenTxt.vhd" type="file.vhdl" enable="1"/>
<File path="src/pllHDMI/pllHDMI.vhd" type="file.vhdl" enable="1"/>
<File path="src/pllSystem/pllSystem.vhd" type="file.vhdl" enable="1"/>
<File path="src/sdramController.vhd" type="file.vhdl" enable="1"/>
<File path="src/spi.vhd" type="file.vhdl" enable="1"/>
<File path="src/systemRam/systemRam.vhd" type="file.vhdl" enable="1"/>
<File path="src/tangyRiscVSOCTop.vhd" type="file.vhdl" enable="1"/>
<File path="src/textureShader.vhd" type="file.vhdl" enable="1"/>
<File path="src/uart.vhd" type="file.vhdl" enable="1"/>
<File path="src/uartFiFo/uartFiFo.vhd" type="file.vhdl" enable="1"/>
<File path="src/usbHost.vhd" type="file.vhdl" enable="1"/>
<File path="src/tangyRiscVSOC.cst" type="file.cst" enable="1"/>
<File path="src/tangyRiscVSOC.sdc" type="file.sdc" enable="1"/>
</FileList>
</Project>