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target/hexagon: avoid shadowing globals
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The typedef `vaddr` is shadowed by `vaddr` identifiers, so we rename the
identifiers to avoid shadowing the type name.

The global `cpu_env` is shadowed by local `cpu_env` arguments, so we
rename the function arguments to avoid shadowing the global.

Signed-off-by: Brian Cain <bcain@quicinc.com>
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@androm3da
androm3da committed Oct 5, 2023
1 parent 4c20c4f commit 7f20565
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Showing 5 changed files with 42 additions and 42 deletions.
56 changes: 28 additions & 28 deletions target/hexagon/genptr.c
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Original file line number Diff line number Diff line change
Expand Up @@ -334,28 +334,28 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
tcg_gen_deposit_i64(result, result, src64, N * 8, 8);
}

static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
static inline void gen_load_locked4u(TCGv dest, TCGv v_addr, int mem_index)
{
tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL);
tcg_gen_mov_tl(hex_llsc_addr, vaddr);
tcg_gen_qemu_ld_tl(dest, v_addr, mem_index, MO_TEUL);
tcg_gen_mov_tl(hex_llsc_addr, v_addr);
tcg_gen_mov_tl(hex_llsc_val, dest);
}

static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
static inline void gen_load_locked8u(TCGv_i64 dest, TCGv v_addr, int mem_index)
{
tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ);
tcg_gen_mov_tl(hex_llsc_addr, vaddr);
tcg_gen_qemu_ld_i64(dest, v_addr, mem_index, MO_TEUQ);
tcg_gen_mov_tl(hex_llsc_addr, v_addr);
tcg_gen_mov_i64(hex_llsc_val_i64, dest);
}

static inline void gen_store_conditional4(DisasContext *ctx,
TCGv pred, TCGv vaddr, TCGv src)
TCGv pred, TCGv v_addr, TCGv src)
{
TCGLabel *fail = gen_new_label();
TCGLabel *done = gen_new_label();
TCGv one, zero, tmp;

tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail);

one = tcg_constant_tl(0xff);
zero = tcg_constant_tl(0);
Expand All @@ -374,13 +374,13 @@ static inline void gen_store_conditional4(DisasContext *ctx,
}

static inline void gen_store_conditional8(DisasContext *ctx,
TCGv pred, TCGv vaddr, TCGv_i64 src)
TCGv pred, TCGv v_addr, TCGv_i64 src)
{
TCGLabel *fail = gen_new_label();
TCGLabel *done = gen_new_label();
TCGv_i64 one, zero, tmp;

tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
tcg_gen_brcond_tl(TCG_COND_NE, v_addr, hex_llsc_addr, fail);

one = tcg_constant_i64(0xff);
zero = tcg_constant_i64(0);
Expand All @@ -407,57 +407,57 @@ static TCGv gen_slotval(DisasContext *ctx)
}
#endif

void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
void gen_store32(TCGv v_addr, TCGv src, int width, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_mov_tl(hex_store_addr[slot], v_addr);
tcg_gen_movi_tl(hex_store_width[slot], width);
tcg_gen_mov_tl(hex_store_val32[slot], src);
}

void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
void gen_store1(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
gen_store32(vaddr, src, 1, slot);
gen_store32(v_addr, src, 1, slot);
}

void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
void gen_store1i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store1(cpu_env, vaddr, tmp, slot);
gen_store1(cpu_env_, v_addr, tmp, slot);
}

void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
void gen_store2(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
gen_store32(vaddr, src, 2, slot);
gen_store32(v_addr, src, 2, slot);
}

void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
void gen_store2i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store2(cpu_env, vaddr, tmp, slot);
gen_store2(cpu_env_, v_addr, tmp, slot);
}

void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
void gen_store4(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot)
{
gen_store32(vaddr, src, 4, slot);
gen_store32(v_addr, src, 4, slot);
}

void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
void gen_store4i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot)
{
TCGv tmp = tcg_constant_tl(src);
gen_store4(cpu_env, vaddr, tmp, slot);
gen_store4(cpu_env_, v_addr, tmp, slot);
}

void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
void gen_store8(TCGv_env cpu_env_, TCGv v_addr, TCGv_i64 src, uint32_t slot)
{
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
tcg_gen_mov_tl(hex_store_addr[slot], v_addr);
tcg_gen_movi_tl(hex_store_width[slot], 8);
tcg_gen_mov_i64(hex_store_val64[slot], src);
}

void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot)
void gen_store8i(TCGv_env cpu_env_, TCGv v_addr, int64_t src, uint32_t slot)
{
TCGv_i64 tmp = tcg_constant_i64(src);
gen_store8(cpu_env, vaddr, tmp, slot);
gen_store8(cpu_env_, v_addr, tmp, slot);
}

TCGv gen_8bitsof(TCGv result, TCGv value)
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18 changes: 9 additions & 9 deletions target/hexagon/genptr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -24,15 +24,15 @@

extern const SemanticInsn opcode_genptr[];

void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot);
void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot);
void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot);
void gen_store32(TCGv v_addr, TCGv src, int width, uint32_t slot);
void gen_store1(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot);
void gen_store2(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot);
void gen_store4(TCGv_env cpu_env_, TCGv v_addr, TCGv src, uint32_t slot);
void gen_store8(TCGv_env cpu_env_, TCGv v_addr, TCGv_i64 src, uint32_t slot);
void gen_store1i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot);
void gen_store2i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot);
void gen_store4i(TCGv_env cpu_env_, TCGv v_addr, int32_t src, uint32_t slot);
void gen_store8i(TCGv_env cpu_env_, TCGv v_addr, int64_t src, uint32_t slot);
TCGv gen_read_reg(TCGv result, int num);
TCGv gen_read_preg(TCGv pred, uint8_t num);
TCGv get_result_gpr(DisasContext *ctx, int rnum);
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4 changes: 2 additions & 2 deletions target/hexagon/mmvec/system_ext_mmvec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -19,12 +19,12 @@
#include "cpu.h"
#include "mmvec/system_ext_mmvec.h"

void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot)
void mem_gather_store(CPUHexagonState *env, target_ulong v_addr, int slot)
{
size_t size = sizeof(MMVector);

env->vstore_pending[slot] = 1;
env->vstore[slot].va = vaddr;
env->vstore[slot].va = v_addr;
env->vstore[slot].size = size;
memcpy(&env->vstore[slot].data.ub[0], &env->tmp_VRegs[0], size);

Expand Down
2 changes: 1 addition & 1 deletion target/hexagon/mmvec/system_ext_mmvec.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
#ifndef HEXAGON_SYSTEM_EXT_MMVEC_H
#define HEXAGON_SYSTEM_EXT_MMVEC_H

void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot);
void mem_gather_store(CPUHexagonState *env, target_ulong v_addr, int slot);
void mem_vector_scatter_init(CPUHexagonState *env);
void mem_vector_gather_init(CPUHexagonState *env);

Expand Down
4 changes: 2 additions & 2 deletions target/hexagon/op_helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -577,12 +577,12 @@ void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask)
* wasn't cancelled), we have to do the store first.
*/
static void check_noshuf(CPUHexagonState *env, bool pkt_has_store_s1,
uint32_t slot, target_ulong vaddr, int size,
uint32_t slot, target_ulong v_addr, int size,
uintptr_t ra)
{
if (slot == 0 && pkt_has_store_s1 &&
((env->slot_cancelled & (1 << 1)) == 0)) {
probe_read(env, vaddr, size, MMU_USER_IDX, ra);
probe_read(env, v_addr, size, MMU_USER_IDX, ra);
commit_store(env, 1, ra);
}
}
Expand Down

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