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arm64.ss
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arm64.ss
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;;; arm64.ss
;;; SECTION 1: registers
;;; ABI:
;;; Register usage:
;;; r0-r7: C argument/result registers, caller-save
;;; r8: indirect-result register, caller-save
;;; r9-18: caller-save
;;; r19-28: callee-save
;;; r29: frame pointer, callee-save
;;; r30: a.k.a. lr, link register
;;; sp: stack pointer or (same register number) zero register
;;; --------
;;; v0-v7: FP registers used for C arguments/results, caller-save
;;; v8-v15: callee-save for low 64 bits
;;; v16-v31: caller-save
;;; Alignment:
;;; stack must be 16-byte aligned, essentially always
(define-registers
(reserved
[%tc %r19 #t 19 uptr]
[%sfp %r20 #t 20 uptr]
[%ap %r21 #t 21 uptr]
[%trap %r22 #t 22 uptr])
(allocable
[%ac0 %r23 #t 23 uptr]
[%xp %r24 #t 24 uptr]
[%ts %r8 #f 8 uptr]
[%td %r25 #t 25 uptr]
[%cp %r26 #t 26 uptr]
[ %r0 %Carg1 %Cretval #f 0 uptr]
[ %r1 %Carg2 #f 1 uptr]
[ %r2 %Carg3 %reify1 #f 2 uptr]
[ %r3 %Carg4 %reify2 #f 3 uptr]
[ %r4 %Carg5 %save1 #f 4 uptr]
[ %r5 %Carg6 #f 5 uptr]
[ %r6 %Carg7 #f 6 uptr]
[ %r7 %Carg8 #f 7 uptr]
[ %r9 #f 9 uptr]
[ %r12 #f 12 uptr]
[ %r13 #f 13 uptr]
[ %r14 #f 14 uptr]
[ %r15 #f 15 uptr]
[ %lr #f 30 uptr] ; %lr is trashed by 'c' calls including calls to hand-coded routines like get-room
[%fp1 %v16 #f 16 fp]
[%fp2 %v17 #f 17 fp]
[%fp3 %v18 #f 18 fp]
[%fp4 %v19 #f 19 fp]
[%fp5 %v20 #f 20 fp]
[%fp6 %v21 #f 21 fp]
)
(machine-dependent
[%jmptmp %argtmp #f 10 uptr]
[%argtmp2 #f 11 uptr]
[%sp %real-zero #t 31 uptr]
[%Cfparg1 %Cfpretval %v0 #f 0 fp]
[%Cfparg2 %v1 #f 1 fp]
[%Cfparg3 %v2 #f 2 fp]
[%Cfparg4 %v3 #f 3 fp]
[%Cfparg5 %v4 #f 4 fp]
[%Cfparg6 %v5 #f 5 fp]
[%Cfparg7 %v6 #f 6 fp]
[%Cfparg8 %v7 #f 7 fp]
;; etc., but FP registers v8-v15 are preserved
))
;;; SECTION 2: instructions
(module (md-handle-jump ; also sets primitive handlers
mem->mem
fpmem->fpmem
coercible?
coerce-opnd)
(import asm-module)
(define imm-funkymask?
(lambda (x)
(nanopass-case (L15c Triv) x
[(immediate ,imm) (and (funkymask imm) #t)]
[else #f])))
(define imm-unsigned12?
(lambda (x)
(nanopass-case (L15c Triv) x
[(immediate ,imm) (unsigned12? imm)]
[else #f])))
(define imm-neg-unsigned12?
(lambda (x)
(nanopass-case (L15c Triv) x
[(immediate ,imm) (unsigned12? (- imm))]
[else #f])))
(define imm-constant?
(lambda (x)
(nanopass-case (L15c Triv) x
[(immediate ,imm) #t]
[else #f])))
(define-pass imm->negate-imm : (L15c Triv) (ir) -> (L15d Triv) ()
(Triv : Triv (ir) -> Triv ()
[(immediate ,imm) `(immediate ,(- imm))]
[else (sorry! who "~s is not an immediate" ir)]))
(define mref->mref
(lambda (a k)
(define return
(lambda (x0 x1 imm type)
; arm load & store instructions support index or offset but not both
(safe-assert (or (eq? x1 %zero) (eqv? imm 0)))
(k (with-output-language (L15d Triv) `(mref ,x0 ,x1 ,imm ,type)))))
(nanopass-case (L15c Triv) a
[(mref ,lvalue0 ,lvalue1 ,imm ,type)
(lvalue->ur lvalue0
(lambda (x0)
(lvalue->ur lvalue1
(lambda (x1)
(cond
[(and (eq? x1 %zero) (or (signed9? imm)
(aligned-offset? imm)))
(return x0 %zero imm type)]
[(and (not (eq? x1 %zero)) (unsigned12? imm))
(let ([u (make-tmp 'u)])
(seq
(build-set! ,u (asm ,null-info ,(asm-add #f) ,x1 (immediate ,imm)))
(return x0 u 0 type)))]
[(and (not (eq? x1 %zero)) (unsigned12? (- imm)))
(let ([u (make-tmp 'u)])
(seq
(build-set! ,u (asm ,null-info ,(asm-sub #f) ,x1 (immediate ,(- imm))))
(return x0 u 0 type)))]
[else
(let ([u (make-tmp 'u)])
(seq
(build-set! ,u (immediate ,imm))
(if (eq? x1 %zero)
(return x0 u 0 type)
(seq
(build-set! ,u (asm ,null-info ,(asm-add #f) ,u ,x1))
(return x0 u 0 type)))))])))))])))
(define mem->mem
(lambda (a k)
(cond
[(literal@? a)
(let ([u (make-tmp 'u)])
(seq
(build-set! ,u ,(literal@->literal a))
(k (with-output-language (L15d Lvalue) `(mref ,u ,%zero 0 uptr)))))]
[else (mref->mref a k)])))
(define fpmem->fpmem mem->mem)
;; `define-instruction` code takes care of `ur` and `fpur`, to which
;; all type-compatible values must convert
(define-syntax coercible?
(syntax-rules ()
[(_ ?a ?aty*)
(let ([a ?a] [aty* ?aty*])
(or (and (memq 'unsigned12 aty*) (imm-unsigned12? a))
(and (memq 'neg-unsigned12 aty*) (imm-neg-unsigned12? a))
(and (memq 'funkymask aty*) (imm-funkymask? a))
(and (memq 'imm-constant aty*) (imm-constant? a))
(and (memq 'mem aty*) (mem? a))
(and (memq 'fpmem aty*) (fpmem? a))))]))
;; `define-instruction` doesn't try to cover `ur` and `fpur`
(define-syntax coerce-opnd ; passes k something compatible with aty*
(syntax-rules ()
[(_ ?a ?aty* ?k)
(let ([a ?a] [aty* ?aty*] [k ?k])
(cond
[(and (memq 'mem aty*) (mem? a)) (mem->mem a k)]
[(and (memq 'fpmem aty*) (fpmem? a)) (fpmem->fpmem a k)]
[(and (memq 'unsigned12 aty*) (imm-unsigned12? a)) (k (imm->imm a))]
[(and (memq 'neg-unsigned12 aty*) (imm-neg-unsigned12? a)) (k (imm->negate-imm a))]
[(and (memq 'funkymask aty*) (imm-funkymask? a)) (k (imm->imm a))]
[(and (memq 'imm-constant aty*) (imm-constant? a)) (k (imm->imm a))]
[(memq 'ur aty*)
(cond
[(ur? a) (k a)]
[(imm? a)
(let ([u (make-tmp 'u)])
(seq
(build-set! ,u ,(imm->imm a))
(k u)))]
[(mem? a)
(mem->mem a
(lambda (a)
(let ([u (make-tmp 'u)])
(seq
(build-set! ,u ,a)
(k u)))))]
[else (sorry! 'coerce-opnd "unexpected operand ~s" a)])]
[(memq 'fpur aty*)
(cond
[(fpur? a) (k a)]
[(fpmem? a)
(fpmem->fpmem a
(lambda (a)
(let ([u (make-tmp 'u 'fp)])
(seq
(build-set! ,u ,a)
(k u)))))]
[else
(sorry! 'coerce-opnd "unexpected operand ~s" a)])]
[else (sorry! 'coerce-opnd "cannot coerce ~s to ~s" a aty*)]))]))
(define md-handle-jump
(lambda (t)
(with-output-language (L15d Tail)
(define long-form
(lambda (e)
(let ([tmp (make-tmp 'utmp)])
(values
(in-context Effect `(set! ,(make-live-info) ,tmp ,e))
`(jump ,tmp)))))
(nanopass-case (L15c Triv) t
[,lvalue
(if (mem? lvalue)
(mem->mem lvalue (lambda (e) (values '() `(jump ,e))))
(values '() `(jump ,lvalue)))]
[(literal ,info)
(guard (and (not (info-literal-indirect? info))
(memq (info-literal-type info) '(entry library-code))))
(values '() `(jump (literal ,info)))]
[(label-ref ,l ,offset)
(values '() `(jump (label-ref ,l ,offset)))]
[else (long-form t)]))))
(define info-cc-eq (make-info-condition-code 'eq? #f #t))
(define asm-eq (asm-relop info-cc-eq #f))
; x is not the same as z in any clause that follows a clause where (x z)
; and y is coercible to one of its types, however:
; WARNING: do not assume that if x isn't the same as z then x is independent
; of z, since x might be an mref with z as it's base or index
(define-instruction value (- -/ovfl -/eq -/pos)
[(op (z ur) (x ur) (y unsigned12))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-sub (not (eq? op '-))) ,x ,y))]
[(op (z ur) (x ur) (y neg-unsigned12))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-add (not (eq? op '-))) ,x ,y))]
[(op (z ur) (x ur) (y ur))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-sub (not (eq? op '-))) ,x ,y))])
(define-instruction value (+ +/ovfl +/carry)
[(op (z ur) (x ur) (y unsigned12))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-add (not (eq? op '+))) ,x ,y))]
[(op (z ur) (x ur) (y neg-unsigned12))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-sub (not (eq? op '+))) ,x ,y))]
[(op (z ur) (x unsigned12) (y ur))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-add (not (eq? op '+))) ,y ,x))]
[(op (z ur) (x ur) (y ur))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-add (not (eq? op '+))) ,x ,y))])
(define-instruction value (*)
; no imm form available
[(op (z ur) (x ur) (y ur))
`(set! ,(make-live-info) ,z (asm ,info ,asm-mul ,x ,y))])
(define-instruction value (*/ovfl) ; z flag set iff no overflow
; no imm form available
[(op (z ur) (x ur) (y ur))
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,asm-smulh ,x ,y))
`(set! ,(make-live-info) ,z (asm ,null-info ,asm-mul ,x ,y))
`(asm ,null-info ,asm-cmp/asr63 ,u ,z)))])
(define-instruction value (/)
[(op (z ur) (x ur) (y ur))
`(set! ,(make-live-info) ,z (asm ,info ,asm-div ,x ,y))])
(define-instruction value (logand)
[(op (z ur) (x ur) (y funkymask))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-logand #f) ,x ,y))]
[(op (z ur) (x funkymask) (y ur))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-logand #f) ,y ,x))]
[(op (z ur) (x ur) (y ur))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-logand #f) ,x ,y))])
(let ()
(define select-op (lambda (op) (if (eq? op 'logor) asm-logor asm-logxor)))
(define-instruction value (logor logxor)
[(op (z ur) (x funkymask) (y ur))
`(set! ,(make-live-info) ,z (asm ,info ,((select-op op) #f) ,y ,x))]
[(op (z ur) (x ur) (y funkymask ur))
`(set! ,(make-live-info) ,z (asm ,info ,((select-op op) #f) ,x ,y))]))
(define-instruction value (lognot)
[(op (z ur) (x ur))
`(set! ,(make-live-info) ,z (asm ,info ,asm-lognot ,x))])
(define-instruction value (sll srl sra)
[(op (z ur) (x ur) (y imm-constant ur))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-shiftop op) ,x ,y))])
(define-instruction value popcount
[(op (z ur) (x ur))
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,asm-kill))
`(set! ,(make-live-info) ,z (asm ,info ,asm-popcount ,x ,u))))])
(define-instruction value (move)
[(op (z mem) (x ur))
`(set! ,(make-live-info) ,z ,x)]
[(op (z ur) (x ur mem imm-constant))
`(set! ,(make-live-info) ,z ,x)])
(let ()
(define build-lea1
(lambda (info z x)
(let ([offset (info-lea-offset info)])
(with-output-language (L15d Effect)
(cond
[(unsigned12? offset)
`(set! ,(make-live-info) ,z (asm ,info ,(asm-add #f) ,x (immediate ,offset)))]
[(unsigned12? (- offset))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-sub #f) ,x (immediate ,(- offset))))]
[else
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u (immediate ,offset))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-add #f) ,x ,u))))])))))
(define-instruction value lea1
;; NB: would be simpler if offset were explicit operand
;; NB: why not one version of lea with %zero for y in lea1 case?
[(op (z ur) (x ur)) (build-lea1 info z x)])
(define-instruction value lea2
;; NB: would be simpler if offset were explicit operand
[(op (z ur) (x ur) (y ur))
(let ([u (make-tmp 'u)])
(seq
(build-lea1 info u x)
`(set! ,(make-live-info) ,z (asm ,info ,(asm-add #f) ,y ,u))))]))
(define-instruction value (sext8 sext16 sext32 zext8 zext16 zext32)
[(op (z ur) (x ur)) `(set! ,(make-live-info) ,z (asm ,info ,(asm-move/extend op) ,x))])
(let ()
(define imm-zero (with-output-language (L15d Triv) `(immediate 0)))
(define load/store
(lambda (x y w type k) ; x ur, y ur, w ur or imm
(with-output-language (L15d Effect)
(if (ur? w)
(if (eq? y %zero)
(k x w imm-zero)
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,(asm-add #f) ,y ,w))
(k x u imm-zero))))
(let ([n (nanopass-case (L15d Triv) w [(immediate ,imm) imm])])
(cond
[(and (eq? y %zero)
(aligned-offset? n (case type
[(unsigned-32 integer-32) 2]
[(unsigned-16 integer-16) 1]
[(unsigned-8 integer-8) 0]
[else 3])))
(let ([w (in-context Triv `(immediate ,n))])
(k x y w))]
[(and (eq? y %zero) (signed9? n))
(let ([w (in-context Triv `(immediate ,n))])
(k x y w))]
[(and (not (eq? y %zero)) (unsigned12? n))
(let ([w (in-context Triv `(immediate ,n))])
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,(asm-add #f) ,y ,w))
(k x u imm-zero))))]
[(and (not (eq? y %zero)) (unsigned12? (- n)))
(let ([w (in-context Triv `(immediate ,(- n)))])
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,(asm-sub #f) ,y ,w))
(k x u imm-zero))))]
[else
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u (immediate ,n))
(if (eq? y %zero)
(k x u imm-zero)
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,(asm-add #f) ,x ,u))
(k u y imm-zero)))))]))))))
(define-instruction value (load)
[(op (z ur) (x ur) (y ur) (w ur imm-constant))
(let ([type (info-load-type info)])
(load/store x y w type
(lambda (x y w)
(let ([instr `(set! ,(make-live-info) ,z (asm ,null-info ,(asm-load type) ,x ,y ,w))])
(if (info-load-swapped? info)
(seq
instr
`(set! ,(make-live-info) ,z (asm ,null-info ,(asm-swap type) ,z)))
instr)))))])
(define-instruction effect (store)
[(op (x ur) (y ur) (w ur imm-constant) (z ur))
(let ([type (info-load-type info)])
(load/store x y w type
(lambda (x y w)
(if (info-load-swapped? info)
(let ([u (make-tmp 'unique-bob)])
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,(asm-swap type) ,z))
`(asm ,null-info ,(asm-store type) ,x ,y ,w ,u)))
`(asm ,null-info ,(asm-store type) ,x ,y ,w ,z)))))]))
(define-instruction value (load-single->double)
[(op (x fpur) (y fpmem))
(let ([u (make-tmp 'u 'fp)])
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,asm-fpmove-single ,y))
`(set! ,(make-live-info) ,x (asm ,info ,(asm-fl-cvt 'single->double) ,u))))])
(define-instruction effect (store-double->single)
[(op (x fpmem) (y fpur))
(let ([u (make-tmp 'u 'fp)])
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,(asm-fl-cvt 'double->single) ,y))
`(asm ,info ,asm-fpmove-single ,x ,u)))])
(define-instruction effect (store-single)
[(op (x fpmem) (y fpur))
`(asm ,info ,asm-fpmove-single ,x ,y)])
(define-instruction value (load-single)
[(op (x fpur) (y fpmem))
`(set! ,(make-live-info) ,x (asm ,info ,asm-fpmove-single ,y))])
(define-instruction value (single->double double->single)
[(op (x fpur) (y fpur))
`(set! ,(make-live-info) ,x (asm ,info ,(asm-fl-cvt op) ,y))])
(define-instruction value (fpt)
[(op (x fpur) (y ur))
`(set! ,(make-live-info) ,x (asm ,info ,asm-fpt ,y))])
(define-instruction value (fptrunc)
[(op (x ur) (y fpur))
`(set! ,(make-live-info) ,x (asm ,info ,asm-fptrunc ,y))])
(define-instruction value (fpsingle)
[(op (x fpur) (y fpur)) `(set! ,(make-live-info) ,x (asm ,info ,asm-fpsingle ,y))])
(define-instruction value (fpmove)
[(op (x fpmem) (y fpur)) `(set! ,(make-live-info) ,x ,y)]
[(op (x fpur) (y fpmem fpur)) `(set! ,(make-live-info) ,x ,y)])
(let ()
(define (mem->mem mem new-type)
(nanopass-case (L15d Triv) mem
[(mref ,x0 ,x1 ,imm ,type)
(with-output-language (L15d Lvalue) `(mref ,x0 ,x1 ,imm ,new-type))]))
(define-instruction value (fpcastto)
[(op (x mem) (y fpur)) `(set! ,(make-live-info) ,(mem->mem x 'fp) ,y)]
[(op (x ur) (y fpur)) `(set! ,(make-live-info) ,x (asm ,info ,asm-fpcastto ,y))])
(define-instruction value (fpcastfrom)
[(op (x fpmem) (y ur)) `(set! ,(make-live-info) ,(mem->mem x 'uptr) ,y)]
[(op (x fpur) (y ur)) `(set! ,(make-live-info) ,x (asm ,info ,asm-fpcastfrom ,y))]))
(define-instruction value (fp+ fp- fp/ fp*)
[(op (x fpur) (y fpur) (z fpur))
`(set! ,(make-live-info) ,x (asm ,info ,(asm-fpop-2 op) ,y ,z))])
(define-instruction value (fpsqrt)
[(op (x fpur) (y fpur))
`(set! ,(make-live-info) ,x (asm ,info ,asm-fpsqrt ,y))])
(define-instruction pred (fp= fp< fp<=)
[(op (x fpur) (y fpur))
(let ([info (make-info-condition-code op #f #f)])
(values '() `(asm ,info ,(asm-fp-relop info) ,x ,y)))])
(define-instruction effect (inc-cc-counter)
[(op (x ur) (w unsigned12) (z ur unsigned12))
(let ([u1 (make-tmp 'u1)] [u2 (make-tmp 'u2)])
(seq
`(set! ,(make-live-info) ,u1 (asm ,null-info ,(asm-add #f) ,x ,w))
`(set! ,(make-live-info) ,u2 (asm ,null-info ,asm-kill))
`(asm ,null-info ,asm-inc-cc-counter ,u1 ,z ,u2)))])
(define-instruction effect (inc-profile-counter)
[(op (x mem) (y unsigned12))
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u ,x)
`(set! ,(make-live-info) ,u (asm ,null-info ,(asm-add #f) ,u ,y))
`(set! ,(make-live-info) ,x ,u)))])
(define-instruction value (read-time-stamp-counter)
[(op (z ur)) `(set! ,(make-live-info) ,z (asm ,null-info
;; CNTPCT_EL0
,(asm-read-counter #b11 #b011 #b1110 #b0000 #b001)))])
(define-instruction value (read-performance-monitoring-counter)
[(op (z ur) (x ur)) `(set! ,(make-live-info) ,z (immediate 0))])
;; no kills since we expect to be called when all necessary state has already been saved
(define-instruction value (get-tc)
[(op (z ur))
(safe-assert (eq? z %Cretval))
(let ([ulr (make-precolored-unspillable 'ulr %lr)])
(seq
`(set! ,(make-live-info) ,ulr (asm ,null-info ,asm-kill))
`(set! ,(make-live-info) ,z (asm ,info ,asm-get-tc ,ulr))))])
(define-instruction value activate-thread
[(op (z ur))
(safe-assert (eq? z %Cretval))
(let ([ulr (make-precolored-unspillable 'ulr %lr)])
(seq
`(set! ,(make-live-info) ,ulr (asm ,null-info ,asm-kill))
`(set! ,(make-live-info) ,z (asm ,info ,asm-activate-thread ,ulr))))])
(define-instruction effect deactivate-thread
[(op)
(let ([ulr (make-precolored-unspillable 'ulr %lr)])
(seq
`(set! ,(make-live-info) ,ulr (asm ,null-info ,asm-kill))
`(asm ,info ,asm-deactivate-thread ,ulr)))])
(define-instruction effect unactivate-thread
[(op (x ur))
(safe-assert (eq? x %Carg1))
(let ([ulr (make-precolored-unspillable 'ulr %lr)])
(seq
`(set! ,(make-live-info) ,ulr (asm ,null-info ,asm-kill))
`(asm ,info ,asm-unactivate-thread ,x ,ulr)))])
(define-instruction value (asmlibcall)
[(op (z ur))
(if (info-asmlib-save-ra? info)
`(set! ,(make-live-info) ,z (asm ,info ,(asm-library-call (info-asmlib-libspec info) #t) ,(info-kill*-live*-live* info) ...))
(let ([ulr (make-precolored-unspillable 'ulr %lr)])
(seq
`(set! ,(make-live-info) ,ulr (asm ,null-info ,asm-kill))
`(set! ,(make-live-info) ,z (asm ,info ,(asm-library-call (info-asmlib-libspec info) #f) ,ulr ,(info-kill*-live*-live* info) ...)))))])
(define-instruction effect (asmlibcall!)
[(op)
(if (info-asmlib-save-ra? info)
(let ([ulr (make-precolored-unspillable 'ulr %lr)])
`(asm ,info ,(asm-library-call! (info-asmlib-libspec info) #t) ,(info-kill*-live*-live* info) ...))
(let ([ulr (make-precolored-unspillable 'ulr %lr)])
(seq
`(set! ,(make-live-info) ,ulr (asm ,null-info ,asm-kill))
`(asm ,info ,(asm-library-call! (info-asmlib-libspec info) #f) ,ulr ,(info-kill*-live*-live* info) ...))))])
(safe-assert (reg-callee-save? %tc)) ; no need to save-restore
(define-instruction effect (c-simple-call)
[(op)
(if (info-c-simple-call-save-ra? info)
`(asm ,info ,(asm-c-simple-call (info-c-simple-call-entry info) #t))
(let ([ulr (make-precolored-unspillable 'ulr %lr)])
(seq
`(set! ,(make-live-info) ,ulr (asm ,null-info ,asm-kill))
`(asm ,info ,(asm-c-simple-call (info-c-simple-call-entry info) #f) ,ulr))))])
(define-instruction pred (eq? u< < > <= >=)
[(op (y unsigned12) (x ur))
(let ([info (if (eq? op 'eq?) info-cc-eq (make-info-condition-code op #t #t))])
(values '() `(asm ,info ,(asm-relop info #f) ,x ,y)))]
[(op (y neg-unsigned12) (x ur))
(let ([info (if (eq? op 'eq?) info-cc-eq (make-info-condition-code op #t #t))])
(values '() `(asm ,info ,(asm-relop info #t) ,x ,y)))]
[(op (x ur) (y ur unsigned12))
(let ([info (if (eq? op 'eq?) info-cc-eq (make-info-condition-code op #f #t))])
(values '() `(asm ,info ,(asm-relop info #f) ,x ,y)))]
[(op (x ur) (y neg-unsigned12))
(let ([info (if (eq? op 'eq?) info-cc-eq (make-info-condition-code op #f #t))])
(values '() `(asm ,info ,(asm-relop info #t) ,x ,y)))])
(define-instruction pred (condition-code)
[(op) (values '() `(asm ,info ,(asm-condition-code info)))])
(define-instruction pred (type-check?)
[(op (x ur) (mask funkymask ur) (type unsigned12 ur))
(let ([tmp (make-tmp 'u)])
(values
(with-output-language (L15d Effect)
`(set! ,(make-live-info) ,tmp (asm ,null-info ,(asm-logand #f) ,x ,mask)))
`(asm ,info-cc-eq ,asm-eq ,tmp ,type)))])
(define-instruction pred (logtest log!test)
[(op (x funkymask) (y ur))
(values '() `(asm ,info-cc-eq ,(asm-logtest (eq? op 'log!test) info-cc-eq) ,y ,x))]
[(op (x ur) (y ur funkymask))
(values '() `(asm ,info-cc-eq ,(asm-logtest (eq? op 'log!test) info-cc-eq) ,x ,y))])
(let ()
(define lea->reg
(lambda (x y w k)
(with-output-language (L15d Effect)
(define add-offset
(lambda (r)
(let ([i (nanopass-case (L15d Triv) w [(immediate ,imm) imm])])
(cond
[(eqv? i 0) (k r)]
[(unsigned12? i)
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,(asm-add #f) ,r ,w))
(k u)))]
[else
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u ,w)
`(set! ,(make-live-info) ,u (asm ,null-info ,(asm-add #f) ,r ,u))
(k u)))]))))
(if (eq? y %zero)
(add-offset x)
(let ([u (make-tmp 'u)])
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,(asm-add #f) ,x ,y))
(add-offset u)))))))
;; NB: compiler implements init-lock! and unlock! as word store of zero
(define-instruction pred (lock!)
[(op (x ur) (y ur) (w imm-constant))
(let ([u (make-tmp 'u)]
[u2 (make-tmp 'u2)])
(values
(lea->reg x y w
(lambda (r)
(with-output-language (L15d Effect)
(seq
`(set! ,(make-live-info) ,u (asm ,null-info ,asm-kill))
`(set! ,(make-live-info) ,u2 (asm ,null-info ,asm-kill))
`(asm ,null-info ,asm-lock ,r ,u ,u2)))))
`(asm ,info-cc-eq ,asm-eq ,u (immediate 0))))])
(define-instruction effect (locked-incr! locked-decr!)
[(op (x ur) (y ur) (w imm-constant))
(lea->reg x y w
(lambda (r)
(let ([u1 (make-tmp 'u1)] [u2 (make-tmp 'u2)])
(seq
`(set! ,(make-live-info) ,u1 (asm ,null-info ,asm-kill))
`(set! ,(make-live-info) ,u2 (asm ,null-info ,asm-kill))
`(asm ,null-info ,(asm-lock+/- op) ,r ,u1 ,u2)))))])
(define-instruction effect (cas)
[(op (x ur) (y ur) (w imm-constant) (old ur) (new ur))
(lea->reg x y w
(lambda (r)
(let ([u1 (make-tmp 'u1)] [u2 (make-tmp 'u2)])
(seq
`(set! ,(make-live-info) ,u1 (asm ,null-info ,asm-kill))
`(set! ,(make-live-info) ,u2 (asm ,null-info ,asm-kill))
`(asm ,info ,asm-cas ,r ,old ,new ,u1 ,u2)))))]))
(define-instruction effect (store-store-fence)
[(op)
`(asm ,info ,(asm-fence 'store-store))])
(define-instruction effect (acquire-fence)
[(op)
`(asm ,info ,(asm-fence 'acquire))])
(define-instruction effect (release-fence)
[(op)
`(asm ,info ,(asm-fence 'release))])
(define-instruction effect (pause)
;; NB: use sqrt or something like that?
[(op) '()])
(define-instruction effect (debug)
[(op)
`(asm ,info ,asm-debug)])
(define-instruction effect (c-call)
[(op (x ur))
(let ([ulr (make-precolored-unspillable 'ulr %lr)])
(seq
`(set! ,(make-live-info) ,ulr (asm ,null-info ,asm-kill))
`(asm ,info ,asm-indirect-call ,x ,ulr ,(info-kill*-live*-live* info) ...)))])
(define-instruction effect (pop-multiple)
[(op) `(asm ,info ,(asm-pop-multiple (info-kill*-kill* info)))])
(define-instruction effect (push-multiple)
[(op) `(asm ,info ,(asm-push-multiple (info-kill*-live*-live* info)))])
(define-instruction effect (pop-fpmultiple)
[(op) `(asm ,info ,(asm-pop-fpmultiple (info-kill*-kill* info)))])
(define-instruction effect (push-fpmultiple)
[(op) `(asm ,info ,(asm-push-fpmultiple (info-kill*-live*-live* info)))])
(define-instruction effect save-flrv
[(op) `(asm ,info ,(asm-push-fpmultiple (list %Cfpretval)))])
(define-instruction effect restore-flrv
[(op) `(asm ,info ,(asm-pop-fpmultiple (list %Cfpretval)))])
(define-instruction effect (invoke-prelude)
[(op) `(set! ,(make-live-info) ,%tc ,%Carg1)])
)
;;; SECTION 3: assembler
(module asm-module (; required exports
asm-move asm-move/extend asm-load asm-store asm-swap asm-library-call asm-library-call! asm-library-jump
asm-mul asm-smulh asm-div asm-add asm-sub asm-logand asm-logor asm-logxor
asm-pop-multiple asm-shiftop asm-logand asm-lognot asm-cmp/asr63 asm-popcount
asm-logtest asm-fp-relop asm-relop asm-push-multiple asm-push-fpmultiple asm-pop-fpmultiple
asm-indirect-jump asm-literal-jump
asm-direct-jump asm-return-address asm-jump asm-conditional-jump
asm-indirect-call asm-condition-code
asm-fpmove-single asm-fl-cvt asm-fpt asm-fpmove asm-fpcastto asm-fpcastfrom
asm-fptrunc asm-fpsingle
asm-lock asm-lock+/- asm-cas asm-fence
asm-fpop-2 asm-fpsqrt asm-c-simple-call
asm-return asm-c-return asm-size
asm-enter asm-foreign-call asm-foreign-callable
asm-debug
asm-read-counter
asm-inc-cc-counter
signed9? unsigned12? aligned-offset? funkymask shifted16
; threaded version specific
asm-get-tc
asm-activate-thread asm-deactivate-thread asm-unactivate-thread
; machine dependent exports
asm-kill)
(define ax-register?
(case-lambda
[(x) (record-case x [(reg) r #t] [else #f])]
[(x reg) (record-case x [(reg) r (eq? r reg)] [else #f])]))
(define-who ax-ea-reg-code
(lambda (ea)
(record-case ea
[(reg) r (reg-mdinfo r)]
[else (sorry! who "ea=~s" ea)])))
(define ax-reg?
(lambda (ea)
(record-case ea
[(reg) ignore #t]
[else #f])))
(define ax-imm?
(lambda (ea)
(record-case ea
[(imm) ignore #t]
[else #f])))
(define-who ax-imm-data
(lambda (ea)
(record-case ea
[(imm) (n) n]
[else (sorry! who "ax-imm-data ea=~s" ea)])))
; define-op sets up assembly op macros--
; the opcode and all other expressions are passed to the specified handler--
(define-syntax define-op
(lambda (x)
(syntax-case x ()
[(k op handler e ...)
(with-syntax ([op (construct-name #'k "asmop-" #'op)])
#'(define-syntax op
(syntax-rules ()
[(_ mneu arg (... ...))
(handler 'mneu e ... arg (... ...))])))])))
(define-syntax emit
(lambda (x)
(syntax-case x ()
[(k op x ...)
(with-syntax ([emit-op (construct-name #'k "asmop-" #'op)])
#'(emit-op op x ...))])))
;;; note that the assembler isn't clever--you must be very explicit about
;;; which flavor you want, and there are a few new varieties introduced
;;; (commented-out opcodes are not currently used by the assembler--
;;; spaces are left to indicate possible size extensions)
(define-op movzi movzi-op #b10) ; 16-bit immediate, shifted
(define-op movki movzi-op #b11) ; 16-bit immediate, shifted
(define-op movi movi-op) ; immediate encoded as a mask
(define-op addi add-imm-op #b0) ; selector is at bit 30 (op)
(define-op subi add-imm-op #b1)
(define-op andi logical-imm-op #b00)
(define-op orri logical-imm-op #b01)
(define-op eori logical-imm-op #b10)
(define-op add binary-op #b0)
(define-op sub binary-op #b1)
(define-op and logical-op #b00)
(define-op orr logical-op #b01)
(define-op eor logical-op #b10)
(define-op cmp cmp-op #b1101011 #b00 0)
(define-op tst cmp-op #b1101010 #b00 0)
(define-op cmp/asr63 cmp-op #b1101011 #b10 63)
(define-op cmpi cmp-imm-op #b1) ; selector is at bit 30 (op)
(define-op cmni cmp-imm-op #b0)
(define-op tsti logical-imm-op #b11 #f `(reg . ,%real-zero))
(define-op mov mov-op #b1 #b0) ; selectors are a bit 31 (sf) and 21 (N)
(define-op movw mov-op #b0 #b0)
(define-op mvn mov-op #b1 #b1)
(define-op lsli shifti-op #b10 'l) ; selector is at bit 29 (opc)
(define-op lsri shifti-op #b10 'r)
(define-op asri shifti-op #b00 'r)
(define-op lsl shift-op #b00) ; selector is at bit 10 (op2)
(define-op lsr shift-op #b01)
(define-op asr shift-op #b10)
(define-op sxtb extend-op #b100 #b1 #b000111) ; selectors are at bits 29 (sfc+opc), 22 (N), and 10 (imms)
(define-op sxth extend-op #b100 #b1 #b001111)
(define-op sxtw extend-op #b100 #b1 #b011111)
(define-op uxtb extend-op #b010 #b0 #b000111)
(define-op uxth extend-op #b010 #b0 #b001111)
(define-op mul mul-op #b000) ; selector is at bit 21
(define-op smulh mul-op #b010)
(define-op sdiv div-op)
(define-op cnt cnt-op)
(define-op addv.b addv.b-op)
;; scaled variants (offset must be aligned):
(define-op ldri load-imm-op 3 #b11 #b0 #b01) ; selectors are at bits 30 (size), 26, and 22 (opc)
(define-op ldrbi load-imm-op 0 #b00 #b0 #b01)
(define-op ldrhi load-imm-op 1 #b01 #b0 #b01)
(define-op ldrwi load-imm-op 2 #b10 #b0 #b01)
(define-op ldrfi load-imm-op 3 #b11 #b1 #b01)
(define-op ldrfsi load-imm-op 2 #b10 #b1 #b01) ; single-precision
(define-op ldrsbi load-imm-op 0 #b00 #b0 #b10)
(define-op ldrshi load-imm-op 1 #b01 #b0 #b10)
(define-op ldrswi load-imm-op 2 #b10 #b0 #b10)
(define-op stri load-imm-op 3 #b11 #b0 #b00)
(define-op strbi load-imm-op 0 #b00 #b0 #b00)
(define-op strhi load-imm-op 1 #b01 #b0 #b00)
(define-op strwi load-imm-op 2 #b10 #b0 #b00)
(define-op strfi load-imm-op 3 #b11 #b1 #b00)
(define-op strfsi load-imm-op 2 #b10 #b1 #b00) ; single-precision
;; unscaled variants (offset must be signed9):
(define-op lduri load-unscaled-imm-op #b11 #b0 #b01) ; selectors are at bits 30 (size), 26, and 22 (opc)
(define-op ldurbi load-unscaled-imm-op #b00 #b0 #b01)
(define-op ldurhi load-unscaled-imm-op #b01 #b0 #b01)
(define-op ldurwi load-unscaled-imm-op #b10 #b0 #b01)
(define-op ldurfi load-unscaled-imm-op #b11 #b1 #b01)
(define-op ldurfsi load-unscaled-imm-op #b10 #b1 #b01) ; single-precision
(define-op ldursbi load-unscaled-imm-op #b00 #b0 #b10)
(define-op ldurshi load-unscaled-imm-op #b01 #b0 #b10)
(define-op ldurswi load-unscaled-imm-op #b10 #b0 #b10)
(define-op sturi load-unscaled-imm-op #b11 #b0 #b00)
(define-op sturbi load-unscaled-imm-op #b00 #b0 #b00)
(define-op sturhi load-unscaled-imm-op #b01 #b0 #b00)
(define-op sturwi load-unscaled-imm-op #b10 #b0 #b00)
(define-op sturfi load-unscaled-imm-op #b11 #b1 #b00)
(define-op sturfsi load-unscaled-imm-op #b10 #b1 #b00) ; single-precision
(define-op ldr load-op #b11 #b0 #b01) ; selectors are at bits 30 (size), 26, and 22 (opc)
(define-op ldrw load-op #b10 #b0 #b01)
(define-op ldrh load-op #b01 #b0 #b01)
(define-op ldrb load-op #b00 #b0 #b01)
(define-op ldrf load-op #b11 #b1 #b01)
(define-op ldrfs load-op #b10 #b1 #b01)
(define-op ldrsw load-op #b10 #b0 #b10)
(define-op ldrsh load-op #b01 #b0 #b10)
(define-op ldrsb load-op #b00 #b0 #b10)
(define-op str load-op #b11 #b0 #b00)
(define-op strw load-op #b10 #b0 #b00)
(define-op strh load-op #b01 #b0 #b00)
(define-op strb load-op #b00 #b0 #b00)
(define-op strf load-op #b11 #b1 #b00)
(define-op strfs load-op #b10 #b1 #b00)
(define-op ldr/postidx load-idx-op #b01 #b0 #b01) ; selectors are at bits 22 (opc), 26, and 10
(define-op str/preidx load-idx-op #b00 #b0 #b11)
(define-op ldrf/postidx load-idx-op #b01 #b1 #b01)
(define-op strf/preidx load-idx-op #b00 #b1 #b11)
(define-op ldrp/postidx loadp-idx-op #b10 #b0 #b001 #b1) ; selectors are at bits 30 (opc), 26, 23, and 22 (L)
(define-op strp/preidx loadp-idx-op #b10 #b0 #b011 #b0)
(define-op ldrpf/postidx loadp-idx-op #b01 #b1 #b001 #b1)
(define-op strpf/preidx loadp-idx-op #b01 #b1 #b011 #b0)
(define-op ldxr ldxr-op #b1 `(reg . ,%real-zero))
(define-op stxr ldxr-op #b0)
(define-op dmbst dmb-op #b1110)
(define-op dmbish dmb-op #b1011)
(define-op dmbishld dmb-op #b1001)
(define-op dmbishst dmb-op #b1010)
(define-op bnei branch-imm-op (ax-cond 'ne))
(define-op beqi branch-imm-op (ax-cond 'eq))
(define-op brai branch-imm-op (ax-cond 'al))
(define-op br branch-reg-op #b00)
(define-op blr branch-reg-op #b01)
(define-op b branch-always-label-op)
(define-op beq branch-label-op (ax-cond 'eq))
(define-op bne branch-label-op (ax-cond 'ne))
(define-op blt branch-label-op (ax-cond 'lt))
(define-op ble branch-label-op (ax-cond 'le))
(define-op bgt branch-label-op (ax-cond 'gt))
(define-op bge branch-label-op (ax-cond 'ge))
(define-op bcc branch-label-op (ax-cond 'cc))
(define-op bcs branch-label-op (ax-cond 'cs))
(define-op bvc branch-label-op (ax-cond 'vc))
(define-op bvs branch-label-op (ax-cond 'vs))
(define-op bls branch-label-op (ax-cond 'ls))
(define-op bhi branch-label-op (ax-cond 'hi))
(define-op adr adr-op)
(define-op ret ret-op)
(define-op fcvt.s->d fcvt-op #b00 #b01)
(define-op fcvt.d->s fcvt-op #b01 #b00)
(define-op fcvtzs fdcvt-op #b11 #b000) ; selectors are at bits 19 (mode) and 1 6(opcode)
(define-op scvtf fdcvt-op #b00 #b010)
(define-op fmov fmov-op #b0 #b000 #b1) ; selectors are at bits 31, 16, and 14
(define-op fmov.f->g fmov-op #b1 #b110 #b0)
(define-op fmov.g->f fmov-op #b1 #b111 #b0)
(define-op fcmp fcmp-op)
(define-op rev rev-op #b11) ; selector is at bit 10 (opc)
(define-op rev16 rev-op #b01)
(define-op rev32 rev-op #b10)
(define-op mrs mrs-op)
(define-op und und-op)
(define-op fadd f-arith-op #b0010) ; selector is at bit 12
(define-op fsub f-arith-op #b0011)
(define-op fmul f-arith-op #b0000)
(define-op fdiv f-arith-op #b0001)
(define-op fsqrt fsqrt-op)
(define movzi-op
(lambda (op opc dest imm shift code*)
(emit-code (op dest imm shift code*)
[31 #b1]
[29 opc]
[23 #b100101]
[21 shift] ; `shift` is implicitly multiplied by 16
[5 imm]
[0 (ax-ea-reg-code dest)])))
(define movi-op
(lambda (op dest imm n+immr+imms code*)
(let ([n (car n+immr+imms)]
[immr (cadr n+immr+imms)]
[imms (caddr n+immr+imms)])
(emit-code (op dest imm n+immr+imms code*)
[23 #b101100100]
[22 n]
[16 immr]
[10 imms]
[5 #b11111]
[0 (ax-ea-reg-code dest)]))))
(define add-imm-op
(lambda (op opcode set-cc? dest src imm code*)
(emit-code (op dest src imm (and set-cc? #t) code*)
[31 #b1]
[30 opcode]
[29 (if set-cc? #b1 #b0)]
[24 #b10001]
[22 #b00] ; shift
[10 imm]
[5 (ax-ea-reg-code src)]
[0 (ax-ea-reg-code dest)])))
(define logical-imm-op
(lambda (op opcode set-cc? dest src imm code*)
(safe-assert (not set-cc?)) ; but opcode may imply setting condition codes