hcp_port

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "mip_brust.h"
#include "xil_io.h"


//#define BRAM_BASE XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR
//#define BRAM_HIGH XPAR_AXI_BRAM_CTRL_0_S_AXI_HIGHADDR

#define BASEADDR       XPAR_MIP_BRUST_0_S00_AXI_BASEADDR
#define CMD_CNTRL      MIP_BRUST_S00_AXI_SLV_REG0_OFFSET
#define ADRRESS        MIP_BRUST_S00_AXI_SLV_REG1_OFFSET
#define WRITE_DATA     MIP_BRUST_S00_AXI_SLV_REG2_OFFSET
#define READ_DATA      MIP_BRUST_S00_AXI_SLV_REG3_OFFSET
#define READ_LET       MIP_BRUST_S00_AXI_SLV_REG4_OFFSET
#define WRITE_LET      MIP_BRUST_S00_AXI_SLV_REG5_OFFSET


#define WRITE_COMMAND 0x0000CDAC
#define READ_COMMAND  0xCDAC2020


#define No_of_TXN 50
#define DDR_ADDRESS 0x4000

#define BRAM_INITIAL_VAL 0xCDAC2000
#define DDR_INITIAL_VAL  0xCDAC5000

int wait_data ()
{
	MIP_BRUST_mWriteReg(BASEADDR, READ_DATA, 0);

  	int value = 0;
    while(!value)
	     { value = MIP_BRUST_mReadReg(BASEADDR, MIP_BRUST_S00_AXI_SLV_REG3_OFFSET ); }

    return 0;
}



int main()
{
    init_platform();
  //  int value=0;
   // Xil_SetTlbAttributes(0xFFFFC000, 0x10002);


  //  int t_wd;
  //  int t_rd;
  //  int n;


    print(" Hello World, Testing MIP (MY IP) Read and Write functionality \n\r");
/*
   for(int i=0; i<4; ++i) {

	   MIP_BRUST_mWriteReg(BASEADDR,0+4*i, 0xCDAC2020+2*i);
   }

   for(int i=0; i<4; ++i) {
    value = MIP_BRUST_mReadReg(BASEADDR,0+4*i);
    printf("Value : 0x%x ", value);
    printf("\n");
   }
*/

/*
    printf("\n");
	xil_printf("Writing %d Words to Block Memory Region : 0x%x - 0x%x:", No_of_TXN, BRAM_BASE, BRAM_HIGH); printf("\n");
	volatile uint32_t *ptr = (volatile uint32_t*)(BRAM_BASE);
	for (int h = 0; h < No_of_TXN; h++) {
		*ptr++ = 0x0;
	}

	//xil_printf("Writing %d Words to Block Memory Region through MIP with initial value 0x%x ", No_of_TXN, BRAM_INITIAL_VAL); printf("\n");
	xil_printf("Writing %d Words to BRAM through MIP with initial value 0x%x ", No_of_TXN, BRAM_INITIAL_VAL); printf("\n");

	for (int h = 0; h < No_of_TXN; h++) {

	    MIP_BRUST_mWriteReg(BASEADDR, ADRRESS, BRAM_BASE+4*h); //Address
	    MIP_BRUST_mWriteReg(BASEADDR, WRITE_DATA, BRAM_INITIAL_VAL+h);  // DATA
	    MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, WRITE_COMMAND);  // Initiate TXN

	}

       printf(" Reading the Block Memory Region through Processor");  printf("\n");
	   volatile uint32_t *ptr2 = (volatile uint32_t*)(BRAM_BASE);
	   for (int h = 0; h < No_of_TXN; h++)
	   {
	   		xil_printf(" Value is   0x%p: %x", ptr2, *ptr2); printf("\n");
	   		*ptr2++;
	   	}


    print(" Reading the Block Memory Region through MIP");  printf("\n");
    for (int h = 0; h < No_of_TXN; h++)
	 {
	    MIP_BRUST_mWriteReg(BASEADDR, ADRRESS, BRAM_BASE+4*h); //Address
	    MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, READ_COMMAND);  // Initiate TXN
	    wait_data ();
	    value = MIP_BRUST_mReadReg(BASEADDR, READ_DATA);
	    printf("Value at 0x%x : 0x%x ",BRAM_BASE+4*h, value);

	    printf("\n");

	 }

    printf("\n");   printf("\n");
    xil_printf("Writing %d Words to DDR through MIP at 0x%x with initial value 0x%x ", No_of_TXN, DDR_ADDRESS, DDR_INITIAL_VAL); printf("\n");
	for (int h = 0; h < No_of_TXN; h++) {

	    MIP_BRUST_mWriteReg(BASEADDR, ADRRESS, DDR_ADDRESS+4*h); //Address
	    MIP_BRUST_mWriteReg(BASEADDR, WRITE_DATA, DDR_INITIAL_VAL+h);  // DATA
	    MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, WRITE_COMMAND);  // Initiate TXN

	}

	printf(" Reading the DDR Region through Processor");  printf("\n");
	   for (int h = 0; h < No_of_TXN; h++)
	   {
		    value = Xil_In32(DDR_ADDRESS+4*h);
	        printf("DDR_Value at  0x%x : 0x%x ",DDR_ADDRESS+4*h, value);  printf("\n");

	   }


	    print(" Reading the DDR Region through MIP");  printf("\n");
	    for (int h = 0; h < No_of_TXN; h++)
		 {
		    MIP_BRUST_mWriteReg(BASEADDR, ADRRESS, DDR_ADDRESS+4*h); //Address
		    MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, READ_COMMAND);  // Initiate TXN
		    wait_data ();
		    value = MIP_BRUST_mReadReg(BASEADDR, READ_DATA);
		    printf("DDR_Value at 0x%x : 0x%x ",DDR_ADDRESS+4*h, value);

		    printf("\n");

		 }

*/

/*
	for (int h = 0; h < 10000; h++) {

	    MIP_BRUST_mWriteReg(BASEADDR, ADRRESS, DDR_ADDRESS+4*h); //Address
	    MIP_BRUST_mWriteReg(BASEADDR, WRITE_DATA, DDR_INITIAL_VAL+h);  // DATA
	    MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, WRITE_COMMAND);  // Initiate TXN

	}

*/


/*
	MIP_BRUST_mWriteReg(BASEADDR, ADRRESS, DDR_ADDRESS+500); //Address
	MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, READ_COMMAND);  // Initiate TXN
	wait_data ();
	value = MIP_BRUST_mReadReg(BASEADDR, READ_DATA);
	printf("DDR_Value at 0x%x : 0x%x \n",DDR_ADDRESS+500, value);

	value = MIP_BRUST_mReadReg(BASEADDR, READ_LET);
	printf("READ Latency_Value at: 0x%x \n", value);


*/
/*
    t_wd = 0;
    value =0;
    n = 1000;

for(int i=0; i<n; ++i)
{
		MIP_BRUST_mWriteReg(BASEADDR, ADRRESS, DDR_ADDRESS+4*i); //Address
		MIP_BRUST_mWriteReg(BASEADDR, WRITE_DATA, DDR_INITIAL_VAL+i);  // DATA
		MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, WRITE_COMMAND);  // Initiate TXN


		value = MIP_BRUST_mReadReg(BASEADDR, WRITE_LET);
		while(!value)
			value = MIP_BRUST_mReadReg(BASEADDR, WRITE_LET);

		t_wd += value;

		printf(" Write Latency_Value at: 0x%x \n", value);
}

printf("Average Write Latency_Value at: 0x%x \n\n\n", t_wd/n);

t_rd = 0;
value = 0;

for(int i=0; i<n; ++i)
{
		MIP_BRUST_mWriteReg(BASEADDR, ADRRESS, DDR_ADDRESS+4*i); //Address
		MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, READ_COMMAND);  // Initiate TXN
		wait_data ();
		value = MIP_BRUST_mReadReg(BASEADDR, READ_DATA);
		printf("DDR_Value at 0x%x : 0x%x \n",DDR_ADDRESS+4*i, value);

		value = MIP_BRUST_mReadReg(BASEADDR, READ_LET);

		t_rd = t_rd+value;

	//	  printf("\n ***** Testing is Ended ***** \n ");
}

printf("Average READ Latency_Value at: 0x%x \n",t_rd/n);


	    printf("\n ***** Testing is Ended ***** \n ");

*/
    int value=0;
    int t_wd=0;
    int n = 100;

for(int i=0; i<n; ++i)
{
	MIP_BRUST_mWriteReg(BASEADDR, ADRRESS, DDR_ADDRESS+(4*i*256)); //Address
	MIP_BRUST_mWriteReg(BASEADDR, WRITE_DATA, DDR_INITIAL_VAL+i);  // DATA
	MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, WRITE_COMMAND);  // Initiate TXN

	value = MIP_BRUST_mReadReg(BASEADDR, WRITE_LET);
	while(!value)
		value = MIP_BRUST_mReadReg(BASEADDR, WRITE_LET);

	printf(" Write Latency_Value at: %d \n", value);
	t_wd += value;

}
	printf(" Total Write Latency_Value at: 0x%x \n", t_wd);


    printf("\n ***** For READ ***** \n ");


	int t_rd = 0;
	value = 0;

for(int i=0; i<n; ++i)
{


	MIP_BRUST_mWriteReg(BASEADDR, ADRRESS, DDR_ADDRESS+(4*i*256)); //Address
	MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, READ_COMMAND);  // Initiate TXN
	wait_data ();
	value = MIP_BRUST_mReadReg(BASEADDR, READ_DATA);
//	printf("DDR_Value at 0x%x : 0x%x \n",DDR_ADDRESS+4*i*256, value);

	value = MIP_BRUST_mReadReg(BASEADDR, READ_LET);
	//while(!value)
		//value = MIP_BRUST_mReadReg(BASEADDR, WRITE_LET);

	printf(" read Latency_Value at: %d \n", value);
	t_rd += value;

}
	printf(" Total Read Latency_Value at: 0x%x \n", t_rd);



    printf("\n ***** Testing is Ended ***** \n ");

/*
     	MIP_BRUST_mWriteReg(BASEADDR, WRITE_DATA, DDR_INITIAL_VAL);  // DATA

		MIP_BRUST_mWriteReg(BASEADDR, CMD_CNTRL, WRITE_COMMAND);  // Initiate TXN
		printf("\n ***** Testing is Ended ***** \n ");

*/

    cleanup_platform();
    return 0;
}