-
Notifications
You must be signed in to change notification settings - Fork 20
/
registers.v
2203 lines (2104 loc) · 87.6 KB
/
registers.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// This file is part of the vicii-kawari distribution
// (https://github.com/randyrossi/vicii-kawari)
// Copyright (c) 2022 Randy Rossi.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, version 3.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
`timescale 1ns / 1ps
`include "common.vh"
module registers
#(
parameter ram_width = `VIDEO_RAM_WIDTH,
ram_hi_width = `VIDEO_RAM_HI_WIDTH
)
(
output reg rst = 1'b1,
`ifdef HIRES_RESET
input cpu_reset_i,
`endif
input standard_sw,
input clk_dot4x,
input clk_dvi,
input clk_phi,
input [15:0] phi_phase_start,
input ras,
input ce,
input rw,
input aec,
input [5:0] adi,
input [7:0] dbi,
input [8:0] raster_line,
input irq,
input ilp,
input immc,
input imbc,
input irst,
input [7:0] sprite_m2m,
input [7:0] sprite_m2d,
input [7:0] lpx,
input [7:0] lpy,
output reg [3:0] ec,
output reg [3:0] b0c,
output reg [3:0] b1c,
output reg [3:0] b2c,
output reg [3:0] b3c,
output reg [2:0] xscroll,
output reg [2:0] yscroll,
output reg csel,
output reg rsel,
output reg den,
output reg bmm,
output reg ecm,
output reg mcm,
output reg irst_clr,
output reg imbc_clr,
output reg immc_clr,
output reg ilp_clr,
output reg [8:0] raster_irq_compare,
output reg [7:0] sprite_en,
output reg [7:0] sprite_xe,
output reg [7:0] sprite_ye,
output reg [7:0] sprite_pri,
output reg [7:0] sprite_mmc,
output reg [3:0] sprite_mc0,
output reg [3:0] sprite_mc1,
output [71:0] sprite_x_o,
output [63:0] sprite_y_o,
output [31:0] sprite_col_o,
output reg m2m_clr,
output reg m2d_clr,
output reg handle_sprite_crunch,
output reg [7:0] dbo,
output reg [7:0] last_bus,
`ifdef WIV_EXTENSIONS
output reg [3:0] cb,
`else
output reg [2:0] cb,
`endif
output reg [3:0] vm,
output reg elp,
output reg emmc,
output reg embc,
output reg erst,
// pixel_color3 is from native res pixel sequencer and should be used
// to look up luma/phase/chroma values
input [3:0] pixel_color3,
// pixel_color4 is from the scan doubler and should be used to look up
// RGB color register ram, 4 bit address.
`ifdef NEED_RGB
input [3:0] pixel_color4,
input half_bright,
input active,
output reg[5:0] red,
output reg[5:0] green,
output reg[5:0] blue,
// Current settings
output reg last_raster_lines, // for dvi/vga only
output reg last_is_native_y, // for dvi/vga only
output reg last_is_native_x, // for dvi/vga only
output reg last_enable_csync, // for dvi/vga only
output reg last_hpolarity, // for vga only
output reg last_vpolarity, // for vga only
`endif
`ifdef GEN_LUMA_CHROMA
output reg white_line = 1'b1,
output reg ntsc_50 = 1'b0,
output reg pal_60 = 1'b0,
output reg [5:0] lumareg_o,
output reg [7:0] phasereg_o,
output reg [3:0] amplitudereg_o,
`endif
`ifdef WITH_EXTENSIONS
`ifdef HAVE_FLASH
output reg flash_s = 1'b1,
`endif
`ifdef HAVE_EEPROM
input cfg_reset,
output reg eeprom_s = 1'b1,
`endif
input spi_lock,
input extensions_lock,
input persistence_lock,
`ifdef GEN_LUMA_CHROMA
`ifdef CONFIGURABLE_LUMAS
output reg [5:0] blanking_level,
output reg [3:0] burst_amplitude,
`endif
`endif
`ifdef CONFIGURABLE_TIMING
output reg timing_change,
output reg [7:0] timing_h_blank_ntsc,
output reg [7:0] timing_h_fporch_ntsc,
output reg [7:0] timing_h_sync_ntsc,
output reg [7:0] timing_h_bporch_ntsc,
output reg [7:0] timing_v_blank_ntsc,
output reg [7:0] timing_v_fporch_ntsc,
output reg [7:0] timing_v_sync_ntsc,
output reg [7:0] timing_v_bporch_ntsc,
output reg [7:0] timing_h_blank_pal,
output reg [7:0] timing_h_fporch_pal,
output reg [7:0] timing_h_sync_pal,
output reg [7:0] timing_h_bporch_pal,
output reg [7:0] timing_v_blank_pal,
output reg [7:0] timing_v_fporch_pal,
output reg [7:0] timing_v_sync_pal,
output reg [7:0] timing_v_bporch_pal,
`endif
`ifdef HIRES_MODES
input [ram_width-1:0] video_ram_addr_b,
output [7:0] video_ram_data_out_b,
output reg [2:0] hires_char_pixel_base,
output reg [3:0] hires_matrix_base,
output reg [3:0] hires_color_base,
output reg hires_enabled,
output reg hires_allow_bad,
output reg [2:0] hires_mode,
output reg [7:0] hires_cursor_hi,
output reg [7:0] hires_cursor_lo,
`endif
`ifdef WITH_SPI
output reg spi_d = 1'b1,
input spi_q,
output reg spi_c = 1'b1,
`endif
`ifdef WITH_RAM
input [3:0] cycle_type,
input idle,
output reg dma_done = 1'b1,
output reg [15:0] dma_addr,
`endif
`endif // WITH_EXTENSIONS
`ifdef WIV_EXTENSIONS
output reg wiv_cre = 1'b0, // VIC-WIV control registers read enable
output reg wiv_xmp = 1'b0, // VIC-WIV extended memory pointers: enable all bits of register $18
output reg wiv_dvb = 1'b0, // VIC-WIV disable vertical border
output reg wiv_dmb = 1'b0, // VIC-WIV disable main border
output reg [7:4] wiv_cr3_unused = 4'b0000,
output reg [7:0] wiv_cr4_unused = 8'b00000000,
`endif
output reg rw_ctl = 1'b0,
output reg [1:0] chip
);
// 2D arrays that need to be flattened for output
reg [8:0] sprite_x[0:`NUM_SPRITES - 1];
reg [7:0] sprite_y[0:`NUM_SPRITES - 1];
reg [3:0] sprite_col[0:`NUM_SPRITES - 1];
integer n;
// Handle flattening here
assign sprite_x_o = {sprite_x[0], sprite_x[1], sprite_x[2], sprite_x[3], sprite_x[4], sprite_x[5], sprite_x[6], sprite_x[7]};
assign sprite_y_o = {sprite_y[0], sprite_y[1], sprite_y[2], sprite_y[3], sprite_y[4], sprite_y[5], sprite_y[6], sprite_y[7]};
assign sprite_col_o = {sprite_col[0], sprite_col[1], sprite_col[2], sprite_col[3], sprite_col[4], sprite_col[5], sprite_col[6],sprite_col[7]};
reg res;
// Register Read/Write
reg [5:0] addr_latched;
reg addr_latch_done;
`ifdef WITH_EXTENSIONS
// Default to min version. If we never read any eeprom values,
// this is the value that will be returned.
reg[7:0] cfg_version = 8'hff;
reg[7:0] magic_1;
reg[7:0] magic_2;
reg[7:0] magic_3;
reg[7:0] magic_4;
reg [1:0] extra_regs_activation_ctr;
reg extra_regs_activated;
reg [1:0] spi_reg_activation_ctr;
reg spi_reg_activated;
`ifdef WITH_RAM
// Flags to govern read accesses causing auto inc/dec
reg video_ram_r; // also used to trigger auto inc after read
reg video_ram_r2; // also used to trigger auto inc after read
reg video_ram_aw; // auto increment after write is necessary
`endif
`ifdef CONFIGURABLE_RGB
reg color_regs_r; // also used to trigger auto inc after read
reg color_regs_r2; // also used to trigger auto inc after read
reg color_regs_aw; // auto increment after write is necessary
reg [1:0] color_regs_r_nibble;
reg [1:0] color_regs_wr_nibble;
`endif
`ifdef CONFIGURABLE_LUMAS
reg luma_regs_r; // also used to trigger auto inc after read
reg luma_regs_r2; // also used to trigger auto inc after read
reg luma_regs_aw; // auto increment after write is necessary
reg [1:0] luma_regs_r_nibble;
reg [1:0] luma_regs_wr_nibble;
`endif
`ifdef WITH_MATH
reg [31:0] result32;
reg [15:0] u_op_1;
reg [15:0] u_op_2;
reg signed [15:0] s_op_1;
reg signed [15:0] s_op_2;
wire u_div_done;
wire s_div_done;
wire [15:0] u_quotient;
wire [15:0] u_remain;
wire [15:0] s_quotient;
wire [15:0] s_remain;
reg [7:0] operator;
reg divzero;
`endif
reg [1:0] flag_port_1_func;
reg [1:0] flag_port_2_func;
reg port_selector; // which port are we applying func to
reg flag_regs_overlay;
reg flag_persist;
reg [7:0] port_hi_1;
reg [7:0] port_lo_1;
reg [7:0] port_idx_1;
reg [7:0] port_hi_2;
reg [7:0] port_lo_2;
reg [7:0] port_idx_2;
`ifdef WITH_RAM
// Port A used for CPU access
reg [ram_width-1:0] video_ram_addr_a;
reg video_ram_wr_a;
reg [7:0] video_ram_data_in_a;
wire [7:0] video_ram_data_out_a;
reg [15:0] video_ram_copy_src; // for both vmem<->vmem or dram<->vmem
reg [15:0] video_ram_copy_dst; // for both vmem<->vmem or dram<->vmem
reg [15:0] video_ram_copy_num; // for vmem<->vmem
reg [15:0] video_dma_copy_num; // for dram<->vmem
// For vmem<->vmem, direction of copy
// For dram<->vmem, 0=dram->vmem, 1=vmem->dram
reg video_ram_copy_dir;
// 0= write off, set read addr
// 1= read data, set write addr, write on
reg [1:0] video_ram_copy_state;
reg video_ram_copy_done = 1'b1;
reg [15:0] video_ram_fill_dst;
reg [15:0] video_ram_fill_num;
reg [7:0] video_ram_fill_val;
reg video_ram_fill_done = 1'b1;
`ifdef WITH_BLITTER
reg [9:0] blit_width;
reg [9:0] blit_height;
reg [15:0] blit_src_ptr;
reg [1:0] blit_src_x;
reg [7:0] blit_src_stride;
reg [15:0] blit_dst_ptr;
reg [1:0] blit_dst_x;
reg [7:0] blit_dst_stride;
reg [7:0] blit_flags;
reg blit_done = 1'b1;
reg [15:0] blit_src_cur;
reg [15:0] blit_dst_cur;
reg [7:0] blit_d; // dest mem byte
reg [7:0] blit_s; // src mem byte
reg [7:0] blit_o; // output byte
reg [8:0] blit_dst_pos; // dest byte offset from base ptr
reg [8:0] blit_src_pos; // src byte offset from base ptr
reg [9:0] blit_line; // keep track of raster line of bitmap
reg [1:0] blit_dst_align; // num pixels out of alignment
reg [1:0] blit_src_align; // num pixels out of alignment
reg [2:0] blit_src_avail; // num pixels available from src
reg [2:0] blit_dst_avail; // num pixels available from dst
reg [2:0] blit_out_avail; // num pixels available from out
reg [9:0] blit_pixels_written; // num pixels written from output
reg [2:0] blit_state;
reg blit_init;
wire [2:0] PIXELS_PER_BYTE;
assign PIXELS_PER_BYTE = hires_mode == 3'b011 ? 3'd4 : 3'd2;
`endif // WITH_BLITTER
`endif // WITH_RAM
// Regarding pre_wr registers below: We need an additional cycle to
// read existing values before writing. Otherwise, the data_out_a
// register will have garbage. This goes for both color and luma
// registers where we pack components inside a wider register.
`ifdef CONFIGURABLE_RGB
// For CPU register read/write to color regs
reg [3:0] color_regs_addr_a; // 16 regs
reg color_regs_wr_a;
reg color_regs_pre_wr_a;
reg color_regs_pre_wr2_a;
reg [5:0] color_regs_wr_value;
reg [23:0] color_regs_data_in_a;
wire [23:0] color_regs_data_out_a;
wire [23:0] color_regs_data_out_b;
`endif
`ifdef CONFIGURABLE_LUMAS
// For CPU register read/write to luma regs
reg [3:0] luma_regs_addr_a;
reg luma_regs_wr_a;
reg luma_regs_pre_wr_a;
reg luma_regs_pre_wr2_a;
reg [7:0] luma_regs_wr_value;
reg [17:0] luma_regs_data_in_a;
wire [17:0] luma_regs_data_out_a;
wire [17:0] luma_regs_data_out_b;
`endif
`ifndef HIRES_MODES
// Implies WITH_RAM and WITH_EXTENSIONS
// When extensions are enabled but we have no hires modes,
// then nothing needs to read from port b of video ram.
// So we have to define the wire/reg here.
wire [ram_width-1:0] video_ram_addr_b;
wire [7:0] video_ram_data_out_b;
assign video_ram_addr_b = {8'b0, `VIDEO_RAM_LO_PAD};
`endif
`ifdef WITH_RAM
// Auto increment/decrement of extra reg addr should happen on reads/writes
// to the extra reg data port. Some CPU instructions result in a single
// read or write. However, some CPU instructions address the
// memory location over 2 cycles, once for a read and then again for a write.
// We defer read inc/dec until the following cycle in case it is immediately
// followed by a write. This ensures increment happens after the CPU
// instruction is complete.
VIDEO_RAM video_ram(clk_dot4x,
video_ram_wr_a, // CPU can read/write
video_ram_addr_a,
video_ram_data_in_a,
video_ram_data_out_a,
1'b0, // Video can only read
video_ram_addr_b,
8'b0, // Video can only read
video_ram_data_out_b
);
`endif // WITH_RAM
`ifdef CONFIGURABLE_RGB
COLOR_REGS color_regs(clk_dot4x,
color_regs_wr_a, // write to color ram
color_regs_addr_a, // addr for color ram read/write
color_regs_data_in_a,
color_regs_data_out_a,
1'b0, // we never write to port b
clk_dvi,
`ifdef NEED_RGB
pixel_color4, // read addr for color lookups
`else
4'b0,
`endif
24'b0, // we never write to port b
color_regs_data_out_b // read value for color lookups
);
`endif
`ifdef CONFIGURABLE_LUMAS
LUMA_REGS luma_regs(clk_dot4x,
luma_regs_wr_a, // write to luma ram
luma_regs_addr_a, // addr for luma ram read/write
luma_regs_data_in_a,
luma_regs_data_out_a,
1'b0, // we never write to port b
pixel_color3, // read addr for luma lookups
18'b0, // we never write to port b
luma_regs_data_out_b // read value for luma lookups
);
`endif
`endif // WITH_EXTENSIONS
`ifdef HAVE_EEPROM
`include "registers_eeprom.vh"
`else
`include "registers_no_eeprom.vh"
`endif
`ifdef WITH_EXTENSIONS
`ifdef HAVE_FLASH
`include "registers_flash.vh"
`endif
`ifdef WITH_MATH
divide u_divider(.clk(clk_dot4x),
.sign(1'b0),
.done(u_div_done),
.dividend(u_op_1),
.divider(u_op_2),
.quotient(u_quotient),
.remainder(u_remain));
divide s_divider(.clk(clk_dot4x),
.sign(1'b1),
.done(s_div_done),
.dividend(s_op_1),
.divider(s_op_2),
.quotient(s_quotient),
.remainder(s_remain));
always @(posedge clk_dot4x)
begin
case (operator)
`U_MULT: begin
result32 = {16'b0, u_op_1} * {16'b0, u_op_2};
divzero = 0;
end
`U_DIV: begin
if (u_op_2 == 0)
divzero = 1;
else if (u_div_done) begin
result32[15:0] = u_quotient;
result32[31:16] = u_remain;
divzero = 0;
end
end
`S_MULT: begin
result32 = {s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15],s_op_1[15], s_op_1[15:0]} *
{s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15],s_op_2[15], s_op_2[15:0]};
divzero = 0;
end
`S_DIV: begin
if (s_op_2 == 0)
divzero = 1;
else if (s_div_done) begin
result32[15:0] = s_quotient;
result32[31:16] = s_remain;
divzero = 0;
end
end
default: ;
endcase
end
`endif // WITH_MATH
`endif // WITH_EXTENSIONS
// Master process block for registers
always @(posedge clk_dot4x)
begin
handle_persist(rst);
if (rst) begin
`ifdef TEST_PATTERN
ec <= `LIGHT_BLUE;
b0c <= `BLUE;
den <= `TRUE;
`endif
`ifdef HAVE_FLASH
flash_busy <= 1'b0;
`endif
//ec <= `BLACK;
//b0c <= `BLACK;
//den <= `FALSE;
//b1c <= BLACK;
//b2c <= BLACK;
//b3c <= BLACK;
//xscroll <= 3'd0;
//yscroll <= 3'd3;
//csel <= `FALSE;
//rsel <= `FALSE;
//bmm <= `FALSE;
//ecm <= `FALSE;
//res <= `FALSE;
//mcm <= `FALSE;
//irst_clr <= `FALSE;
//imbc_clr <= `FALSE;
//immc_clr <= `FALSE;
//ilp_clr <= `FALSE;
//raster_irq_compare <= 9'b0;
//sprite_en <= 8'b0;
//sprite_xe <= 8'b0;
//sprite_ye <= 8'b0;
//sprite_pri <= 8'b0;
//sprite_mmc <= 8'b0;
//sprite_mc0 <= BLACK;
//sprite_mc1 <= BLACK;
//for (n = 0; n < `NUM_SPRITES; n = n + 1) begin
// sprite_x[n] <= 9'b0;
// sprite_y[n] <= 8'b0;
// sprite_col[n] <= BLACK;
// end
//m2m_clr <= `FALSE;
//m2d_clr <= `FALSE;
//erst <= `FALSE;
//embc <= `FALSE;
//emmc <= `FALSE;
//elp <= `FALSE;
//dbo[7:0] <= 8'd0;
//handle_sprite_crunch <= `FALSE;
`ifdef NEED_RGB
last_raster_lines <= 1'b0;
last_is_native_y <= 1'b0;
last_is_native_x <= 1'b0;
last_enable_csync <= 1'b0;
last_hpolarity <= 1'b0;
last_vpolarity <= 1'b0;
`endif
`ifdef WITH_EXTENSIONS
`ifdef GEN_LUMA_CHROMA
`ifdef CONFIGURABLE_LUMAS
blanking_level <= 6'd12;
burst_amplitude <= 4'd12;
`endif
`endif
`ifdef CONFIGURABLE_TIMING
timing_change <= 1'b0;
timing_h_blank_ntsc <= 0;
`ifdef ANALOG_RGB_TIMING
timing_h_fporch_ntsc <= 10;
timing_h_sync_ntsc <= 70;
timing_h_bporch_ntsc <= 20;
`else
timing_h_fporch_ntsc <= 5;
timing_h_sync_ntsc <= 35;
timing_h_bporch_ntsc <= 40;
`endif
timing_v_blank_ntsc <= 11;
timing_v_fporch_ntsc <= 8;
timing_v_sync_ntsc <= 4;
timing_v_bporch_ntsc <= 3;
timing_h_blank_pal <= 0;
timing_h_fporch_pal <= 10;
timing_h_sync_pal <= 60;
timing_h_bporch_pal <= 20;
timing_v_blank_pal <= 28; // represents 284 (284-256)
timing_v_fporch_pal <= 5;
timing_v_sync_pal <= 2;
timing_v_bporch_pal <= 40; // NOTE: crosses 0, we sub 311 and invert sta/end
`endif
extra_regs_activation_ctr <= 2'b0;
flag_port_1_func <= 2'b0;
flag_port_2_func <= 2'b0;
flag_regs_overlay <= 1'b0;
flag_persist <= 1'b0;
`ifdef SIMULATOR_BOARD
extra_regs_activated <= 1'b1;
`ifdef HIRES_MODES
`ifdef HIRES_TEXT
// Test mode 0 : Text
hires_enabled <= 1'b1;
hires_allow_bad <= 1'b0;
hires_mode <= 3'b000;
// char pixels @0000(4K)
hires_char_pixel_base <= 3'b0;
// color table @1000(2K)
hires_color_base <= 4'b10;
// matrix @1800(2K)
hires_matrix_base <= 4'b11;
// Cursor top left
hires_cursor_hi <= 8'h18;
hires_cursor_lo <= 8'b00;
`endif
`ifdef HIRES_BITMAP1
hires_enabled <= 1'b1;
hires_allow_bad <= 1'b0;
hires_mode <= 3'b001;
hires_char_pixel_base <= 3'b0; // ignored
// pixels @0000(16k)
hires_matrix_base <= 4'b0000;
// color table @8000(2K)
hires_color_base <= 4'b1000;
`endif
`ifdef HIRES_BITMAP2
hires_enabled <= 1'b1;
hires_allow_bad <= 1'b0;
hires_mode <= 3'b010;
hires_char_pixel_base <= 3'b0; // ignored
hires_matrix_base <= 4'b0000; // 32k bank
hires_color_base <= 4'b0000; // ignored
`endif
`ifdef HIRES_BITMAP3
hires_enabled <= 1'b1;
hires_allow_bad <= 1'b0;
hires_mode <= 3'b011;
hires_char_pixel_base <= 3'b0; // ignored
hires_matrix_base <= 4'b0000; // 32k bank
hires_color_base <= 4'b0000; // 4 color bank
`endif
`ifdef HIRES_BITMAP4
hires_enabled <= 1'b1;
hires_allow_bad <= 1'b0;
hires_mode <= 3'b100;
hires_char_pixel_base <= 3'b0; // ignored
// pixels @0000(16k)
hires_matrix_base <= 4'b0000;
hires_color_base <= 4'b0000; // ignored
`endif
`endif // HIRES_MODES
/*
`ifdef HAVE_FLASH
//FOR TESTING FLASH WRITE IN SIM
if (spi_lock) begin
flash_begin <= `FLASH_WRITE;
// Grab the write address from 0x35,0x36,0x3a
flash_vmem_addr <= 0;
flash_addr <= 24'h7d000;
flash_command_ctr <= `FLASH_CMD_WREN;
flash_bit_ctr <= 6'd0;
flash_busy <= 1'b1;
flash_verify_error <= 1'b0;
flash_page_ctr = 6'b0;
end
`endif
*/
/*
`ifdef HAVE_FLASH
//FOR TESTING FLASH READ IN SIM
if (spi_lock) begin
flash_begin <= `FLASH_READ;
// Grab the write address from 0x35,0x36,0x3a
flash_vmem_addr <= 0;
flash_addr <= 24'h7d000;
flash_command_ctr <= `FLASH_CMD_READ;
flash_bit_ctr <= 6'd0;
flash_busy <= 1'b1;
flash_verify_error <= 1'b0;
flash_page_ctr = 6'b0;
end
`endif
*/
`else // SIMULATION_BOARD
extra_regs_activated <= 1'b0;
`ifdef HIRES_MODES
hires_mode <= 3'b000;
hires_enabled <= 1'b0;
hires_allow_bad <= 1'b0;
hires_char_pixel_base <= 3'b0;
hires_matrix_base <= 4'b0000; // ignored
hires_color_base <= 4'b0000; // ignored
hires_cursor_hi <= 8'b0;
hires_cursor_lo <= 8'b0;
`endif // HIRES_MODES
`endif // SIMULATOR_BOARD
`endif // WITH_EXTENSIONS
end else
begin
`ifdef WITH_EXTENSIONS
`ifdef HAVE_FLASH
handle_flash();
`endif
`ifdef HIRES_MODES
`ifdef HIRES_RESET
// This block will detect a reset (if the reset line is
// hooked up to the 6510 CPU reset pin) and reset hires
// registers and restore all extra regs as well if eeprom
// is included.
`ifdef HAVE_EEPROM
if (!cpu_reset_i && extra_regs_activated && !eeprom_busy) begin
`else
if (!cpu_reset_i && extra_regs_activated) begin
`endif
hires_mode <= 3'b000;
hires_enabled <= 1'b0;
hires_allow_bad <= 1'b0;
hires_char_pixel_base <= 3'b0;
hires_matrix_base <= 4'b0000;
hires_color_base <= 4'b0000;
hires_cursor_hi <= 8'b0;
hires_cursor_lo <= 8'b0;
spi_reg_activated <= 1'b0;
`ifdef HAVE_EEPROM
state_ctr_reset_for_read <= 1;
// TODO: Else, we should reset color regs from hardcoded values.
`endif
end
`endif // HIRES_RESET
`endif // HIRES_MODES
`ifdef HAVE_EEPROM
if (!cfg_reset && !eeprom_busy) begin
eeprom_busy <= 1'b1;
eeprom_w_addr <= { 2'b0, `EXT_REG_MAGIC_0 };
eeprom_w_value <= 8'h00;
state_ctr_reset_for_write <= 1'b1;
ec <= `WHITE;
b0c <= `WHITE;
end
`endif
`endif // WITH_EXTENSIONS
if (phi_phase_start[`DATA_DAV_PLUS_1]) begin
if (!clk_phi) begin
// always clear these immediately after they may
// have been used. This should be DAV + 1
irst_clr <= `FALSE;
imbc_clr <= `FALSE;
immc_clr <= `FALSE;
ilp_clr <= `FALSE;
m2m_clr <= `FALSE;
m2d_clr <= `FALSE;
end
addr_latch_done <= `FALSE;
last_bus <= 8'hff;
// clear sprite crunch immediately after it may
// have been used
handle_sprite_crunch <= `FALSE;
end
if (!ras && clk_phi && !addr_latch_done) begin
addr_latched <= adi[5:0];
addr_latch_done <= `TRUE;
end
if (aec && !ce && addr_latch_done) begin
// READ from register
// For registers that clear collisions, we do it on [dav].
// Otherwise, we'd do it way too early if we did it at the
// same time we assert dbo in the block below. VICE sync
// complains it is too early.
if (rw && phi_phase_start[`DATA_DAV]) begin
case (addr_latched[5:0])
/* 0x1e */ `REG_SPRITE_2_SPRITE_COLLISION: begin
// reading this register clears the value
m2m_clr <= 1;
end
/* 0x1f */ `REG_SPRITE_2_DATA_COLLISION: begin
// reading this register clears the value
m2d_clr <= 1;
end
default: ;
endcase
end
if (rw) begin
last_bus <= dbo;
case (addr_latched[5:0])
/* 0x00 */ `REG_SPRITE_X_0:
dbo[7:0] <= sprite_x[0][7:0];
/* 0x02 */ `REG_SPRITE_X_1:
dbo[7:0] <= sprite_x[1][7:0];
/* 0x04 */ `REG_SPRITE_X_2:
dbo[7:0] <= sprite_x[2][7:0];
/* 0x06 */ `REG_SPRITE_X_3:
dbo[7:0] <= sprite_x[3][7:0];
/* 0x08 */ `REG_SPRITE_X_4:
dbo[7:0] <= sprite_x[4][7:0];
/* 0x0a */ `REG_SPRITE_X_5:
dbo[7:0] <= sprite_x[5][7:0];
/* 0x0c */ `REG_SPRITE_X_6:
dbo[7:0] <= sprite_x[6][7:0];
/* 0x0e */ `REG_SPRITE_X_7:
dbo[7:0] <= sprite_x[7][7:0];
/* 0x01 */ `REG_SPRITE_Y_0:
dbo[7:0] <= sprite_y[0];
/* 0x03 */ `REG_SPRITE_Y_1:
dbo[7:0] <= sprite_y[1];
/* 0x05 */ `REG_SPRITE_Y_2:
dbo[7:0] <= sprite_y[2];
/* 0x07 */ `REG_SPRITE_Y_3:
dbo[7:0] <= sprite_y[3];
/* 0x09 */ `REG_SPRITE_Y_4:
dbo[7:0] <= sprite_y[4];
/* 0x0b */ `REG_SPRITE_Y_5:
dbo[7:0] <= sprite_y[5];
/* 0x0d */ `REG_SPRITE_Y_6:
dbo[7:0] <= sprite_y[6];
/* 0x0f */ `REG_SPRITE_Y_7:
dbo[7:0] <= sprite_y[7];
/* 0x10 */ `REG_SPRITE_X_BIT_8:
dbo[7:0] <= {sprite_x[7][8],
sprite_x[6][8],
sprite_x[5][8],
sprite_x[4][8],
sprite_x[3][8],
sprite_x[2][8],
sprite_x[1][8],
sprite_x[0][8]};
/* 0x11 */ `REG_SCREEN_CONTROL_1: begin
dbo[2:0] <= yscroll;
dbo[3] <= rsel;
dbo[4] <= den;
dbo[5] <= bmm;
dbo[6] <= ecm;
dbo[7] <= raster_line[8];
end
/* 0x12 */ `REG_RASTER_LINE: dbo[7:0] <= raster_line[7:0];
`ifdef WIV_EXTENSIONS
/* 0x13 */ `REG_LIGHT_PEN_X: begin
if (wiv_cre) begin
dbo[0] <= wiv_cre;
dbo[1] <= wiv_xmp;
dbo[2] <= wiv_dvb;
dbo[3] <= wiv_dmb;
dbo[7:4] <= wiv_cr3_unused;
end else begin
dbo[7:0] <= lpx;
end
end
/* 0x14 */ `REG_LIGHT_PEN_Y: begin
if (wiv_cre)
dbo[7:0] <= wiv_cr4_unused;
else
dbo[7:0] <= lpx;
end
`else
/* 0x13 */ `REG_LIGHT_PEN_X: dbo[7:0] <= lpx;
/* 0x14 */ `REG_LIGHT_PEN_Y: dbo[7:0] <= lpy;
`endif //WIV_EXTENSIONS
/* 0x15 */ `REG_SPRITE_ENABLE: dbo[7:0] <= sprite_en;
/* 0x16 */ `REG_SCREEN_CONTROL_2:
dbo[7:0] <= {2'b11, res, mcm, csel, xscroll};
/* 0x17 */ `REG_SPRITE_EXPAND_Y:
dbo[7:0] <= sprite_ye;
/* 0x18 */ `REG_MEMORY_SETUP: begin
`ifdef WIV_EXTENSIONS
dbo[0] <= cb[0] | ~wiv_xmp;
dbo[3:1] <= cb[3:1];
`else
dbo[0] <= 1'b1;
dbo[3:1] <= cb[2:0];
`endif
dbo[7:4] <= vm[3:0];
end
// NOTE: Our irq is inverted already
/* 0x19 */ `REG_INTERRUPT_STATUS:
dbo[7:0] <= {irq, 3'b111, ilp, immc, imbc, irst};
/* 0x1a */ `REG_INTERRUPT_CONTROL:
dbo[7:0] <= {4'b1111, elp, emmc, embc, erst};
/* 0x1b */ `REG_SPRITE_PRIORITY:
dbo[7:0] <= sprite_pri;
/* 0x1c */ `REG_SPRITE_MULTICOLOR_MODE:
dbo[7:0] <= sprite_mmc;
/* 0x1d */ `REG_SPRITE_EXPAND_X:
dbo[7:0] <= sprite_xe;
/* 0x1e */ `REG_SPRITE_2_SPRITE_COLLISION:
dbo[7:0] <= sprite_m2m;
/* 0x1f */ `REG_SPRITE_2_DATA_COLLISION:
dbo[7:0] <= sprite_m2d;
/* 0x20 */ `REG_BORDER_COLOR:
dbo[7:0] <= {4'b1111, ec};
/* 0x21 */ `REG_BACKGROUND_COLOR_0:
dbo[7:0] <= {4'b1111, b0c};
/* 0x22 */ `REG_BACKGROUND_COLOR_1:
dbo[7:0] <= {4'b1111, b1c};
/* 0x23 */ `REG_BACKGROUND_COLOR_2:
dbo[7:0] <= {4'b1111, b2c};
/* 0x24 */ `REG_BACKGROUND_COLOR_3:
dbo[7:0] <= {4'b1111, b3c};
/* 0x25 */ `REG_SPRITE_MULTI_COLOR_0:
dbo[7:0] <= {4'b1111, sprite_mc0};
/* 0x26 */ `REG_SPRITE_MULTI_COLOR_1:
dbo[7:0] <= {4'b1111, sprite_mc1};
/* 0x27 */ `REG_SPRITE_COLOR_0:
dbo[7:0] <= {4'b1111, sprite_col[0]};
/* 0x28 */ `REG_SPRITE_COLOR_1:
dbo[7:0] <= {4'b1111, sprite_col[1]};
/* 0x29 */ `REG_SPRITE_COLOR_2:
dbo[7:0] <= {4'b1111, sprite_col[2]};
/* 0x2a */ `REG_SPRITE_COLOR_3:
dbo[7:0] <= {4'b1111, sprite_col[3]};
/* 0x2b */ `REG_SPRITE_COLOR_4:
dbo[7:0] <= {4'b1111, sprite_col[4]};
/* 0x2c */ `REG_SPRITE_COLOR_5:
dbo[7:0] <= {4'b1111, sprite_col[5]};
/* 0x2d */ `REG_SPRITE_COLOR_6:
dbo[7:0] <= {4'b1111, sprite_col[6]};
/* 0x2e */ `REG_SPRITE_COLOR_7:
dbo[7:0] <= {4'b1111, sprite_col[7]};
default:
// Make sure we qualify this with a check on extra regs
// activated or not if we have extensions. We don't want to
// set dbo here and then possibly again down below.
`ifdef WITH_EXTENSIONS
if (~extra_regs_activated)
`endif // WITH_EXTENSIONS
dbo[7:0] <= 8'hFF;
endcase
`ifdef WITH_EXTENSIONS
if (extra_regs_activated) begin
case (addr_latched[5:0])
`ifdef WITH_MATH
/* 0x2f */ 6'h2f: begin
dbo[7:0] <= result32[31:24];
end
/* 0x30 */ 6'h30: begin
dbo[7:0] <= result32[23:16];
end
/* 0x31 */ 6'h31: begin
dbo[7:0] <= result32[15:8];
end
/* 0x32 */ 6'h32: begin
dbo[7:0] <= result32[7:0];
end
/* 0x33 */ 6'h33: begin
dbo[7:0] <= {7'b0, divzero};
end
`endif
`SPI_REG:
dbo[7:0] <= {
2'b0,
persistence_lock,
extensions_lock,
spi_lock,
`ifdef HAVE_FLASH
flash_verify_error,
flash_busy,
`else
1'b0,
1'b0,
`endif
`ifdef WITH_SPI
spi_q
`else
1'b0
`endif
};
`VIDEO_MEM_1_IDX:
dbo[7:0] <= port_idx_1;
`VIDEO_MEM_2_IDX:
dbo[7:0] <= port_idx_2;
`VIDEO_MODE1: begin
`ifdef HIRES_MODES
dbo[7:0] <= { hires_mode,
hires_enabled,
hires_allow_bad,
hires_char_pixel_base };
`else
dbo[7:0] <= { 1'b0,
2'b0,