/
dwc_otg_hcd_intr.c
2246 lines (2005 loc) · 65.3 KB
/
dwc_otg_hcd_intr.c
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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
* $Revision: #89 $
* $Date: 2011/10/20 $
* $Change: 1869487 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef DWC_DEVICE_ONLY
#include "dwc_otg_hcd.h"
#include "dwc_otg_regs.h"
#include "dwc_otg_mphi_fix.h"
#include <linux/jiffies.h>
#include <mach/hardware.h>
extern bool microframe_schedule;
/** @file
* This file contains the implementation of the HCD Interrupt handlers.
*/
/*
* Some globals to communicate between the FIQ and INTERRUPT
*/
void * dummy_send;
mphi_regs_t c_mphi_regs;
int fiq_done, int_done;
int g_next_sched_frame, g_np_count, g_np_sent, g_work_expected;
static int mphi_int_count = 0 ;
extern bool fiq_fix_enable, nak_holdoff_enable;
hcchar_data_t nak_hcchar;
hctsiz_data_t nak_hctsiz;
hcsplt_data_t nak_hcsplt;
int nak_count;
void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void)
{
gintsts_data_t gintsts;
hfnum_data_t hfnum;
/* entry takes care to store registers we will be treading on here */
asm __volatile__ (
"mov ip, sp ;"
/* stash FIQ and normal regs */
"stmdb sp!, {r0-r12, lr};"
/* !! THIS SETS THE FRAME, adjust to > sizeof locals */
"sub fp, ip, #256 ;"
);
fiq_done++;
gintsts.d32 = FIQ_READ_IO_ADDRESS(USB_BASE + 0x14) & FIQ_READ_IO_ADDRESS(USB_BASE + 0x18);
hfnum.d32 = FIQ_READ_IO_ADDRESS(USB_BASE + 0x408);
if(gintsts.d32)
{
if(gintsts.b.sofintr && g_np_count == g_np_sent && dwc_frame_num_gt(g_next_sched_frame, hfnum.b.frnum))
{
/*
* If np_count != np_sent that means we need to queue non-periodic (bulk) packets this packet
* g_next_sched_frame is the next frame we have periodic packets for
*
* if neither of these are required for this frame then just clear the interrupt
*/
gintsts.d32 = 0;
gintsts.b.sofintr = 1;
FIQ_WRITE_IO_ADDRESS((USB_BASE + 0x14), gintsts.d32);
g_work_expected = 0;
}
else
{
g_work_expected = 1;
/* To enable the MPHI interrupt (INT 32)
*/
FIQ_WRITE( c_mphi_regs.outdda, (int) dummy_send);
FIQ_WRITE( c_mphi_regs.outddb, (1 << 29));
mphi_int_count++;
/* Clear the USB global interrupt so we don't just sit in the FIQ */
FIQ_MODIFY_IO_ADDRESS((USB_BASE + 0x8),1,0);
}
}
mb();
/* exit back to normal mode restoring everything */
asm __volatile__ (
/* return FIQ regs back to pristine state
* and get normal regs back
*/
"ldmia sp!, {r0-r12, lr};"
/* return */
"subs pc, lr, #4;"
);
}
/** This function handles interrupts for the HCD. */
int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
{
int retval = 0;
static int last_time;
dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
gintsts_data_t gintsts;
hfnum_data_t hfnum;
#ifdef DEBUG
dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
#endif
/* Exit from ISR if core is hibernated */
if (core_if->hibernation_suspend == 1) {
goto exit_handler_routine;
}
DWC_SPINLOCK(dwc_otg_hcd->lock);
/* Check if HOST Mode */
if (dwc_otg_is_host_mode(core_if)) {
gintsts.d32 = dwc_otg_read_core_intr(core_if);
if (!gintsts.d32) {
goto exit_handler_routine;
}
#ifdef DEBUG
/* Don't print debug message in the interrupt handler on SOF */
#ifndef DEBUG_SOF
if (gintsts.d32 != DWC_SOF_INTR_MASK)
#endif
DWC_DEBUGPL(DBG_HCDI, "\n");
#endif
#ifdef DEBUG
#ifndef DEBUG_SOF
if (gintsts.d32 != DWC_SOF_INTR_MASK)
#endif
DWC_DEBUGPL(DBG_HCDI,
"DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n",
gintsts.d32, core_if);
#endif
hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum);
if (gintsts.b.sofintr && g_np_count == g_np_sent && dwc_frame_num_gt(g_next_sched_frame, hfnum.b.frnum))
{
/* Note, we should never get here if the FIQ is doing it's job properly*/
retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd, g_work_expected);
}
else if (gintsts.b.sofintr) {
retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd, g_work_expected);
}
if (gintsts.b.rxstsqlvl) {
retval |=
dwc_otg_hcd_handle_rx_status_q_level_intr
(dwc_otg_hcd);
}
if (gintsts.b.nptxfempty) {
retval |=
dwc_otg_hcd_handle_np_tx_fifo_empty_intr
(dwc_otg_hcd);
}
if (gintsts.b.i2cintr) {
/** @todo Implement i2cintr handler. */
}
if (gintsts.b.portintr) {
retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
}
if (gintsts.b.hcintr) {
retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
}
if (gintsts.b.ptxfempty) {
retval |=
dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
(dwc_otg_hcd);
}
#ifdef DEBUG
#ifndef DEBUG_SOF
if (gintsts.d32 != DWC_SOF_INTR_MASK)
#endif
{
DWC_DEBUGPL(DBG_HCDI,
"DWC OTG HCD Finished Servicing Interrupts\n");
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
DWC_READ_REG32(&global_regs->gintsts));
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
DWC_READ_REG32(&global_regs->gintmsk));
}
#endif
#ifdef DEBUG
#ifndef DEBUG_SOF
if (gintsts.d32 != DWC_SOF_INTR_MASK)
#endif
DWC_DEBUGPL(DBG_HCDI, "\n");
#endif
}
exit_handler_routine:
if (fiq_fix_enable)
{
/* Clear the MPHI interrupt */
DWC_WRITE_REG32(c_mphi_regs.intstat, (1<<16));
if (mphi_int_count >= 60)
{
DWC_WRITE_REG32(c_mphi_regs.ctrl, ((1<<31) + (1<<16)));
DWC_WRITE_REG32(c_mphi_regs.ctrl, (1<<31));
mphi_int_count = 0;
}
int_done++;
if((jiffies / HZ) > last_time)
{
/* Once a second output the fiq and irq numbers, useful for debug */
last_time = jiffies / HZ;
DWC_DEBUGPL(DBG_USER, "int_done = %d fiq_done = %d\n", int_done, fiq_done);
}
/* Re-Enable FIQ interrupt from USB peripheral */
DWC_MODIFY_REG32((uint32_t *)IO_ADDRESS(USB_BASE + 0x8), 0 , 1);
}
DWC_SPINUNLOCK(dwc_otg_hcd->lock);
return retval;
}
#ifdef DWC_TRACK_MISSED_SOFS
#warning Compiling code to track missed SOFs
#define FRAME_NUM_ARRAY_SIZE 1000
/**
* This function is for debug only.
*/
static inline void track_missed_sofs(uint16_t curr_frame_number)
{
static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
static int frame_num_idx = 0;
static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
static int dumped_frame_num_array = 0;
if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
curr_frame_number) {
frame_num_array[frame_num_idx] = curr_frame_number;
last_frame_num_array[frame_num_idx++] = last_frame_num;
}
} else if (!dumped_frame_num_array) {
int i;
DWC_PRINTF("Frame Last Frame\n");
DWC_PRINTF("----- ----------\n");
for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
DWC_PRINTF("0x%04x 0x%04x\n",
frame_num_array[i], last_frame_num_array[i]);
}
dumped_frame_num_array = 1;
}
last_frame_num = curr_frame_number;
}
#endif
/**
* Handles the start-of-frame interrupt in host mode. Non-periodic
* transactions may be queued to the DWC_otg controller for the current
* (micro)frame. Periodic transactions may be queued to the controller for the
* next (micro)frame.
*/
int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd, int32_t work_expected)
{
hfnum_data_t hfnum;
dwc_list_link_t *qh_entry;
dwc_otg_qh_t *qh;
dwc_otg_transaction_type_e tr_type;
gintsts_data_t gintsts = {.d32 = 0 };
int did_something = 0;
int32_t next_sched_frame = -1;
hfnum.d32 =
DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
#ifdef DEBUG_SOF
DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
#endif
hcd->frame_number = hfnum.b.frnum;
#ifdef DEBUG
hcd->frrem_accum += hfnum.b.frrem;
hcd->frrem_samples++;
#endif
#ifdef DWC_TRACK_MISSED_SOFS
track_missed_sofs(hcd->frame_number);
#endif
/* Determine whether any periodic QHs should be executed. */
qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
while (qh_entry != &hcd->periodic_sched_inactive) {
qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
qh_entry = qh_entry->next;
if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
/*
* Move QH to the ready list to be executed next
* (micro)frame.
*/
DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
&qh->qh_list_entry);
did_something = 1;
}
else
{
if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame))
{
next_sched_frame = qh->sched_frame;
}
}
}
g_next_sched_frame = next_sched_frame;
tr_type = dwc_otg_hcd_select_transactions(hcd);
if (tr_type != DWC_OTG_TRANSACTION_NONE) {
dwc_otg_hcd_queue_transactions(hcd, tr_type);
did_something = 1;
}
if(work_expected && !did_something)
DWC_DEBUGPL(DBG_USER, "Nothing to do !! frame = %x, g_next_sched_frame = %x\n", (int) hfnum.b.frnum, g_next_sched_frame);
if(!work_expected && did_something)
DWC_DEBUGPL(DBG_USER, "Unexpected work done !! frame = %x, g_next_sched_frame = %x\n", (int) hfnum.b.frnum, g_next_sched_frame);
/* Clear interrupt */
gintsts.b.sofintr = 1;
DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
return 1;
}
/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
* least one packet in the Rx FIFO. The packets are moved from the FIFO to
* memory if the DWC_otg controller is operating in Slave mode. */
int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
{
host_grxsts_data_t grxsts;
dwc_hc_t *hc = NULL;
DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
grxsts.d32 =
DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
if (!hc) {
DWC_ERROR("Unable to get corresponding channel\n");
return 0;
}
/* Packet Status */
DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
hc->data_pid_start);
DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
switch (grxsts.b.pktsts) {
case DWC_GRXSTS_PKTSTS_IN:
/* Read the data into the host buffer. */
if (grxsts.b.bcnt > 0) {
dwc_otg_read_packet(dwc_otg_hcd->core_if,
hc->xfer_buff, grxsts.b.bcnt);
/* Update the HC fields for the next packet received. */
hc->xfer_count += grxsts.b.bcnt;
hc->xfer_buff += grxsts.b.bcnt;
}
case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
case DWC_GRXSTS_PKTSTS_CH_HALTED:
/* Handled in interrupt, just ignore data */
break;
default:
DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
grxsts.b.pktsts);
break;
}
return 1;
}
/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
* data packets may be written to the FIFO for OUT transfers. More requests
* may be written to the non-periodic request queue for IN transfers. This
* interrupt is enabled only in Slave mode. */
int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
{
DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
DWC_OTG_TRANSACTION_NON_PERIODIC);
return 1;
}
/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
* packets may be written to the FIFO for OUT transfers. More requests may be
* written to the periodic request queue for IN transfers. This interrupt is
* enabled only in Slave mode. */
int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
{
DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
DWC_OTG_TRANSACTION_PERIODIC);
return 1;
}
/** There are multiple conditions that can cause a port interrupt. This function
* determines which interrupt conditions have occurred and handles them
* appropriately. */
int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
{
int retval = 0;
hprt0_data_t hprt0;
hprt0_data_t hprt0_modify;
hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
/* Clear appropriate bits in HPRT0 to clear the interrupt bit in
* GINTSTS */
hprt0_modify.b.prtena = 0;
hprt0_modify.b.prtconndet = 0;
hprt0_modify.b.prtenchng = 0;
hprt0_modify.b.prtovrcurrchng = 0;
/* Port Connect Detected
* Set flag and clear if detected */
if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
// Dont modify port status if we are in hibernation state
hprt0_modify.b.prtconndet = 1;
hprt0_modify.b.prtenchng = 1;
DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
return retval;
}
if (hprt0.b.prtconndet) {
/** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
if (dwc_otg_hcd->core_if->adp_enable &&
dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
/* TODO - check if this is required, as
* host initialization was already performed
* after initial ADP probing
*/
/*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
dwc_otg_core_init(dwc_otg_hcd->core_if);
dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
cil_hcd_start(dwc_otg_hcd->core_if);*/
} else {
DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
"Port Connect Detected--\n", hprt0.d32);
dwc_otg_hcd->flags.b.port_connect_status_change = 1;
dwc_otg_hcd->flags.b.port_connect_status = 1;
hprt0_modify.b.prtconndet = 1;
/* B-Device has connected, Delete the connection timer. */
DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
}
/* The Hub driver asserts a reset when it sees port connect
* status change flag */
retval |= 1;
}
/* Port Enable Changed
* Clear if detected - Set internal flag if disabled */
if (hprt0.b.prtenchng) {
DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
"Port Enable Changed--\n", hprt0.d32);
hprt0_modify.b.prtenchng = 1;
if (hprt0.b.prtena == 1) {
hfir_data_t hfir;
int do_reset = 0;
dwc_otg_core_params_t *params =
dwc_otg_hcd->core_if->core_params;
dwc_otg_core_global_regs_t *global_regs =
dwc_otg_hcd->core_if->core_global_regs;
dwc_otg_host_if_t *host_if =
dwc_otg_hcd->core_if->host_if;
/* Every time when port enables calculate
* HFIR.FrInterval
*/
hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
/* Check if we need to adjust the PHY clock speed for
* low power and adjust it */
if (params->host_support_fs_ls_low_power) {
gusbcfg_data_t usbcfg;
usbcfg.d32 =
DWC_READ_REG32(&global_regs->gusbcfg);
if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
|| hprt0.b.prtspd ==
DWC_HPRT0_PRTSPD_FULL_SPEED) {
/*
* Low power
*/
hcfg_data_t hcfg;
if (usbcfg.b.phylpwrclksel == 0) {
/* Set PHY low power clock select for FS/LS devices */
usbcfg.b.phylpwrclksel = 1;
DWC_WRITE_REG32
(&global_regs->gusbcfg,
usbcfg.d32);
do_reset = 1;
}
hcfg.d32 =
DWC_READ_REG32
(&host_if->host_global_regs->hcfg);
if (hprt0.b.prtspd ==
DWC_HPRT0_PRTSPD_LOW_SPEED
&& params->host_ls_low_power_phy_clk
==
DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
{
/* 6 MHZ */
DWC_DEBUGPL(DBG_CIL,
"FS_PHY programming HCFG to 6 MHz (Low Power)\n");
if (hcfg.b.fslspclksel !=
DWC_HCFG_6_MHZ) {
hcfg.b.fslspclksel =
DWC_HCFG_6_MHZ;
DWC_WRITE_REG32
(&host_if->host_global_regs->hcfg,
hcfg.d32);
do_reset = 1;
}
} else {
/* 48 MHZ */
DWC_DEBUGPL(DBG_CIL,
"FS_PHY programming HCFG to 48 MHz ()\n");
if (hcfg.b.fslspclksel !=
DWC_HCFG_48_MHZ) {
hcfg.b.fslspclksel =
DWC_HCFG_48_MHZ;
DWC_WRITE_REG32
(&host_if->host_global_regs->hcfg,
hcfg.d32);
do_reset = 1;
}
}
} else {
/*
* Not low power
*/
if (usbcfg.b.phylpwrclksel == 1) {
usbcfg.b.phylpwrclksel = 0;
DWC_WRITE_REG32
(&global_regs->gusbcfg,
usbcfg.d32);
do_reset = 1;
}
}
if (do_reset) {
DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
}
}
if (!do_reset) {
/* Port has been enabled set the reset change flag */
dwc_otg_hcd->flags.b.port_reset_change = 1;
}
} else {
dwc_otg_hcd->flags.b.port_enable_change = 1;
}
retval |= 1;
}
/** Overcurrent Change Interrupt */
if (hprt0.b.prtovrcurrchng) {
DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
"Port Overcurrent Changed--\n", hprt0.d32);
dwc_otg_hcd->flags.b.port_over_current_change = 1;
hprt0_modify.b.prtovrcurrchng = 1;
retval |= 1;
}
/* Clear Port Interrupts */
DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
return retval;
}
/** This interrupt indicates that one or more host channels has a pending
* interrupt. There are multiple conditions that can cause each host channel
* interrupt. This function determines which conditions have occurred for each
* host channel interrupt and handles them appropriately. */
int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
{
int i;
int retval = 0;
haint_data_t haint;
/* Clear appropriate bits in HCINTn to clear the interrupt bit in
* GINTSTS */
haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
if (haint.b2.chint & (1 << i)) {
retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
}
}
return retval;
}
/**
* Gets the actual length of a transfer after the transfer halts. _halt_status
* holds the reason for the halt.
*
* For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
* *short_read is set to 1 upon return if less than the requested
* number of bytes were transferred. Otherwise, *short_read is set to 0 upon
* return. short_read may also be NULL on entry, in which case it remains
* unchanged.
*/
static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
dwc_otg_hc_regs_t * hc_regs,
dwc_otg_qtd_t * qtd,
dwc_otg_halt_status_e halt_status,
int *short_read)
{
hctsiz_data_t hctsiz;
uint32_t length;
if (short_read != NULL) {
*short_read = 0;
}
hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
if (hc->ep_is_in) {
length = hc->xfer_len - hctsiz.b.xfersize;
if (short_read != NULL) {
*short_read = (hctsiz.b.xfersize != 0);
}
} else if (hc->qh->do_split) {
length = qtd->ssplit_out_xfer_count;
} else {
length = hc->xfer_len;
}
} else {
/*
* Must use the hctsiz.pktcnt field to determine how much data
* has been transferred. This field reflects the number of
* packets that have been transferred via the USB. This is
* always an integral number of packets if the transfer was
* halted before its normal completion. (Can't use the
* hctsiz.xfersize field because that reflects the number of
* bytes transferred via the AHB, not the USB).
*/
length =
(hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
}
return length;
}
/**
* Updates the state of the URB after a Transfer Complete interrupt on the
* host channel. Updates the actual_length field of the URB based on the
* number of bytes transferred via the host channel. Sets the URB status
* if the data transfer is finished.
*
* @return 1 if the data transfer specified by the URB is completely finished,
* 0 otherwise.
*/
static int update_urb_state_xfer_comp(dwc_hc_t * hc,
dwc_otg_hc_regs_t * hc_regs,
dwc_otg_hcd_urb_t * urb,
dwc_otg_qtd_t * qtd)
{
int xfer_done = 0;
int short_read = 0;
int xfer_length;
xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
DWC_OTG_HC_XFER_COMPLETE,
&short_read);
/* non DWORD-aligned buffer case handling. */
if (hc->align_buff && xfer_length && hc->ep_is_in) {
dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
xfer_length);
}
urb->actual_length += xfer_length;
if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
(urb->flags & URB_SEND_ZERO_PACKET)
&& (urb->actual_length == urb->length)
&& !(urb->length % hc->max_packet)) {
xfer_done = 0;
} else if (short_read || urb->actual_length >= urb->length) {
xfer_done = 1;
urb->status = 0;
}
#ifdef DEBUG
{
hctsiz_data_t hctsiz;
hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
__func__, (hc->ep_is_in ? "IN" : "OUT"),
hc->hc_num);
DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n",
hctsiz.b.xfersize);
DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
urb->length);
DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n",
urb->actual_length);
DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
short_read, xfer_done);
}
#endif
return xfer_done;
}
/*
* Save the starting data toggle for the next transfer. The data toggle is
* saved in the QH for non-control transfers and it's saved in the QTD for
* control transfers.
*/
void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
{
hctsiz_data_t hctsiz;
hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
dwc_otg_qh_t *qh = hc->qh;
if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
qh->data_toggle = DWC_OTG_HC_PID_DATA0;
} else {
qh->data_toggle = DWC_OTG_HC_PID_DATA1;
}
} else {
if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
} else {
qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
}
}
}
/**
* Updates the state of an Isochronous URB when the transfer is stopped for
* any reason. The fields of the current entry in the frame descriptor array
* are set based on the transfer state and the input _halt_status. Completes
* the Isochronous URB if all the URB frames have been completed.
*
* @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
* transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
*/
static dwc_otg_halt_status_e
update_isoc_urb_state(dwc_otg_hcd_t * hcd,
dwc_hc_t * hc,
dwc_otg_hc_regs_t * hc_regs,
dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
{
dwc_otg_hcd_urb_t *urb = qtd->urb;
dwc_otg_halt_status_e ret_val = halt_status;
struct dwc_otg_hcd_iso_packet_desc *frame_desc;
frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
switch (halt_status) {
case DWC_OTG_HC_XFER_COMPLETE:
frame_desc->status = 0;
frame_desc->actual_length =
get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
/* non DWORD-aligned buffer case handling. */
if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
hc->qh->dw_align_buf, frame_desc->actual_length);
}
break;
case DWC_OTG_HC_XFER_FRAME_OVERRUN:
urb->error_count++;
if (hc->ep_is_in) {
frame_desc->status = -DWC_E_NO_STREAM_RES;
} else {
frame_desc->status = -DWC_E_COMMUNICATION;
}
frame_desc->actual_length = 0;
break;
case DWC_OTG_HC_XFER_BABBLE_ERR:
urb->error_count++;
frame_desc->status = -DWC_E_OVERFLOW;
/* Don't need to update actual_length in this case. */
break;
case DWC_OTG_HC_XFER_XACT_ERR:
urb->error_count++;
frame_desc->status = -DWC_E_PROTOCOL;
frame_desc->actual_length =
get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
/* non DWORD-aligned buffer case handling. */
if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
hc->qh->dw_align_buf, frame_desc->actual_length);
}
/* Skip whole frame */
if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
hc->ep_is_in && hcd->core_if->dma_enable) {
qtd->complete_split = 0;
qtd->isoc_split_offset = 0;
}
break;
default:
DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
break;
}
if (++qtd->isoc_frame_index == urb->packet_count) {
/*
* urb->status is not used for isoc transfers.
* The individual frame_desc statuses are used instead.
*/
hcd->fops->complete(hcd, urb->priv, urb, 0);
ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
} else {
ret_val = DWC_OTG_HC_XFER_COMPLETE;
}
return ret_val;
}
/**
* Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
* QHs, removes the QH from the active non-periodic schedule. If any QTDs are
* still linked to the QH, the QH is added to the end of the inactive
* non-periodic schedule. For periodic QHs, removes the QH from the periodic
* schedule if no more QTDs are linked to the QH.
*/
static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
{
int continue_split = 0;
dwc_otg_qtd_t *qtd;
DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
if (qtd->complete_split) {
continue_split = 1;
} else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
continue_split = 1;
}
if (free_qtd) {
dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
continue_split = 0;
}
qh->channel = NULL;
dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
}
/**
* Releases a host channel for use by other transfers. Attempts to select and
* queue more transactions since at least one host channel is available.
*
* @param hcd The HCD state structure.
* @param hc The host channel to release.
* @param qtd The QTD associated with the host channel. This QTD may be freed
* if the transfer is complete or an error has occurred.
* @param halt_status Reason the channel is being released. This status
* determines the actions taken by this function.
*/
static void release_channel(dwc_otg_hcd_t * hcd,
dwc_hc_t * hc,
dwc_otg_qtd_t * qtd,
dwc_otg_halt_status_e halt_status)
{
dwc_otg_transaction_type_e tr_type;
int free_qtd;
dwc_irqflags_t flags;
dwc_spinlock_t *channel_lock = hcd->channel_lock;
DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n",
__func__, hc->hc_num, halt_status, hc->xfer_len);
switch (halt_status) {
case DWC_OTG_HC_XFER_URB_COMPLETE:
free_qtd = 1;
break;
case DWC_OTG_HC_XFER_AHB_ERR:
case DWC_OTG_HC_XFER_STALL:
case DWC_OTG_HC_XFER_BABBLE_ERR:
free_qtd = 1;
break;
case DWC_OTG_HC_XFER_XACT_ERR:
if (qtd->error_count >= 3) {
DWC_DEBUGPL(DBG_HCDV,
" Complete URB with transaction error\n");
free_qtd = 1;
qtd->urb->status = -DWC_E_PROTOCOL;
hcd->fops->complete(hcd, qtd->urb->priv,
qtd->urb, -DWC_E_PROTOCOL);
} else {
free_qtd = 0;
}
break;
case DWC_OTG_HC_XFER_URB_DEQUEUE:
/*
* The QTD has already been removed and the QH has been
* deactivated. Don't want to do anything except release the
* host channel and try to queue more transfers.
*/
goto cleanup;
case DWC_OTG_HC_XFER_NO_HALT_STATUS:
free_qtd = 0;
break;
case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
DWC_DEBUGPL(DBG_HCDV,
" Complete URB with I/O error\n");
free_qtd = 1;
qtd->urb->status = -DWC_E_IO;
hcd->fops->complete(hcd, qtd->urb->priv,
qtd->urb, -DWC_E_IO);
break;
default:
free_qtd = 0;
break;
}
deactivate_qh(hcd, hc->qh, free_qtd);
cleanup:
/*
* Release the host channel for use by other transfers. The cleanup
* function clears the channel interrupt enables and conditions, so
* there's no need to clear the Channel Halted interrupt separately.
*/
dwc_otg_hc_cleanup(hcd->core_if, hc);
DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
if (!microframe_schedule) {
switch (hc->ep_type) {
case DWC_OTG_EP_TYPE_CONTROL:
case DWC_OTG_EP_TYPE_BULK:
hcd->non_periodic_channels--;
break;
default:
/*
* Don't release reservations for periodic channels here.
* That's done when a periodic transfer is descheduled (i.e.