/
dwc_otg_driver.c
1732 lines (1591 loc) · 55.2 KB
/
dwc_otg_driver.c
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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
* $Revision: #92 $
* $Date: 2012/08/10 $
* $Change: 2047372 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
/** @file
* The dwc_otg_driver module provides the initialization and cleanup entry
* points for the DWC_otg driver. This module will be dynamically installed
* after Linux is booted using the insmod command. When the module is
* installed, the dwc_otg_driver_init function is called. When the module is
* removed (using rmmod), the dwc_otg_driver_cleanup function is called.
*
* This module also defines a data structure for the dwc_otg_driver, which is
* used in conjunction with the standard ARM lm_device structure. These
* structures allow the OTG driver to comply with the standard Linux driver
* model in which devices and drivers are registered with a bus driver. This
* has the benefit that Linux can expose attributes of the driver and device
* in its special sysfs file system. Users can then read or write files in
* this file system to perform diagnostics on the driver components or the
* device.
*/
#include "dwc_otg_os_dep.h"
#include "dwc_os.h"
#include "dwc_otg_dbg.h"
#include "dwc_otg_driver.h"
#include "dwc_otg_attr.h"
#include "dwc_otg_core_if.h"
#include "dwc_otg_pcd_if.h"
#include "dwc_otg_hcd_if.h"
#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012"
#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
bool microframe_schedule=true;
static const char dwc_driver_name[] = "dwc_otg";
extern void* dummy_send;
extern int pcd_init(
#ifdef LM_INTERFACE
struct lm_device *_dev
#elif defined(PCI_INTERFACE)
struct pci_dev *_dev
#elif defined(PLATFORM_INTERFACE)
struct platform_device *dev
#endif
);
extern int hcd_init(
#ifdef LM_INTERFACE
struct lm_device *_dev
#elif defined(PCI_INTERFACE)
struct pci_dev *_dev
#elif defined(PLATFORM_INTERFACE)
struct platform_device *dev
#endif
);
extern int pcd_remove(
#ifdef LM_INTERFACE
struct lm_device *_dev
#elif defined(PCI_INTERFACE)
struct pci_dev *_dev
#elif defined(PLATFORM_INTERFACE)
struct platform_device *_dev
#endif
);
extern void hcd_remove(
#ifdef LM_INTERFACE
struct lm_device *_dev
#elif defined(PCI_INTERFACE)
struct pci_dev *_dev
#elif defined(PLATFORM_INTERFACE)
struct platform_device *_dev
#endif
);
extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
/*-------------------------------------------------------------------------*/
/* Encapsulate the module parameter settings */
struct dwc_otg_driver_module_params {
int32_t opt;
int32_t otg_cap;
int32_t dma_enable;
int32_t dma_desc_enable;
int32_t dma_burst_size;
int32_t speed;
int32_t host_support_fs_ls_low_power;
int32_t host_ls_low_power_phy_clk;
int32_t enable_dynamic_fifo;
int32_t data_fifo_size;
int32_t dev_rx_fifo_size;
int32_t dev_nperio_tx_fifo_size;
uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
int32_t host_rx_fifo_size;
int32_t host_nperio_tx_fifo_size;
int32_t host_perio_tx_fifo_size;
int32_t max_transfer_size;
int32_t max_packet_count;
int32_t host_channels;
int32_t dev_endpoints;
int32_t phy_type;
int32_t phy_utmi_width;
int32_t phy_ulpi_ddr;
int32_t phy_ulpi_ext_vbus;
int32_t i2c_enable;
int32_t ulpi_fs_ls;
int32_t ts_dline;
int32_t en_multiple_tx_fifo;
uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
uint32_t thr_ctl;
uint32_t tx_thr_length;
uint32_t rx_thr_length;
int32_t pti_enable;
int32_t mpi_enable;
int32_t lpm_enable;
int32_t ic_usb_cap;
int32_t ahb_thr_ratio;
int32_t power_down;
int32_t reload_ctl;
int32_t dev_out_nak;
int32_t cont_on_bna;
int32_t ahb_single;
int32_t otg_ver;
int32_t adp_enable;
};
static struct dwc_otg_driver_module_params dwc_otg_module_params = {
.opt = -1,
.otg_cap = -1,
.dma_enable = -1,
.dma_desc_enable = -1,
.dma_burst_size = -1,
.speed = -1,
.host_support_fs_ls_low_power = -1,
.host_ls_low_power_phy_clk = -1,
.enable_dynamic_fifo = -1,
.data_fifo_size = -1,
.dev_rx_fifo_size = -1,
.dev_nperio_tx_fifo_size = -1,
.dev_perio_tx_fifo_size = {
/* dev_perio_tx_fifo_size_1 */
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1
/* 15 */
},
.host_rx_fifo_size = -1,
.host_nperio_tx_fifo_size = -1,
.host_perio_tx_fifo_size = -1,
.max_transfer_size = -1,
.max_packet_count = -1,
.host_channels = -1,
.dev_endpoints = -1,
.phy_type = -1,
.phy_utmi_width = -1,
.phy_ulpi_ddr = -1,
.phy_ulpi_ext_vbus = -1,
.i2c_enable = -1,
.ulpi_fs_ls = -1,
.ts_dline = -1,
.en_multiple_tx_fifo = -1,
.dev_tx_fifo_size = {
/* dev_tx_fifo_size */
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1
/* 15 */
},
.thr_ctl = -1,
.tx_thr_length = -1,
.rx_thr_length = -1,
.pti_enable = -1,
.mpi_enable = -1,
.lpm_enable = -1,
.ic_usb_cap = -1,
.ahb_thr_ratio = -1,
.power_down = -1,
.reload_ctl = -1,
.dev_out_nak = -1,
.cont_on_bna = -1,
.ahb_single = -1,
.otg_ver = -1,
.adp_enable = -1,
};
//Global variable to switch the fiq fix on or off
bool fiq_fix_enable = true;
//Global variable to switch the nak holdoff on or off
bool nak_holdoff_enable = true;
/**
* This function shows the Driver Version.
*/
static ssize_t version_show(struct device_driver *dev, char *buf)
{
return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
DWC_DRIVER_VERSION);
}
static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
/**
* Global Debug Level Mask.
*/
uint32_t g_dbg_lvl = 0; /* OFF */
/**
* This function shows the driver Debug Level.
*/
static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
{
return sprintf(buf, "0x%0x\n", g_dbg_lvl);
}
/**
* This function stores the driver Debug Level.
*/
static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
size_t count)
{
g_dbg_lvl = simple_strtoul(buf, NULL, 16);
return count;
}
static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
dbg_level_store);
/**
* This function is called during module intialization
* to pass module parameters to the DWC_OTG CORE.
*/
static int set_parameters(dwc_otg_core_if_t * core_if)
{
int retval = 0;
int i;
if (dwc_otg_module_params.otg_cap != -1) {
retval +=
dwc_otg_set_param_otg_cap(core_if,
dwc_otg_module_params.otg_cap);
}
if (dwc_otg_module_params.dma_enable != -1) {
retval +=
dwc_otg_set_param_dma_enable(core_if,
dwc_otg_module_params.
dma_enable);
}
if (dwc_otg_module_params.dma_desc_enable != -1) {
retval +=
dwc_otg_set_param_dma_desc_enable(core_if,
dwc_otg_module_params.
dma_desc_enable);
}
if (dwc_otg_module_params.opt != -1) {
retval +=
dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
}
if (dwc_otg_module_params.dma_burst_size != -1) {
retval +=
dwc_otg_set_param_dma_burst_size(core_if,
dwc_otg_module_params.
dma_burst_size);
}
if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
retval +=
dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
dwc_otg_module_params.
host_support_fs_ls_low_power);
}
if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
retval +=
dwc_otg_set_param_enable_dynamic_fifo(core_if,
dwc_otg_module_params.
enable_dynamic_fifo);
}
if (dwc_otg_module_params.data_fifo_size != -1) {
retval +=
dwc_otg_set_param_data_fifo_size(core_if,
dwc_otg_module_params.
data_fifo_size);
}
if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
retval +=
dwc_otg_set_param_dev_rx_fifo_size(core_if,
dwc_otg_module_params.
dev_rx_fifo_size);
}
if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
retval +=
dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
dwc_otg_module_params.
dev_nperio_tx_fifo_size);
}
if (dwc_otg_module_params.host_rx_fifo_size != -1) {
retval +=
dwc_otg_set_param_host_rx_fifo_size(core_if,
dwc_otg_module_params.host_rx_fifo_size);
}
if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
retval +=
dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
dwc_otg_module_params.
host_nperio_tx_fifo_size);
}
if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
retval +=
dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
dwc_otg_module_params.
host_perio_tx_fifo_size);
}
if (dwc_otg_module_params.max_transfer_size != -1) {
retval +=
dwc_otg_set_param_max_transfer_size(core_if,
dwc_otg_module_params.
max_transfer_size);
}
if (dwc_otg_module_params.max_packet_count != -1) {
retval +=
dwc_otg_set_param_max_packet_count(core_if,
dwc_otg_module_params.
max_packet_count);
}
if (dwc_otg_module_params.host_channels != -1) {
retval +=
dwc_otg_set_param_host_channels(core_if,
dwc_otg_module_params.
host_channels);
}
if (dwc_otg_module_params.dev_endpoints != -1) {
retval +=
dwc_otg_set_param_dev_endpoints(core_if,
dwc_otg_module_params.
dev_endpoints);
}
if (dwc_otg_module_params.phy_type != -1) {
retval +=
dwc_otg_set_param_phy_type(core_if,
dwc_otg_module_params.phy_type);
}
if (dwc_otg_module_params.speed != -1) {
retval +=
dwc_otg_set_param_speed(core_if,
dwc_otg_module_params.speed);
}
if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
retval +=
dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
dwc_otg_module_params.
host_ls_low_power_phy_clk);
}
if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
retval +=
dwc_otg_set_param_phy_ulpi_ddr(core_if,
dwc_otg_module_params.
phy_ulpi_ddr);
}
if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
retval +=
dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
dwc_otg_module_params.
phy_ulpi_ext_vbus);
}
if (dwc_otg_module_params.phy_utmi_width != -1) {
retval +=
dwc_otg_set_param_phy_utmi_width(core_if,
dwc_otg_module_params.
phy_utmi_width);
}
if (dwc_otg_module_params.ulpi_fs_ls != -1) {
retval +=
dwc_otg_set_param_ulpi_fs_ls(core_if,
dwc_otg_module_params.ulpi_fs_ls);
}
if (dwc_otg_module_params.ts_dline != -1) {
retval +=
dwc_otg_set_param_ts_dline(core_if,
dwc_otg_module_params.ts_dline);
}
if (dwc_otg_module_params.i2c_enable != -1) {
retval +=
dwc_otg_set_param_i2c_enable(core_if,
dwc_otg_module_params.
i2c_enable);
}
if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
retval +=
dwc_otg_set_param_en_multiple_tx_fifo(core_if,
dwc_otg_module_params.
en_multiple_tx_fifo);
}
for (i = 0; i < 15; i++) {
if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
retval +=
dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
dwc_otg_module_params.
dev_perio_tx_fifo_size
[i], i);
}
}
for (i = 0; i < 15; i++) {
if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
dwc_otg_module_params.
dev_tx_fifo_size
[i], i);
}
}
if (dwc_otg_module_params.thr_ctl != -1) {
retval +=
dwc_otg_set_param_thr_ctl(core_if,
dwc_otg_module_params.thr_ctl);
}
if (dwc_otg_module_params.mpi_enable != -1) {
retval +=
dwc_otg_set_param_mpi_enable(core_if,
dwc_otg_module_params.
mpi_enable);
}
if (dwc_otg_module_params.pti_enable != -1) {
retval +=
dwc_otg_set_param_pti_enable(core_if,
dwc_otg_module_params.
pti_enable);
}
if (dwc_otg_module_params.lpm_enable != -1) {
retval +=
dwc_otg_set_param_lpm_enable(core_if,
dwc_otg_module_params.
lpm_enable);
}
if (dwc_otg_module_params.ic_usb_cap != -1) {
retval +=
dwc_otg_set_param_ic_usb_cap(core_if,
dwc_otg_module_params.
ic_usb_cap);
}
if (dwc_otg_module_params.tx_thr_length != -1) {
retval +=
dwc_otg_set_param_tx_thr_length(core_if,
dwc_otg_module_params.tx_thr_length);
}
if (dwc_otg_module_params.rx_thr_length != -1) {
retval +=
dwc_otg_set_param_rx_thr_length(core_if,
dwc_otg_module_params.
rx_thr_length);
}
if (dwc_otg_module_params.ahb_thr_ratio != -1) {
retval +=
dwc_otg_set_param_ahb_thr_ratio(core_if,
dwc_otg_module_params.ahb_thr_ratio);
}
if (dwc_otg_module_params.power_down != -1) {
retval +=
dwc_otg_set_param_power_down(core_if,
dwc_otg_module_params.power_down);
}
if (dwc_otg_module_params.reload_ctl != -1) {
retval +=
dwc_otg_set_param_reload_ctl(core_if,
dwc_otg_module_params.reload_ctl);
}
if (dwc_otg_module_params.dev_out_nak != -1) {
retval +=
dwc_otg_set_param_dev_out_nak(core_if,
dwc_otg_module_params.dev_out_nak);
}
if (dwc_otg_module_params.cont_on_bna != -1) {
retval +=
dwc_otg_set_param_cont_on_bna(core_if,
dwc_otg_module_params.cont_on_bna);
}
if (dwc_otg_module_params.ahb_single != -1) {
retval +=
dwc_otg_set_param_ahb_single(core_if,
dwc_otg_module_params.ahb_single);
}
if (dwc_otg_module_params.otg_ver != -1) {
retval +=
dwc_otg_set_param_otg_ver(core_if,
dwc_otg_module_params.otg_ver);
}
if (dwc_otg_module_params.adp_enable != -1) {
retval +=
dwc_otg_set_param_adp_enable(core_if,
dwc_otg_module_params.
adp_enable);
}
return retval;
}
/**
* This function is the top level interrupt handler for the Common
* (Device and host modes) interrupts.
*/
static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
{
int32_t retval = IRQ_NONE;
retval = dwc_otg_handle_common_intr(dev);
if (retval != 0) {
S3C2410X_CLEAR_EINTPEND();
}
return IRQ_RETVAL(retval);
}
/**
* This function is called when a lm_device is unregistered with the
* dwc_otg_driver. This happens, for example, when the rmmod command is
* executed. The device may or may not be electrically present. If it is
* present, the driver stops device processing. Any resources used on behalf
* of this device are freed.
*
* @param _dev
*/
#ifdef LM_INTERFACE
#define REM_RETVAL(n)
static void dwc_otg_driver_remove( struct lm_device *_dev )
{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
#elif defined(PCI_INTERFACE)
#define REM_RETVAL(n)
static void dwc_otg_driver_remove( struct pci_dev *_dev )
{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
#elif defined(PLATFORM_INTERFACE)
#define REM_RETVAL(n) n
static int dwc_otg_driver_remove( struct platform_device *_dev )
{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
#endif
DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
if (!otg_dev) {
/* Memory allocation for the dwc_otg_device failed. */
DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
return REM_RETVAL(-ENOMEM);
}
#ifndef DWC_DEVICE_ONLY
if (otg_dev->hcd) {
hcd_remove(_dev);
} else {
DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
return REM_RETVAL(-EINVAL);
}
#endif
#ifndef DWC_HOST_ONLY
if (otg_dev->pcd) {
pcd_remove(_dev);
} else {
DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
return REM_RETVAL(-EINVAL);
}
#endif
/*
* Free the IRQ
*/
if (otg_dev->common_irq_installed) {
#ifdef PLATFORM_INTERFACE
free_irq(platform_get_irq(_dev, 0), otg_dev);
#else
free_irq(_dev->irq, otg_dev);
#endif
} else {
DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
return REM_RETVAL(-ENXIO);
}
if (otg_dev->core_if) {
dwc_otg_cil_remove(otg_dev->core_if);
} else {
DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
return REM_RETVAL(-ENXIO);
}
/*
* Remove the device attributes
*/
dwc_otg_attr_remove(_dev);
/*
* Return the memory.
*/
if (otg_dev->os_dep.base) {
iounmap(otg_dev->os_dep.base);
}
DWC_FREE(otg_dev);
/*
* Clear the drvdata pointer.
*/
#ifdef LM_INTERFACE
lm_set_drvdata(_dev, 0);
#elif defined(PCI_INTERFACE)
release_mem_region(otg_dev->os_dep.rsrc_start,
otg_dev->os_dep.rsrc_len);
pci_set_drvdata(_dev, 0);
#elif defined(PLATFORM_INTERFACE)
platform_set_drvdata(_dev, 0);
#endif
return REM_RETVAL(0);
}
/**
* This function is called when an lm_device is bound to a
* dwc_otg_driver. It creates the driver components required to
* control the device (CIL, HCD, and PCD) and it initializes the
* device. The driver components are stored in a dwc_otg_device
* structure. A reference to the dwc_otg_device is saved in the
* lm_device. This allows the driver to access the dwc_otg_device
* structure on subsequent calls to driver methods for this device.
*
* @param _dev Bus device
*/
static int dwc_otg_driver_probe(
#ifdef LM_INTERFACE
struct lm_device *_dev
#elif defined(PCI_INTERFACE)
struct pci_dev *_dev,
const struct pci_device_id *id
#elif defined(PLATFORM_INTERFACE)
struct platform_device *_dev
#endif
)
{
int retval = 0;
dwc_otg_device_t *dwc_otg_device;
int devirq;
dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
#ifdef LM_INTERFACE
dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
#elif defined(PCI_INTERFACE)
if (!id) {
DWC_ERROR("Invalid pci_device_id %p", id);
return -EINVAL;
}
if (!_dev || (pci_enable_device(_dev) < 0)) {
DWC_ERROR("Invalid pci_device %p", _dev);
return -ENODEV;
}
dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
/* other stuff needed as well? */
#elif defined(PLATFORM_INTERFACE)
dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
(unsigned)_dev->resource->start,
(unsigned)(_dev->resource->end - _dev->resource->start));
#endif
dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
if (!dwc_otg_device) {
dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
return -ENOMEM;
}
memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
/*
* Map the DWC_otg Core memory into virtual address space.
*/
#ifdef LM_INTERFACE
dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
if (!dwc_otg_device->os_dep.base) {
dev_err(&_dev->dev, "ioremap() failed\n");
DWC_FREE(dwc_otg_device);
return -ENOMEM;
}
dev_dbg(&_dev->dev, "base=0x%08x\n",
(unsigned)dwc_otg_device->os_dep.base);
#elif defined(PCI_INTERFACE)
_dev->current_state = PCI_D0;
_dev->dev.power.power_state = PMSG_ON;
if (!_dev->irq) {
DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
pci_name(_dev));
iounmap(dwc_otg_device->os_dep.base);
DWC_FREE(dwc_otg_device);
return -ENODEV;
}
dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
(unsigned)dwc_otg_device->os_dep.rsrc_start,
(unsigned)dwc_otg_device->os_dep.rsrc_len);
if (!request_mem_region
(dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
"dwc_otg")) {
dev_dbg(&_dev->dev, "error requesting memory\n");
iounmap(dwc_otg_device->os_dep.base);
DWC_FREE(dwc_otg_device);
return -EFAULT;
}
dwc_otg_device->os_dep.base =
ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
dwc_otg_device->os_dep.rsrc_len);
if (dwc_otg_device->os_dep.base == NULL) {
dev_dbg(&_dev->dev, "error mapping memory\n");
release_mem_region(dwc_otg_device->os_dep.rsrc_start,
dwc_otg_device->os_dep.rsrc_len);
iounmap(dwc_otg_device->os_dep.base);
DWC_FREE(dwc_otg_device);
return -EFAULT;
}
dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
dwc_otg_device->os_dep.base);
dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
dwc_otg_device->os_dep.base);
dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
(unsigned)dwc_otg_device->os_dep.rsrc_start,
dwc_otg_device->os_dep.base);
pci_set_master(_dev);
pci_set_drvdata(_dev, dwc_otg_device);
#elif defined(PLATFORM_INTERFACE)
DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
_dev->resource->start,
_dev->resource->end - _dev->resource->start + 1);
#if 1
if (!request_mem_region(_dev->resource[0].start,
_dev->resource[0].end - _dev->resource[0].start + 1,
"dwc_otg")) {
dev_dbg(&_dev->dev, "error reserving mapped memory\n");
retval = -EFAULT;
goto fail;
}
dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start,
_dev->resource[0].end -
_dev->resource[0].start+1);
if (fiq_fix_enable)
{
if (!request_mem_region(_dev->resource[1].start,
_dev->resource[1].end - _dev->resource[1].start + 1,
"dwc_otg")) {
dev_dbg(&_dev->dev, "error reserving mapped memory\n");
retval = -EFAULT;
goto fail;
}
dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start,
_dev->resource[1].end -
_dev->resource[1].start + 1);
dummy_send = (void *) kmalloc(16, GFP_ATOMIC);
}
#else
{
struct map_desc desc = {
.virtual = IO_ADDRESS((unsigned)_dev->resource->start),
.pfn = __phys_to_pfn((unsigned)_dev->resource->start),
.length = SZ_128K,
.type = MT_DEVICE
};
iotable_init(&desc, 1);
dwc_otg_device->os_dep.base = (void *)desc.virtual;
}
#endif
if (!dwc_otg_device->os_dep.base) {
dev_err(&_dev->dev, "ioremap() failed\n");
retval = -ENOMEM;
goto fail;
}
dev_dbg(&_dev->dev, "base=0x%08x\n",
(unsigned)dwc_otg_device->os_dep.base);
#endif
/*
* Initialize driver data to point to the global DWC_otg
* Device structure.
*/
#ifdef LM_INTERFACE
lm_set_drvdata(_dev, dwc_otg_device);
#elif defined(PLATFORM_INTERFACE)
platform_set_drvdata(_dev, dwc_otg_device);
#endif
dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
dwc_otg_device, dwc_otg_device->core_if);//GRAYG
if (!dwc_otg_device->core_if) {
dev_err(&_dev->dev, "CIL initialization failed!\n");
retval = -ENOMEM;
goto fail;
}
dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
/*
* Attempt to ensure this device is really a DWC_otg Controller.
* Read and verify the SNPSID register contents. The value should be
* 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
* as in "OTG version 2.XX" or "OTG version 3.XX".
*/
if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
retval = -EINVAL;
goto fail;
}
/*
* Validate parameter values.
*/
dev_dbg(&_dev->dev, "Calling set_parameters\n");
if (set_parameters(dwc_otg_device->core_if)) {
retval = -EINVAL;
goto fail;
}
/*
* Create Device Attributes in sysfs
*/
dev_dbg(&_dev->dev, "Calling attr_create\n");
dwc_otg_attr_create(_dev);
/*
* Disable the global interrupt until all the interrupt
* handlers are installed.
*/
dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
/*
* Install the interrupt handler for the common interrupts before
* enabling common interrupts in core_init below.
*/
#if defined(PLATFORM_INTERFACE)
devirq = platform_get_irq(_dev, 0);
#else
devirq = _dev->irq;
#endif
DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
devirq);
dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
retval = request_irq(devirq, dwc_otg_common_irq,
IRQF_SHARED,
"dwc_otg", dwc_otg_device);
if (retval) {
DWC_ERROR("request of irq%d failed\n", devirq);
retval = -EBUSY;
goto fail;
} else {
dwc_otg_device->common_irq_installed = 1;
}
#ifndef IRQF_TRIGGER_LOW
#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
dev_dbg(&_dev->dev, "Calling set_irq_type\n");
set_irq_type(devirq,
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
IRQT_LOW
#else
IRQ_TYPE_LEVEL_LOW
#endif
);
#endif
#endif /*IRQF_TRIGGER_LOW*/
/*
* Initialize the DWC_otg core.
*/
dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
dwc_otg_core_init(dwc_otg_device->core_if);
#ifndef DWC_HOST_ONLY
/*
* Initialize the PCD
*/
dev_dbg(&_dev->dev, "Calling pcd_init\n");
retval = pcd_init(_dev);
if (retval != 0) {
DWC_ERROR("pcd_init failed\n");
dwc_otg_device->pcd = NULL;
goto fail;
}
#endif
#ifndef DWC_DEVICE_ONLY
/*
* Initialize the HCD
*/
dev_dbg(&_dev->dev, "Calling hcd_init\n");
retval = hcd_init(_dev);
if (retval != 0) {
DWC_ERROR("hcd_init failed\n");
dwc_otg_device->hcd = NULL;
goto fail;
}
#endif
/* Recover from drvdata having been overwritten by hcd_init() */
#ifdef LM_INTERFACE
lm_set_drvdata(_dev, dwc_otg_device);
#elif defined(PLATFORM_INTERFACE)
platform_set_drvdata(_dev, dwc_otg_device);
#elif defined(PCI_INTERFACE)
pci_set_drvdata(_dev, dwc_otg_device);
dwc_otg_device->os_dep.pcidev = _dev;
#endif
/*
* Enable the global interrupt after all the interrupt
* handlers are installed if there is no ADP support else
* perform initial actions required for Internal ADP logic.
*/
if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
dev_dbg(&_dev->dev, "Done\n");
} else
dwc_otg_adp_start(dwc_otg_device->core_if,
dwc_otg_is_host_mode(dwc_otg_device->core_if));
return 0;
fail:
dwc_otg_driver_remove(_dev);
return retval;
}
/**
* This structure defines the methods to be called by a bus driver
* during the lifecycle of a device on that bus. Both drivers and
* devices are registered with a bus driver. The bus driver matches
* devices to drivers based on information in the device and driver
* structures.