-
Notifications
You must be signed in to change notification settings - Fork 4.9k
/
dwc-i2s.c
1217 lines (1023 loc) · 30.1 KB
/
dwc-i2s.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* ALSA SoC Synopsys I2S Audio Layer
*
* sound/soc/dwc/designware_i2s.c
*
* Copyright (C) 2010 ST Microelectronics
* Rajeev Kumar <rajeevkumar.linux@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <sound/designware_i2s.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/dmaengine_pcm.h>
#include "local.h"
static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
{
writel(val, io_base + reg);
}
static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
{
return readl(io_base + reg);
}
static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
{
u32 i = 0;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
for (i = 0; i < 4; i++)
i2s_write_reg(dev->i2s_base, TER(i), 0);
} else {
for (i = 0; i < 4; i++)
i2s_write_reg(dev->i2s_base, RER(i), 0);
}
}
static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
{
u32 i = 0;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
for (i = 0; i < 4; i++)
i2s_read_reg(dev->i2s_base, TOR(i));
} else {
for (i = 0; i < 4; i++)
i2s_read_reg(dev->i2s_base, ROR(i));
}
}
static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
int chan_nr)
{
u32 i, irq;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
for (i = 0; i < (chan_nr / 2); i++) {
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
}
} else {
for (i = 0; i < (chan_nr / 2); i++) {
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
}
}
}
static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
int chan_nr)
{
u32 i, irq;
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
for (i = 0; i < (chan_nr / 2); i++) {
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
}
} else {
for (i = 0; i < (chan_nr / 2); i++) {
irq = i2s_read_reg(dev->i2s_base, IMR(i));
i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
}
}
}
static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
{
struct dw_i2s_dev *dev = dev_id;
bool irq_valid = false;
u32 isr[4];
int i;
for (i = 0; i < 4; i++)
isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
for (i = 0; i < 4; i++) {
/*
* Check if TX fifo is empty. If empty fill FIFO with samples
* NOTE: Only two channels supported
*/
if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
dw_pcm_push_tx(dev);
irq_valid = true;
}
/*
* Data available. Retrieve samples from FIFO
* NOTE: Only two channels supported
*/
if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
dw_pcm_pop_rx(dev);
irq_valid = true;
}
/* Error Handling: TX */
if (isr[i] & ISR_TXFO) {
dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i);
irq_valid = true;
}
/* Error Handling: TX */
if (isr[i] & ISR_RXFO) {
dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i);
irq_valid = true;
}
}
if (irq_valid)
return IRQ_HANDLED;
else
return IRQ_NONE;
}
static void i2s_enable_dma(struct dw_i2s_dev *dev, u32 stream)
{
u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);
/* Enable DMA handshake for stream */
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_reg |= I2S_DMAEN_TXBLOCK;
else
dma_reg |= I2S_DMAEN_RXBLOCK;
i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);
}
static void i2s_disable_dma(struct dw_i2s_dev *dev, u32 stream)
{
u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);
/* Disable DMA handshake for stream */
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
dma_reg &= ~I2S_DMAEN_TXBLOCK;
i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1);
} else {
dma_reg &= ~I2S_DMAEN_RXBLOCK;
i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1);
}
i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);
}
static void i2s_start(struct dw_i2s_dev *dev,
struct snd_pcm_substream *substream)
{
struct i2s_clk_config_data *config = &dev->config;
u32 reg = IER_IEN;
if (dev->tdm_slots) {
reg |= (dev->tdm_slots - 1) << IER_TDM_SLOTS_SHIFT;
reg |= IER_INTF_TYPE;
reg |= dev->frame_offset << IER_FRAME_OFF_SHIFT;
}
i2s_write_reg(dev->i2s_base, IER, reg);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
i2s_write_reg(dev->i2s_base, ITER, 1);
else
i2s_write_reg(dev->i2s_base, IRER, 1);
/* I2S needs to enable IRQ to make a handshake with DMAC on the JH7110 SoC */
if (dev->use_pio || dev->is_jh7110)
i2s_enable_irqs(dev, substream->stream, config->chan_nr);
else
i2s_enable_dma(dev, substream->stream);
i2s_write_reg(dev->i2s_base, CER, 1);
}
static void i2s_stop(struct dw_i2s_dev *dev,
struct snd_pcm_substream *substream)
{
if (dev->is_jh7110) {
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai_link *dai_link = rtd->dai_link;
dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC;
}
i2s_clear_irqs(dev, substream->stream);
i2s_disable_irqs(dev, substream->stream, 8);
}
static void i2s_pause(struct dw_i2s_dev *dev,
struct snd_pcm_substream *substream)
{
i2s_clear_irqs(dev, substream->stream);
if (dev->use_pio || dev->is_jh7110)
i2s_disable_irqs(dev, substream->stream, 8);
else
i2s_disable_dma(dev, substream->stream);
if (!dev->active) {
i2s_write_reg(dev->i2s_base, CER, 0);
/* Keep the device enabled until the shutdown - do not clear IER */
}
}
static void dw_i2s_config(struct dw_i2s_dev *dev, int stream);
static int dw_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
union dw_i2s_snd_dma_data *dma_data = NULL;
u32 dmacr;
dev_dbg(dev->dev, "%s(%s)\n", __func__, substream->name);
if (!(dev->capability & DWC_I2S_RECORD) &&
substream->stream == SNDRV_PCM_STREAM_CAPTURE)
return -EINVAL;
if (!(dev->capability & DWC_I2S_PLAY) &&
substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return -EINVAL;
dw_i2s_config(dev, substream->stream);
dmacr = i2s_read_reg(dev->i2s_base, I2S_DMACR);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_data = &dev->play_dma_data;
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
dma_data = &dev->capture_dma_data;
snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
i2s_write_reg(dev->i2s_base, I2S_DMACR, dmacr);
if (dev->is_jh7110) {
struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
struct snd_soc_dai_link *dai_link = rtd->dai_link;
dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC;
}
return 0;
}
static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
dev_dbg(dev->dev, "%s(%s)\n", __func__, substream->name);
i2s_disable_channels(dev, substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
i2s_write_reg(dev->i2s_base, ITER, 0);
else
i2s_write_reg(dev->i2s_base, IRER, 0);
i2s_disable_irqs(dev, substream->stream, 8);
if (!dev->active) {
i2s_write_reg(dev->i2s_base, CER, 0);
i2s_write_reg(dev->i2s_base, IER, 0);
}
}
static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
{
u32 ch_reg;
struct i2s_clk_config_data *config = &dev->config;
u32 dmacr = 0;
i2s_disable_channels(dev, stream);
for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
i2s_write_reg(dev->i2s_base, TCR(ch_reg),
dev->xfer_resolution);
i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
dev->fifo_th - 1);
i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN |
dev->tdm_mask << TER_TXSLOT_SHIFT);
dmacr |= (DMACR_DMAEN_TXCH0 << ch_reg);
} else {
i2s_write_reg(dev->i2s_base, RCR(ch_reg),
dev->xfer_resolution);
i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
dev->fifo_th - 1);
i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN |
dev->tdm_mask << RER_RXSLOT_SHIFT);
dmacr |= (DMACR_DMAEN_RXCH0 << ch_reg);
}
}
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
dmacr |= DMACR_DMAEN_TX;
else if (stream == SNDRV_PCM_STREAM_CAPTURE)
dmacr |= DMACR_DMAEN_RX;
i2s_write_reg(dev->i2s_base, I2S_DMACR, dmacr);
}
static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
struct i2s_clk_config_data *config = &dev->config;
union dw_i2s_snd_dma_data *dma_data = NULL;
int ret;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
dma_data = &dev->play_dma_data;
else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
dma_data = &dev->capture_dma_data;
else
return -1;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
config->data_width = 16;
dma_data->dt.addr_width = 2;
dev->ccr = 0x00;
dev->xfer_resolution = 0x02;
break;
case SNDRV_PCM_FORMAT_S24_LE:
config->data_width = 24;
dma_data->dt.addr_width = 4;
dev->ccr = 0x08;
dev->xfer_resolution = 0x04;
break;
case SNDRV_PCM_FORMAT_S32_LE:
config->data_width = 32;
dma_data->dt.addr_width = 4;
dev->ccr = 0x10;
dev->xfer_resolution = 0x05;
break;
default:
dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
return -EINVAL;
}
if (dev->tdm_slots)
config->data_width = 32;
config->chan_nr = params_channels(params);
switch (config->chan_nr) {
case EIGHT_CHANNEL_SUPPORT:
case SIX_CHANNEL_SUPPORT:
case FOUR_CHANNEL_SUPPORT:
case TWO_CHANNEL_SUPPORT:
break;
default:
dev_err(dev->dev, "channel not supported\n");
return -EINVAL;
}
dw_i2s_config(dev, substream->stream);
i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
config->sample_rate = params_rate(params);
if (dev->capability & DW_I2S_MASTER) {
if (dev->i2s_clk_cfg) {
ret = dev->i2s_clk_cfg(config);
if (ret < 0) {
dev_err(dev->dev, "runtime audio clk config fail\n");
return ret;
}
} else {
u32 bitclk = config->sample_rate *
config->data_width * 2;
ret = clk_set_rate(dev->clk, bitclk);
if (ret) {
dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
ret);
return ret;
}
}
}
return 0;
}
static int dw_i2s_prepare(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
i2s_write_reg(dev->i2s_base, TXFFR, 1);
else
i2s_write_reg(dev->i2s_base, RXFFR, 1);
return 0;
}
static int dw_i2s_trigger(struct snd_pcm_substream *substream,
int cmd, struct snd_soc_dai *dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
int ret = 0;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
dev->active++;
i2s_start(dev, substream);
break;
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
dev->active--;
i2s_pause(dev, substream);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
dev->active--;
i2s_stop(dev, substream);
break;
default:
ret = -EINVAL;
break;
}
return ret;
}
static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
int ret = 0;
switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
case SND_SOC_DAIFMT_BC_FC:
if (dev->capability & DW_I2S_SLAVE)
ret = 0;
else
ret = -EINVAL;
break;
case SND_SOC_DAIFMT_BP_FP:
if (dev->capability & DW_I2S_MASTER)
ret = 0;
else
ret = -EINVAL;
break;
case SND_SOC_DAIFMT_BC_FP:
case SND_SOC_DAIFMT_BP_FC:
ret = -EINVAL;
break;
default:
dev_dbg(dev->dev, "dwc : Invalid clock provider format\n");
ret = -EINVAL;
break;
}
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
case SND_SOC_DAIFMT_LEFT_J:
case SND_SOC_DAIFMT_RIGHT_J:
break;
case SND_SOC_DAIFMT_DSP_A:
dev->frame_offset = 1;
break;
case SND_SOC_DAIFMT_DSP_B:
dev->frame_offset = 0;
break;
default:
dev_err(dev->dev, "DAI format unsupported");
return -EINVAL;
}
return ret;
}
static int dw_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai, unsigned int tx_mask,
unsigned int rx_mask, int slots, int slot_width)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
if (slot_width != 32)
return -EINVAL;
if (slots < 0 || slots > 16)
return -EINVAL;
if (rx_mask != tx_mask)
return -EINVAL;
if (!rx_mask)
return -EINVAL;
dev->tdm_slots = slots;
dev->tdm_mask = rx_mask;
dev->l_reg = RSLOT_TSLOT(ffs(rx_mask) - 1);
dev->r_reg = RSLOT_TSLOT(fls(rx_mask) - 1);
return 0;
}
static int dw_i2s_set_bclk_ratio(struct snd_soc_dai *cpu_dai,
unsigned int ratio)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
dev_dbg(dev->dev, "%s(%d)\n", __func__, ratio);
switch (ratio) {
case 32:
dev->ccr = 0x00;
break;
case 48:
dev->ccr = 0x08;
break;
case 64:
dev->ccr = 0x10;
break;
default:
return -EINVAL;
}
i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
return 0;
}
static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
{
struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
return 0;
}
static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
.probe = dw_i2s_dai_probe,
.startup = dw_i2s_startup,
.shutdown = dw_i2s_shutdown,
.hw_params = dw_i2s_hw_params,
.prepare = dw_i2s_prepare,
.trigger = dw_i2s_trigger,
.set_fmt = dw_i2s_set_fmt,
.set_tdm_slot = dw_i2s_set_tdm_slot,
.set_bclk_ratio = dw_i2s_set_bclk_ratio,
};
#ifdef CONFIG_PM
static int dw_i2s_runtime_suspend(struct device *dev)
{
struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
if (dw_dev->capability & DW_I2S_MASTER)
clk_disable(dw_dev->clk);
return 0;
}
static int dw_i2s_runtime_resume(struct device *dev)
{
struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
int ret;
if (dw_dev->capability & DW_I2S_MASTER) {
ret = clk_enable(dw_dev->clk);
if (ret)
return ret;
}
return 0;
}
static int dw_i2s_suspend(struct snd_soc_component *component)
{
struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
if (dev->capability & DW_I2S_MASTER)
clk_disable(dev->clk);
return 0;
}
static int dw_i2s_resume(struct snd_soc_component *component)
{
struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
struct snd_soc_dai *dai;
int stream, ret;
if (dev->capability & DW_I2S_MASTER) {
ret = clk_enable(dev->clk);
if (ret)
return ret;
}
for_each_component_dais(component, dai) {
for_each_pcm_streams(stream)
if (snd_soc_dai_stream_active(dai, stream))
dw_i2s_config(dev, stream);
}
return 0;
}
#else
#define dw_i2s_suspend NULL
#define dw_i2s_resume NULL
#endif
static const struct snd_soc_component_driver dw_i2s_component = {
.name = "dw-i2s",
.suspend = dw_i2s_suspend,
.resume = dw_i2s_resume,
.legacy_dai_naming = 1,
};
/*
* The following tables allow a direct lookup of various parameters
* defined in the I2S block's configuration in terms of sound system
* parameters. Each table is sized to the number of entries possible
* according to the number of configuration bits describing an I2S
* block parameter.
*/
/* Maximum bit resolution of a channel - not uniformly spaced */
static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
12, 16, 20, 24, 32, 0, 0, 0
};
/* Width of (DMA) bus */
static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
DMA_SLAVE_BUSWIDTH_1_BYTE,
DMA_SLAVE_BUSWIDTH_2_BYTES,
DMA_SLAVE_BUSWIDTH_4_BYTES,
DMA_SLAVE_BUSWIDTH_UNDEFINED
};
/* PCM format to support channel resolution */
static const u32 formats[COMP_MAX_WORDSIZE] = {
SNDRV_PCM_FMTBIT_S16_LE,
SNDRV_PCM_FMTBIT_S16_LE,
SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
0,
0,
0
};
static int dw_configure_dai(struct dw_i2s_dev *dev,
struct snd_soc_dai_driver *dw_i2s_dai,
unsigned int rates)
{
/*
* Read component parameter registers to extract
* the I2S block's configuration.
*/
u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
u32 idx;
if (dev->capability & DWC_I2S_RECORD &&
dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
comp1 = comp1 & ~BIT(5);
if (dev->capability & DWC_I2S_PLAY &&
dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
comp1 = comp1 & ~BIT(6);
if (COMP1_TX_ENABLED(comp1)) {
dev_dbg(dev->dev, " designware: play supported\n");
idx = COMP1_TX_WORDSIZE_0(comp1);
if (WARN_ON(idx >= ARRAY_SIZE(formats)))
return -EINVAL;
if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
idx = 1;
dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
dw_i2s_dai->playback.channels_max =
1 << (COMP1_TX_CHANNELS(comp1) + 1);
dw_i2s_dai->playback.formats = formats[idx];
dw_i2s_dai->playback.rates = rates;
}
if (COMP1_RX_ENABLED(comp1)) {
dev_dbg(dev->dev, "designware: record supported\n");
idx = COMP2_RX_WORDSIZE_0(comp2);
if (WARN_ON(idx >= ARRAY_SIZE(formats)))
return -EINVAL;
if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
idx = 1;
dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
dw_i2s_dai->capture.channels_max =
1 << (COMP1_RX_CHANNELS(comp1) + 1);
dw_i2s_dai->capture.formats = formats[idx];
dw_i2s_dai->capture.rates = rates;
}
if (COMP1_MODE_EN(comp1)) {
dev_dbg(dev->dev, "designware: i2s master mode supported\n");
dev->capability |= DW_I2S_MASTER;
} else {
dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
dev->capability |= DW_I2S_SLAVE;
}
dev->fifo_th = fifo_depth / 2;
return 0;
}
static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
struct snd_soc_dai_driver *dw_i2s_dai,
struct resource *res,
const struct i2s_platform_data *pdata)
{
u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
u32 idx = COMP1_APB_DATA_WIDTH(comp1);
int ret;
if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
return -EINVAL;
ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
if (ret < 0)
return ret;
if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
idx = 1;
if (dev->is_jh7110) {
/* Use platform data and snd_dmaengine_dai_dma_data struct at the same time */
u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
u32 idx2;
if (COMP1_TX_ENABLED(comp1)) {
idx2 = COMP1_TX_WORDSIZE_0(comp1);
dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
dev->play_dma_data.dt.fifo_size = dev->fifo_th * 2 *
(fifo_width[idx2]) >> 8;
dev->play_dma_data.dt.maxburst = 16;
}
if (COMP1_RX_ENABLED(comp1)) {
idx2 = COMP2_RX_WORDSIZE_0(comp2);
dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
dev->capture_dma_data.dt.fifo_size = dev->fifo_th * 2 *
(fifo_width[idx2] >> 8);
dev->capture_dma_data.dt.maxburst = 16;
}
} else {
/* Set DMA slaves info */
dev->play_dma_data.pd.data = pdata->play_dma_data;
dev->capture_dma_data.pd.data = pdata->capture_dma_data;
dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
dev->play_dma_data.pd.max_burst = 16;
dev->capture_dma_data.pd.max_burst = 16;
dev->play_dma_data.pd.addr_width = bus_widths[idx];
dev->capture_dma_data.pd.addr_width = bus_widths[idx];
dev->play_dma_data.pd.filter = pdata->filter;
dev->capture_dma_data.pd.filter = pdata->filter;
}
return 0;
}
static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
struct snd_soc_dai_driver *dw_i2s_dai,
struct resource *res)
{
u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
u32 idx2;
int ret;
ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_384000);
if (ret < 0)
return ret;
if (COMP1_TX_ENABLED(comp1)) {
idx2 = COMP1_TX_WORDSIZE_0(comp1);
dev->capability |= DWC_I2S_PLAY;
dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
dev->play_dma_data.dt.fifo_size = fifo_depth *
(fifo_width[idx2]) >> 8;
dev->play_dma_data.dt.maxburst = 16;
}
if (COMP1_RX_ENABLED(comp1)) {
idx2 = COMP2_RX_WORDSIZE_0(comp2);
dev->capability |= DWC_I2S_RECORD;
dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
dev->capture_dma_data.dt.fifo_size = fifo_depth *
(fifo_width[idx2] >> 8);
dev->capture_dma_data.dt.maxburst = 16;
}
return 0;
}
#ifdef CONFIG_OF
/* clocks initialization with master mode on JH7110 SoC */
static int jh7110_i2s_crg_master_init(struct dw_i2s_dev *dev)
{
static struct clk_bulk_data clks[] = {
{ .id = "mclk" },
{ .id = "mclk_ext" },
{ .id = "mclk_inner" },
{ .id = "apb" },
{ .id = "i2sclk" },
};
struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev);
int ret;
struct clk *pclk;
struct clk *bclk_mst;
struct clk *mclk;
struct clk *mclk_ext;
struct clk *mclk_inner;
if (IS_ERR(resets))
return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n");
ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks);
if (ret)
return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n");
mclk = clks[0].clk;
mclk_ext = clks[1].clk;
mclk_inner = clks[2].clk;
pclk = clks[3].clk;
bclk_mst = clks[4].clk;
ret = clk_prepare_enable(pclk);
if (ret)
goto exit;
/* Use inner mclk first and avoid uninitialized gpio for external mclk */
ret = clk_set_parent(mclk, mclk_inner);
if (ret)
goto err_dis_pclk;
ret = clk_prepare_enable(bclk_mst);
if (ret)
goto err_dis_pclk;
/* deassert resets before set clock parent */
ret = reset_control_deassert(resets);
if (ret)
goto err_dis_all;
/* external clock (12.288MHz) for Audio */
ret = clk_set_parent(mclk, mclk_ext);
if (ret)
goto err_dis_all;
/* i2sclk will be got and enabled repeatedly later and should be disabled now. */
clk_disable_unprepare(bclk_mst);
clk_bulk_put(ARRAY_SIZE(clks), clks);
dev->is_jh7110 = true;
return 0;
err_dis_all:
clk_disable_unprepare(bclk_mst);
err_dis_pclk:
clk_disable_unprepare(pclk);
exit:
clk_bulk_put(ARRAY_SIZE(clks), clks);
return ret;
}
/* clocks initialization with slave mode on JH7110 SoC */
static int jh7110_i2s_crg_slave_init(struct dw_i2s_dev *dev)
{
static struct clk_bulk_data clks[] = {
{ .id = "mclk" },
{ .id = "mclk_ext" },
{ .id = "apb" },
{ .id = "bclk_ext" },
{ .id = "lrck_ext" },
{ .id = "bclk" },
{ .id = "lrck" },
{ .id = "mclk_inner" },
{ .id = "i2sclk" },
};
struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev);
int ret;
struct clk *pclk;
struct clk *bclk_mst;
struct clk *bclk_ext;
struct clk *lrck_ext;
struct clk *bclk;
struct clk *lrck;
struct clk *mclk;
struct clk *mclk_ext;
struct clk *mclk_inner;
if (IS_ERR(resets))
return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n");
ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks);
if (ret)
return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n");
mclk = clks[0].clk;
mclk_ext = clks[1].clk;
pclk = clks[2].clk;
bclk_ext = clks[3].clk;
lrck_ext = clks[4].clk;
bclk = clks[5].clk;
lrck = clks[6].clk;
mclk_inner = clks[7].clk;
bclk_mst = clks[8].clk;
ret = clk_prepare_enable(pclk);
if (ret)
goto exit;
ret = clk_set_parent(mclk, mclk_inner);
if (ret)
goto err_dis_pclk;
ret = clk_prepare_enable(bclk_mst);
if (ret)
goto err_dis_pclk;
ret = reset_control_deassert(resets);
if (ret)
goto err_dis_all;
/* The sources of BCLK and LRCK are the external codec. */
ret = clk_set_parent(bclk, bclk_ext);
if (ret)
goto err_dis_all;
ret = clk_set_parent(lrck, lrck_ext);
if (ret)
goto err_dis_all;
ret = clk_set_parent(mclk, mclk_ext);
if (ret)
goto err_dis_all;
/* The i2sclk will be got and enabled repeatedly later and should be disabled now. */
clk_disable_unprepare(bclk_mst);
clk_bulk_put(ARRAY_SIZE(clks), clks);
dev->is_jh7110 = true;
return 0;
err_dis_all:
clk_disable_unprepare(bclk_mst);
err_dis_pclk:
clk_disable_unprepare(pclk);
exit:
clk_bulk_put(ARRAY_SIZE(clks), clks);
return ret;
}
/* Special syscon initialization about RX channel with slave mode on JH7110 SoC */
static int jh7110_i2srx_crg_init(struct dw_i2s_dev *dev)
{
struct regmap *regmap;
unsigned int args[2];
regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node,
"starfive,syscon",