/
usb_halinit.c
executable file
·6261 lines (5229 loc) · 173 KB
/
usb_halinit.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _HCI_HAL_INIT_C_
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
#include <rtw_efuse.h>
#include <rtl8192c_hal.h>
#include <rtl8192c_led.h>
#ifdef DBG_CONFIG_ERROR_DETECT
#include "rtl8192c_sreset.h"
#endif
#ifdef CONFIG_IOL
#include <rtw_iol.h>
#endif
#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
#error "Shall be Linux or Windows, but not both!\n"
#endif
#ifndef CONFIG_USB_HCI
#error "CONFIG_USB_HCI shall be on!\n"
#endif
#include <usb_ops.h>
#include <usb_hal.h>
#include <usb_osintf.h>
#if DISABLE_BB_RF
#define HAL_MAC_ENABLE 0
#define HAL_BB_ENABLE 0
#define HAL_RF_ENABLE 0
#else
#define HAL_MAC_ENABLE 1
#define HAL_BB_ENABLE 1
#define HAL_RF_ENABLE 1
#endif
//endpoint number 1,2,3,4,5
// bult in : 1
// bult out: 2 (High)
// bult out: 3 (Normal) for 3 out_ep, (Low) for 2 out_ep
// interrupt in: 4
// bult out: 5 (Low) for 3 out_ep
static VOID
_OneOutEpMapping(
IN HAL_DATA_TYPE *pHalData
)
{
//only endpoint number 0x02
pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO
pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[0];//VI
pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[0];//BE
pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[0];//BK
pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN
pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT
pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH
pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD
}
static VOID
_TwoOutEpMapping(
IN HAL_DATA_TYPE *pHalData,
IN BOOLEAN bWIFICfg
)
{
/*
#define VO_QUEUE_INX 0
#define VI_QUEUE_INX 1
#define BE_QUEUE_INX 2
#define BK_QUEUE_INX 3
#define BCN_QUEUE_INX 4
#define MGT_QUEUE_INX 5
#define HIGH_QUEUE_INX 6
#define TXCMD_QUEUE_INX 7
*/
if(bWIFICfg){ // Normal chip && wmm
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 0, 1, 0, 1, 0, 0, 0, 0, 0 };
//0:H(end_number=0x02), 1:L (end_number=0x03)
pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[1];//VO
pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[0];//VI
pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[1];//BE
pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[0];//BK
pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN
pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT
pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH
pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD
}
else{//typical setting
//BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 1, 1, 0, 0, 0, 0, 0, 0, 0 };
//0:H(end_number=0x02), 1:L (end_number=0x03)
pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO
pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[0];//VI
pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[1];//BE
pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[1];//BK
pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN
pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT
pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH
pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD
}
}
static VOID _ThreeOutEpMapping(
IN HAL_DATA_TYPE *pHalData,
IN BOOLEAN bWIFICfg
)
{
if(bWIFICfg){//for WMM
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 1, 2, 1, 0, 0, 0, 0, 0, 0 };
//0:H(end_number=0x02), 1:N(end_number=0x03), 2:L (end_number=0x05)
pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO
pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[1];//VI
pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[2];//BE
pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[1];//BK
pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN
pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT
pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH
pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD
}
else{//typical setting
// BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA
//{ 2, 2, 1, 0, 0, 0, 0, 0, 0 };
//0:H(end_number=0x02), 1:N(end_number=0x03), 2:L (end_number=0x05)
pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO
pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[1];//VI
pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[2];//BE
pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[2];//BK
pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN
pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT
pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH
pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD
}
}
static BOOLEAN
_MappingOutEP(
IN PADAPTER pAdapter,
IN u8 NumOutPipe
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
BOOLEAN bWIFICfg = (pregistrypriv->wifi_spec) ?_TRUE:_FALSE;
BOOLEAN result = _TRUE;
switch(NumOutPipe)
{
case 2:
_TwoOutEpMapping(pHalData, bWIFICfg);
break;
case 3:
_ThreeOutEpMapping(pHalData, bWIFICfg);
break;
case 1:
_OneOutEpMapping(pHalData);
break;
default:
result = _FALSE;
break;
}
return result;
}
static VOID
_ConfigChipOutEP(
IN PADAPTER pAdapter,
IN u8 NumOutPipe
)
{
u8 value8;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
pHalData->OutEpQueueSel = 0;
pHalData->OutEpNumber = 0;
// Normal and High queue
value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 1));
if(value8 & USB_NORMAL_SIE_EP_MASK){
pHalData->OutEpQueueSel |= TX_SELE_HQ;
pHalData->OutEpNumber++;
}
#ifdef CONFIG_USB_ONE_OUT_EP
return;
#endif
if((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK){
pHalData->OutEpQueueSel |= TX_SELE_NQ;
pHalData->OutEpNumber++;
}
// Low queue
value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 2));
if(value8 & USB_NORMAL_SIE_EP_MASK){
pHalData->OutEpQueueSel |= TX_SELE_LQ;
pHalData->OutEpNumber++;
}
// TODO: Error recovery for this case
//RT_ASSERT((NumOutPipe == pHalData->OutEpNumber), ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n", (u4Byte)NumOutPipe, (u4Byte)pHalData->OutEpNumber));
}
static BOOLEAN HalUsbSetQueuePipeMapping8192CUsb(
IN PADAPTER pAdapter,
IN u8 NumInPipe,
IN u8 NumOutPipe
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
BOOLEAN result = _FALSE;
_ConfigChipOutEP(pAdapter, NumOutPipe);
#ifndef CONFIG_USB_ONE_OUT_EP
// Normal chip with one IN and one OUT doesn't have interrupt IN EP.
if(1 == pHalData->OutEpNumber){
if(1 != NumInPipe){
return result;
}
}
#endif
result = _MappingOutEP(pAdapter, NumOutPipe);
return result;
}
void rtl8192cu_interface_configure(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
if (pdvobjpriv->ishighspeed == _TRUE)
{
pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
}
else
{
pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
}
pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
pHalData->RtBulkInPipe = pdvobjpriv->ep_num[0];
pHalData->RtBulkOutPipe[0] = pdvobjpriv->ep_num[1];
pHalData->RtBulkOutPipe[1] = pdvobjpriv->ep_num[2];
pHalData->RtIntInPipe = pdvobjpriv->ep_num[3];
pHalData->RtBulkOutPipe[2] = pdvobjpriv->ep_num[4];
#ifdef CONFIG_USB_TX_AGGREGATION
pHalData->UsbTxAggMode = 1;
pHalData->UsbTxAggDescNum = 0x6; // only 4 bits
#endif
#ifdef CONFIG_USB_RX_AGGREGATION
pHalData->UsbRxAggMode = USB_RX_AGG_DMA;// USB_RX_AGG_DMA;
pHalData->UsbRxAggBlockCount = 8; //unit : 512b
pHalData->UsbRxAggBlockTimeout = 0x6;
pHalData->UsbRxAggPageCount = 48; //uint :128 b //0x0A; // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize
pHalData->UsbRxAggPageTimeout = 0x4; //6, absolute time = 34ms/(2^6)
#endif
HalUsbSetQueuePipeMapping8192CUsb(padapter, pdvobjpriv->RtNumInPipes,
#ifdef CONFIG_USB_ONE_OUT_EP
1
#else
pdvobjpriv->RtNumOutPipes
#endif
);
}
static u8 _InitPowerOn(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
u8 ret = _SUCCESS;
u16 value16=0;
u8 value8 = 0;
u32 value32 = 0;
// polling autoload done.
u32 pollingCount = 0;
do
{
if(rtw_read8(padapter, REG_APS_FSMCO) & PFM_ALDN){
//RT_TRACE(COMP_INIT,DBG_LOUD,("Autoload Done!\n"));
break;
}
if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){
//RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n"));
return _FAIL;
}
}while(_TRUE);
// For hardware power on sequence.
//0. RSV_CTRL 0x1C[7:0] = 0x00 // unlock ISO/CLK/Power control register
rtw_write8(padapter, REG_RSV_CTRL, 0x0);
// Power on when re-enter from IPS/Radio off/card disable
rtw_write8(padapter, REG_SPS0_CTRL, 0x2b);//enable SPS into PWM mode
/*
value16 = PlatformIORead2Byte(Adapter, REG_AFE_XTAL_CTRL);//enable AFE clock
value16 &= (~XTAL_GATE_AFE);
PlatformIOWrite2Byte(Adapter,REG_AFE_XTAL_CTRL, value16 );
*/
rtw_udelay_os(100);//PlatformSleepUs(150);//this is not necessary when initially power on
value8 = rtw_read8(padapter, REG_LDOV12D_CTRL);
if(0== (value8 & LDV12_EN) ){
value8 |= LDV12_EN;
rtw_write8(padapter, REG_LDOV12D_CTRL, value8);
//RT_TRACE(COMP_INIT, DBG_LOUD, (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8));
rtw_udelay_os(100);//PlatformSleepUs(100);//this is not necessary when initially power on
value8 = rtw_read8(padapter, REG_SYS_ISO_CTRL);
value8 &= ~ISO_MD2PP;
rtw_write8(padapter, REG_SYS_ISO_CTRL, value8);
}
// auto enable WLAN
pollingCount = 0;
value16 = rtw_read16(padapter, REG_APS_FSMCO);
value16 |= APFM_ONMAC;
rtw_write16(padapter, REG_APS_FSMCO, value16);
do
{
if(0 == (rtw_read16(padapter, REG_APS_FSMCO) & APFM_ONMAC)){
//RT_TRACE(COMP_INIT,DBG_LOUD,("MAC auto ON okay!\n"));
break;
}
if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){
//RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n"));
return _FAIL;
}
}while(_TRUE);
//Enable Radio ,GPIO ,and LED function
rtw_write16(padapter,REG_APS_FSMCO,0x0812);
#ifdef CONFIG_AUTOSUSPEND
//for usb Combo card ,BT
if((BOARD_USB_COMBO == pHalData->BoardType)&&(padapter->registrypriv.usbss_enable))
{
value32 = rtw_read32(padapter, REG_APS_FSMCO);
value32 |= (SOP_ABG|SOP_AMB|XOP_BTCK);
rtw_write32(padapter, REG_APS_FSMCO, value32);
}
#endif
// release RF digital isolation
value16 = rtw_read16(padapter, REG_SYS_ISO_CTRL);
value16 &= ~ISO_DIOR;
rtw_write16(padapter, REG_SYS_ISO_CTRL, value16);
// Enable MAC DMA/WMAC/SCHEDULE/SEC block
value16 = rtw_read16(padapter, REG_CR);
value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
| PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
rtw_write16(padapter, REG_CR, value16);
//tynli_test for suspend mode.
{
rtw_write8(padapter, 0xfe10, 0x19);
}
// 2010/11/22 MH For slim combo debug mode check.
if (pHalData->BoardType == BOARD_USB_COMBO)
{
if (pHalData->SlimComboDbg == _TRUE)
{
DBG_8192C("SlimComboDbg == TRUE\n");
// 1. SIC?Test Mode 中, Debug Ports 會自動 Enable, 所以 Driver 上來後,
// 要關掉請設定 0x 00[7] -> "1", 將它 Disable. effect if not: power consumption increase
rtw_write8(padapter, REG_SYS_ISO_CTRL, rtw_read8(padapter, REG_SYS_ISO_CTRL)|BIT7);
// 2. SIC?Test Mode 中, GPIO-8?會 report Power State 所以 Driver 上來後, 請設定? 0x04[6] -> "1" 將它 Disable
// effect if not: GPIO-8 could not be GPIO or LED function
rtw_write8(padapter, REG_APS_FSMCO, rtw_read8(padapter, REG_APS_FSMCO)|BIT6);
// 3. SIC Test Mode 中, EESK, EECS 會 report?Host Clock status, 所以 Driver 上來後, 請設定? 0x40[4] -> "1" 將它切成 EEPROM 使用 Pin (autoload still from Efuse)
// effect if not:power consumption increase
value8 = rtw_read8(padapter, REG_GPIO_MUXCFG)|BIT4 ;
#ifdef CONFIG_BT_COEXIST
// 2011/01/26 MH UMB-B cut bug. We need to support the modification.
if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) &&
pHalData->bt_coexist.BT_Coexist)
{
value8 |= (BIT5);
}
#endif
rtw_write8(padapter, REG_GPIO_MUXCFG,value8 );
// 4. SIC Test Mode 中,?SIC Debug ports 會自動 Enable , 所以 Driver 上來後馬上, 請設定? 0x40[15:11] -> “0x00”, 將它Disable
// 4.1Two Steps setting for safety: 0x40[15,13,12, 11] -> "0", then ?0x40[14] -> "0"
// effect if not: Host could not transfer packets, and GPIO-3,2 will occupied by SIC then Co-exist could not work.
rtw_write16(padapter, REG_GPIO_MUXCFG, (rtw_read16(padapter, REG_GPIO_MUXCFG)&0x07FF)|BIT14);
rtw_write16(padapter, REG_GPIO_MUXCFG, rtw_read16(padapter, REG_GPIO_MUXCFG)&0x07FF);
}
}
// 2011/02/18 To Fix RU LNA power leakage problem. We need to execute below below in
// Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all
// IC. According to Johnny's opinion, only RU will meet the condition.
if (IS_HARDWARE_TYPE_8192C(padapter) && (pHalData->BoardType == BOARD_USB_High_PA))
rtw_write32(padapter, rFPGA0_XCD_RFParameter, rtw_read32(padapter, rFPGA0_XCD_RFParameter)&(~BIT1));
return ret;
}
static void _dbg_dump_macreg(_adapter *padapter)
{
u32 offset = 0;
u32 val32 = 0;
u32 index =0 ;
for(index=0;index<64;index++)
{
offset = index*4;
val32 = rtw_read32(padapter,offset);
DBG_8192C("offset : 0x%02x ,val:0x%08x\n",offset,val32);
}
}
static void _InitPABias(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
u8 pa_setting;
BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID);
//FIXED PA current issue
//efuse_one_byte_read(padapter, 0x1FA, &pa_setting);
pa_setting = EFUSE_Read1Byte(padapter, 0x1FA);
//RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting));
if(!(pa_setting & BIT0))
{
PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
//RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n"));
}
if(!(pa_setting & BIT1) && is92C)
{
PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
PHY_SetRFReg(padapter,RF_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
//RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n"));
}
if(!(pa_setting & BIT4))
{
pa_setting = rtw_read8(padapter, 0x16);
pa_setting &= 0x0F;
rtw_write8(padapter, 0x16, pa_setting | 0x90);
}
}
#ifdef CONFIG_BT_COEXIST
static void _InitBTCoexist(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist);
u8 u1Tmp;
if(pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4)
{
#if MP_DRIVER != 1
if(pbtpriv->BT_Ant_isolation)
{
rtw_write8( padapter,REG_GPIO_MUXCFG, 0xa0);
DBG_8192C("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0);
}
#endif
u1Tmp = rtw_read8(padapter, 0x4fd) & BIT0;
u1Tmp = u1Tmp |
((pbtpriv->BT_Ant_isolation==1)?0:BIT1) |
((pbtpriv->BT_Service==BT_SCO)?0:BIT2);
rtw_write8( padapter, 0x4fd, u1Tmp);
DBG_8192C("BT write 0x%x = 0x%x for non-isolation\n", 0x4fd, u1Tmp);
rtw_write32(padapter, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
rtw_write32(padapter, REG_BT_COEX_TABLE+8, 0xffbd0040);
DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+8, 0xffbd0040);
rtw_write32(padapter, REG_BT_COEX_TABLE+0xc, 0x40000010);
DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+0xc, 0x40000010);
//Config to 1T1R
u1Tmp = rtw_read8(padapter,rOFDM0_TRxPathEnable);
u1Tmp &= ~(BIT1);
rtw_write8( padapter, rOFDM0_TRxPathEnable, u1Tmp);
DBG_8192C("BT write 0xC04 = 0x%x\n", u1Tmp);
u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable);
u1Tmp &= ~(BIT1);
rtw_write8( padapter, rOFDM1_TRxPathEnable, u1Tmp);
DBG_8192C("BT write 0xD04 = 0x%x\n", u1Tmp);
}
}
#endif
//-------------------------------------------------------------------------
//
// LLT R/W/Init function
//
//-------------------------------------------------------------------------
static u8 _LLTWrite(
IN PADAPTER Adapter,
IN u32 address,
IN u32 data
)
{
u8 status = _SUCCESS;
int count = 0;
u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
rtw_write32(Adapter, REG_LLT_INIT, value);
//polling
do{
value = rtw_read32(Adapter, REG_LLT_INIT);
if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
break;
}
if(count > POLLING_LLT_THRESHOLD){
//RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling write LLT done at address %d!\n", address));
status = _FAIL;
break;
}
}while(count++);
return status;
}
static u8 _LLTRead(
IN PADAPTER Adapter,
IN u32 address
)
{
int count = 0;
u32 value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
rtw_write32(Adapter, REG_LLT_INIT, value);
//polling and get value
do{
value = rtw_read32(Adapter, REG_LLT_INIT);
if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
return (u8)value;
}
if(count > POLLING_LLT_THRESHOLD){
//RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling read LLT done at address %d!\n", address));
break;
}
}while(count++);
return 0xFF;
}
static u8 InitLLTTable(
IN PADAPTER Adapter,
IN u32 boundary
)
{
u8 status = _SUCCESS;
u32 i;
#ifdef CONFIG_IOL_LLT
if(rtw_IOL_applied(Adapter))
{
struct xmit_frame *xmit_frame;
if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
return _FAIL;
rtw_IOL_append_LLT_cmd(xmit_frame, boundary);
status = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
}
else
#endif
{
for(i = 0 ; i < (boundary - 1) ; i++){
status = _LLTWrite(Adapter, i , i + 1);
if(_SUCCESS != status){
return status;
}
}
// end of list
status = _LLTWrite(Adapter, (boundary - 1), 0xFF);
if(_SUCCESS != status){
return status;
}
// Make the other pages as ring buffer
// This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer.
// Otherwise used as local loopback buffer.
for(i = boundary ; i < LAST_ENTRY_OF_TX_PKT_BUFFER ; i++){
status = _LLTWrite(Adapter, i, (i + 1));
if(_SUCCESS != status){
return status;
}
}
// Let last entry point to the start entry of ring buffer
status = _LLTWrite(Adapter, LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
if(_SUCCESS != status){
return status;
}
}
return status;
}
//---------------------------------------------------------------
//
// MAC init functions
//
//---------------------------------------------------------------
static VOID
_SetMacID(
IN PADAPTER Adapter, u8* MacID
)
{
u32 i;
for(i=0 ; i< MAC_ADDR_LEN ; i++){
#ifdef CONFIG_CONCURRENT_MODE
if(Adapter->iface_type == IFACE_PORT1)
rtw_write32(Adapter, REG_MACID1+i, MacID[i]);
else
#endif
rtw_write32(Adapter, REG_MACID+i, MacID[i]);
}
}
static VOID
_SetBSSID(
IN PADAPTER Adapter, u8* BSSID
)
{
u32 i;
for(i=0 ; i< MAC_ADDR_LEN ; i++){
#ifdef CONFIG_CONCURRENT_MODE
if(Adapter->iface_type == IFACE_PORT1)
rtw_write32(Adapter, REG_BSSID1+i, BSSID[i]);
else
#endif
rtw_write32(Adapter, REG_BSSID+i, BSSID[i]);
}
}
// Shall USB interface init this?
static VOID
_InitInterrupt(
IN PADAPTER Adapter
)
{
u32 value32;
// HISR - turn all on
value32 = 0xFFFFFFFF;
rtw_write32(Adapter, REG_HISR, value32);
// HIMR - turn all on
rtw_write32(Adapter, REG_HIMR, value32);
}
static VOID
_InitQueueReservedPage(
IN PADAPTER Adapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
u32 outEPNum = (u32)pHalData->OutEpNumber;
u32 numHQ = 0;
u32 numLQ = 0;
u32 numNQ = 0;
u32 numPubQ;
u32 value32;
u8 value8;
BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
//u32 txQPageNum, txQPageUnit,txQRemainPage;
{ //for WMM
//RT_ASSERT((outEPNum>=2), ("for WMM ,number of out-ep must more than or equal to 2!\n"));
if(pHalData->OutEpQueueSel & TX_SELE_HQ){
numHQ = (bWiFiConfig)?WMM_NORMAL_PAGE_NUM_HPQ:NORMAL_PAGE_NUM_HPQ;
}
if(pHalData->OutEpQueueSel & TX_SELE_LQ){
numLQ = (bWiFiConfig)?WMM_NORMAL_PAGE_NUM_LPQ:NORMAL_PAGE_NUM_LPQ;
}
// NOTE: This step shall be proceed before writting REG_RQPN.
if(pHalData->OutEpQueueSel & TX_SELE_NQ){
numNQ = (bWiFiConfig)?WMM_NORMAL_PAGE_NUM_NPQ:NORMAL_PAGE_NUM_NPQ;
}
value8 = (u8)_NPQ(numNQ);
rtw_write8(Adapter, REG_RQPN_NPQ, value8);
if (bWiFiConfig)
numPubQ = WMM_NORMAL_TX_TOTAL_PAGE_NUMBER - numHQ - numLQ - numNQ;
else
numPubQ = TX_TOTAL_PAGE_NUMBER - numHQ - numLQ - numNQ;
}
// TX DMA
value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
rtw_write32(Adapter, REG_RQPN, value32);
}
static VOID
_InitTxBufferBoundary(
IN PADAPTER Adapter
)
{
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u8 txpktbuf_bndy;
if(!pregistrypriv->wifi_spec){
txpktbuf_bndy = TX_PAGE_BOUNDARY;
}
else{//for WMM
txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
}
rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
#if 1
rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
#else
txdmactrl = PlatformIORead2Byte(Adapter, REG_TDECTRL);
txdmactrl &= ~BCN_HEAD_MASK;
txdmactrl |= BCN_HEAD(txpktbuf_bndy);
PlatformIOWrite2Byte(Adapter, REG_TDECTRL, txdmactrl);
#endif
}
static VOID
_InitPageBoundary(
IN PADAPTER Adapter
)
{
// RX Page Boundary
//srand(static_cast<unsigned int>(time(NULL)) );
u16 rxff_bndy = 0x27FF;//(rand() % 1) ? 0x27FF : 0x23FF;
rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
// TODO: ?? shall we set tx boundary?
}
static VOID
_InitNormalChipRegPriority(
IN PADAPTER Adapter,
IN u16 beQ,
IN u16 bkQ,
IN u16 viQ,
IN u16 voQ,
IN u16 mgtQ,
IN u16 hiQ
)
{
u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
_TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
_TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
}
static VOID
_InitNormalChipOneOutEpPriority(
IN PADAPTER Adapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u16 value = 0;
switch(pHalData->OutEpQueueSel)
{
case TX_SELE_HQ:
value = QUEUE_HIGH;
break;
case TX_SELE_LQ:
value = QUEUE_LOW;
break;
case TX_SELE_NQ:
value = QUEUE_NORMAL;
break;
default:
//RT_ASSERT(FALSE,("Shall not reach here!\n"));
break;
}
_InitNormalChipRegPriority(Adapter,
value,
value,
value,
value,
value,
value
);
}
static VOID
_InitNormalChipTwoOutEpPriority(
IN PADAPTER Adapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ;
u16 valueHi = 0;
u16 valueLow = 0;
switch(pHalData->OutEpQueueSel)
{
case (TX_SELE_HQ | TX_SELE_LQ):
valueHi = QUEUE_HIGH;
valueLow = QUEUE_LOW;
break;
case (TX_SELE_NQ | TX_SELE_LQ):
valueHi = QUEUE_NORMAL;
valueLow = QUEUE_LOW;
break;
case (TX_SELE_HQ | TX_SELE_NQ):
valueHi = QUEUE_HIGH;
valueLow = QUEUE_NORMAL;
break;
default:
//RT_ASSERT(FALSE,("Shall not reach here!\n"));
break;
}
if(!pregistrypriv->wifi_spec ){
beQ = valueLow;
bkQ = valueLow;
viQ = valueHi;
voQ = valueHi;
mgtQ = valueHi;
hiQ = valueHi;
}
else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
beQ = valueLow;
bkQ = valueHi;
viQ = valueHi;
voQ = valueLow;
mgtQ = valueHi;
hiQ = valueHi;
}
_InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
}
static VOID
_InitNormalChipThreeOutEpPriority(
IN PADAPTER Adapter
)
{
struct registry_priv *pregistrypriv = &Adapter->registrypriv;
u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ;
if(!pregistrypriv->wifi_spec ){// typical setting
beQ = QUEUE_LOW;
bkQ = QUEUE_LOW;
viQ = QUEUE_NORMAL;
voQ = QUEUE_HIGH;
mgtQ = QUEUE_HIGH;
hiQ = QUEUE_HIGH;
}
else{// for WMM
beQ = QUEUE_LOW;
bkQ = QUEUE_NORMAL;
viQ = QUEUE_NORMAL;
voQ = QUEUE_HIGH;
mgtQ = QUEUE_HIGH;
hiQ = QUEUE_HIGH;
}
_InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
}
static VOID
_InitNormalChipQueuePriority(
IN PADAPTER Adapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
switch(pHalData->OutEpNumber)
{
case 1:
_InitNormalChipOneOutEpPriority(Adapter);
break;
case 2:
_InitNormalChipTwoOutEpPriority(Adapter);
break;
case 3:
_InitNormalChipThreeOutEpPriority(Adapter);
break;
default:
//RT_ASSERT(FALSE,("Shall not reach here!\n"));
break;
}