bcm2712-rpi.dtsi

// SPDX-License-Identifier: GPL-2.0

#include <dt-bindings/power/raspberrypi-power.h>

&soc {
	firmware: firmware {
		compatible = "raspberrypi,bcm2835-firmware", "simple-mfd";
		#address-cells = <1>;
		#size-cells = <1>;

		mboxes = <&mailbox>;
		dma-ranges;

		firmware_clocks: clocks {
			compatible = "raspberrypi,firmware-clocks";
			#clock-cells = <1>;
		};

		reset: reset {
			compatible = "raspberrypi,firmware-reset";
			#reset-cells = <1>;
		};

		vcio: vcio {
			compatible = "raspberrypi,vcio";
		};
	};

	power: power {
		compatible = "raspberrypi,bcm2835-power";
		firmware = <&firmware>;
		#power-domain-cells = <1>;
	};

	fb: fb {
		compatible = "brcm,bcm2708-fb";
		firmware = <&firmware>;
		status = "okay";
	};

	rpi_rtc: rpi_rtc {
		compatible = "raspberrypi,rpi-rtc";
		firmware = <&firmware>;
		status = "okay";
		trickle-charge-microvolt = <0>;
	};

	/* Define these notional regulators for use by overlays, etc. */
	vdd_3v3_reg: fixedregulator_3v3 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "3v3";
	};

	vdd_5v0_reg: fixedregulator_5v0 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "5v0";
	};
};

/ {
	__overrides__ {
		arm_freq;
	};
};

pciex1: &pcie1 { };
pciex4: &pcie2 { };

&dma32 {
	/* The VPU firmware uses DMA channel 11 for VCHIQ */
	brcm,dma-channel-mask = <0x03f>;
};

&dma40 {
	/* The VPU firmware DMA channel 11 for VCHIQ */
	brcm,dma-channel-mask = <0x07c0>;
};

&hdmi0 {
	dmas = <&dma40 (10|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
};

&hdmi1 {
	dmas = <&dma40 (17|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
};

&spi10 {
	dmas = <&dma40 6>, <&dma40 7>;
	dma-names = "tx", "rx";
};

&usb {
	power-domains = <&power RPI_POWER_DOMAIN_USB>;
};

&rmem {
	/*
	 * RPi4's co-processor will copy the board's bootloader configuration
	 * into memory for the OS to consume. It'll also update this node with
	 * its placement information.
	 */
	blconfig: nvram@0 {
		compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0 0x0 0x0>;
		no-map;
		status = "disabled";
	};
};

&rp1_adc {
	status = "okay";
};

/* Add some gpiomem nodes to make the devices accessible to userspace.
 * /dev/gpiomem<n> should expose the registers for the interface with DT alias
 * gpio<n>.
 */

&rp1 {
	gpiomem@d0000 {
		/* Export IO_BANKs, RIO_BANKs and PADS_BANKs to userspace */
		compatible = "raspberrypi,gpiomem";
		reg = <0xc0 0x400d0000  0x0 0x30000>;
		chardev-name = "gpiomem0";
	};
};

&soc {
	gpiomem@7d508500 {
		compatible = "raspberrypi,gpiomem";
		reg = <0x7d508500 0x40>;
		chardev-name = "gpiomem1";
	};

	gpiomem@7d517c00 {
		compatible = "raspberrypi,gpiomem";
		reg = <0x7d517c00 0x40>;
		chardev-name = "gpiomem2";
	};

	gpiomem@7d504100 {
		compatible = "raspberrypi,gpiomem";
		reg = <0x7d504100 0x20>;
		chardev-name = "gpiomem3";
	};

	gpiomem@7d510700 {
		compatible = "raspberrypi,gpiomem";
		reg = <0x7d510700 0x20>;
		chardev-name = "gpiomem4";
	};
};

i2c0: &rp1_i2c0 { };
i2c1: &rp1_i2c1 { };
i2c2: &rp1_i2c2 { };
i2c3: &rp1_i2c3 { };
i2c4: &rp1_i2c4 { };
i2c5: &rp1_i2c5 { };
i2c6: &rp1_i2c6 { };
i2s:  &rp1_i2s0 { };
i2s_clk_producer: &rp1_i2s0 { };
i2s_clk_consumer: &rp1_i2s1 { };
pwm0: &rp1_pwm0 { };
pwm1: &rp1_pwm1 { };
pwm: &pwm0 { };
spi0: &rp1_spi0 { };
spi1: &rp1_spi1 { };
spi2: &rp1_spi2 { };
spi3: &rp1_spi3 { };
spi4: &rp1_spi4 { };
spi5: &rp1_spi5 { };

uart0_pins: &rp1_uart0_14_15 {};
uart0_ctsrts_pins: &rp1_uart0_ctsrts_16_17 {};
uart0: &rp1_uart0 {
	pinctrl-0 = <&uart0_pins>;
};

uart1_pins: &rp1_uart1_0_1 {};
uart1_ctsrts_pins: &rp1_uart1_ctsrts_2_3 {};
uart1: &rp1_uart1 { };

uart2_pins: &rp1_uart2_4_5 {};
uart2_ctsrts_pins: &rp1_uart2_ctsrts_6_7 {};
uart2: &rp1_uart2 { };

uart3_pins: &rp1_uart3_8_9 {};
uart3_ctsrts_pins: &rp1_uart3_ctsrts_10_11 {};
uart3: &rp1_uart3 { };

uart4_pins: &rp1_uart4_12_13 {};
uart4_ctsrts_pins: &rp1_uart4_ctsrts_14_15 {};
uart4: &rp1_uart4 { };

i2c_vc: &i2c0 {      // This is pins 27,28 on the header (not MIPI)
	pinctrl-0 = <&rp1_i2c0_0_1>;
	pinctrl-names = "default";
	clock-frequency = <100000>;
};

i2c_arm: &i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&rp1_i2c1_2_3>;
	clock-frequency = <100000>;
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&rp1_i2c2_4_5>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&rp1_i2c3_6_7>;
};

&i2s_clk_producer {
	pinctrl-names = "default";
	pinctrl-0 = <&rp1_i2s0_18_21>;
};

&i2s_clk_consumer {
	pinctrl-names = "default";
	pinctrl-0 = <&rp1_i2s1_18_21>;
};

spi0_pins: &rp1_spi0_gpio9 {};
spi0_cs_pins: &rp1_spi0_cs_gpio7 {};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins &spi0_cs_pins>;
	cs-gpios = <&gpio 8 1>, <&gpio 7 1>;

	spidev0: spidev@0 {
		compatible = "spidev";
		reg = <0>;	/* CE0 */
		#address-cells = <1>;
		#size-cells = <0>;
		spi-max-frequency = <125000000>;
	};

	spidev1: spidev@1 {
		compatible = "spidev";
		reg = <1>;	/* CE1 */
		#address-cells = <1>;
		#size-cells = <0>;
		spi-max-frequency = <125000000>;
	};
};

spi2_pins: &rp1_spi2_gpio1 {};
&spi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi2_pins>;
};

spi3_pins: &rp1_spi3_gpio5 {};
&spi3 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi3_pins>;
};

spi4_pins: &rp1_spi4_gpio9 {};
&spi4 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi4_pins>;
};

spi5_pins: &rp1_spi5_gpio13 {};
&spi5 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi5_pins>;
};