clang compatible compile. Mac travis test setup.

tukl-msd · Feb 27, 2016 · e19154f · e19154f
1 parent 9345a5b
commit e19154f
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Showing 10 changed files with 99 additions and 78 deletions.
diff --git a/.travis.yml b/.travis.yml
@@ -1,11 +1,22 @@
+os:
+  - linux
+  - osx
+matrix:
+  allow_failures:
+    - os: osx
 language: cpp
 compiler:
   - gcc
+  - clang
 install:
   - echo "No install."
 before_install:
-  - sudo pip install cpp-coveralls
-  - sudo apt-get install -y libxerces-c-dev
-script: make test COVERAGE=1
+  - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then sudo pip install cpp-coveralls; fi
+  - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then sudo apt-get install -y libxerces-c-dev; fi
+  - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then brew update          ; fi
+  - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then brew install xerces-c; fi
+script:
+  - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then make test COVERAGE=1; fi
+  - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then make test; fi
 after_success:
-  - coveralls --exclude lib --exclude tests --gcov-options '\-lp'
+  - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then coveralls --exclude lib --exclude tests --gcov-options '\-lp'; fi
diff --git a/Makefile b/Makefile
@@ -41,9 +41,11 @@ BINARY := drampower
 LIBS := src/libdrampower.a src/libdrampowerxml.a
 
 # Identifies the source files and derives name of object files.
-CLISOURCES := $(wildcard src/*.cc) $(wildcard src/cli/*.cc)
+
+CLISOURCES := src/TraceParser.cc src/CmdScheduler.cc $(wildcard src/cli/*.cc)
+LIBSOURCES := $(wildcard src/libdrampower/*.cc) src/CommandAnalysis.cc src/MemArchitectureSpec.cc src/MemCommand.cc src/MemoryPowerModel.cc src/MemorySpecification.cc src/MemPowerSpec.cc src/MemTimingSpec.cc src/Parameter.cc src/Parametrisable.cc
+
 XMLPARSERSOURCES := $(wildcard src/xmlparser/*.cc)
-LIBSOURCES := $(wildcard src/*.cc src/libdrampower/*.cc)
 ALLSOURCES := $(wildcard src/cli/*.cc) $(wildcard src/*.cc) $(wildcard src/xmlparser/*.cc) $(wildcard src/libdrampower/*.cc)
 ALLHEADERS := $(wildcard src/*.h) $(wildcard src/xmlparser/*.h) $(wildcard src/libdrampower/*.h)
 
@@ -59,6 +61,7 @@ DEPENDENCIES := ${ALLSOURCES:.cc=.d}
 ##########################################
 
 # State what compiler we use.
+#clang++-3.6
 CXX := g++
 
 ifeq ($(COVERAGE),1)
@@ -74,13 +77,19 @@ OPTCXXFLAGS ?=
 # Debugging flags.
 DBGCXXFLAGS ?= -g ${GCOVFLAGS}
 
-# Common warning flags shared by both C and C++.
+# Warning flags
 WARNFLAGS := -W -pedantic-errors -Wextra -Werror \
              -Wformat -Wformat-nonliteral -Wpointer-arith \
              -Wcast-align -Wconversion -Wall -Werror
 
+# Warning flags for deprecated files
+DEPWARNFLAGS := -W -pedantic-errors -Wextra -Werror \
+             -Wformat -Wformat-nonliteral -Wpointer-arith \
+             -Wcast-align -Wall -Werror
+
 # Sum up the flags.
 CXXFLAGS := -O ${WARNFLAGS} ${DBGCXXFLAGS} ${OPTCXXFLAGS} -std=c++0x
+DEPCXXFLAGS := -O ${DEPWARNFLAGS} ${DBGCXXFLAGS} ${OPTCXXFLAGS} -std=c++0x
 
 # Linker flags.
 LDFLAGS := -Wall
@@ -98,16 +107,19 @@ XERCES_LDFLAGS := -L$(XERCES_LIB) -lxerces-c
 # Targets
 ##########################################
 
-all: ${BINARY} lib parserlib traces
+all: ${BINARY} src/libdrampower.a parserlib traces
+
+$(BINARY): ${XMLPARSEROBJECTS} ${CLIOBJECTS} src/libdrampower.a
+	$(CXX) ${CXXFLAGS} $(LDFLAGS) -o $@ $^ -Lsrc/ $(XERCES_LDFLAGS) -ldrampower
 
-$(BINARY): ${XMLPARSEROBJECTS} ${CLIOBJECTS}
-	$(CXX) ${CXXFLAGS} $(LDFLAGS) -o $@ $^ $(XERCES_LDFLAGS)
+src/CmdScheduler.o: src/CmdScheduler.cc
+	$(CXX) ${DEPCXXFLAGS} -MMD -MF $(subst .o,.d,$@) -iquote src -o $@ -c $<
 
 # From .cpp to .o. Dependency files are generated here
 %.o: %.cc
 	$(CXX) ${CXXFLAGS} -MMD -MF $(subst .o,.d,$@) -iquote src -o $@ -c $<
 
-lib: ${LIBOBJECTS}
+src/libdrampower.a: ${LIBOBJECTS}
 	ar -cvr src/libdrampower.a ${LIBOBJECTS}
 
 parserlib: ${XMLPARSEROBJECTS}

diff --git a/src/CmdScheduler.cc b/src/CmdScheduler.cc
@@ -84,9 +84,10 @@ void cmdScheduler::schedulingInitialization(const MemorySpecification& memSpec)
 {
   const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec;
 
-  ACT.resize(2 * memSpec.memArchSpec.nbrOfBanks);
-  RDWR.resize(2 * memSpec.memArchSpec.nbrOfBanks);
-  PRE.resize(memSpec.memArchSpec.nbrOfBanks);
+  const size_t numBanks = static_cast<size_t>(memSpec.memArchSpec.nbrOfBanks);
+  ACT.resize(2 * numBanks);
+  RDWR.resize(2 * numBanks);
+  PRE.resize(numBanks);
   bankaccess = memSpec.memArchSpec.nbrOfBanks;
   if (!ACT.empty()) {
     ACT.erase(ACT.begin(), ACT.end());
@@ -118,7 +119,7 @@ void cmdScheduler::schedulingInitialization(const MemorySpecification& memSpec)
     cmd.Type = WRITE;
     cmd.name = "WRITE";
     cmd.time = -1;
-    RDWR[i].push_back(cmd);
+    RDWR[static_cast<size_t>(i)].push_back(cmd);
   }
   tREF             = memTimingSpec.REFI;
   transFinish.time = 0;
@@ -141,7 +142,7 @@ void cmdScheduler::getTrans(std::ifstream& trans_trace, const MemorySpecificatio
   transTime = 0;
   uint64_t newtranstime;
   uint64_t transAddr;
-  uint64_t transType = 1;
+  int64_t transType = 1;
   trans    TransItem;
 
   if (!transTrace.empty()) {
@@ -156,7 +157,7 @@ void cmdScheduler::getTrans(std::ifstream& trans_trace, const MemorySpecificatio
       if (itemnum == 0) {
         stringstream timestamp(item);
         timestamp >> newtranstime;
-        transTime = transTime + newtranstime;
+        transTime = transTime + static_cast<int64_t>(newtranstime);
       } else if (itemnum == 1) {
         if (item  == "write" || item == "WRITE") {
           transType = WRITE;
@@ -197,18 +198,17 @@ void cmdScheduler::getTrans(std::ifstream& trans_trace, const MemorySpecificatio
 // into commands.txt which will be used for power analysis.
 void cmdScheduler::analyticalScheduling(const MemorySpecification& memSpec)
 {
-  int64_t  Bs               = -1;
   int64_t  transType        = -1;
   int64_t timer          = 0;
   uint64_t  bankGroupPointer = 0;
   uint64_t  bankGroupAddr    = 0;
   bool collisionFound;
   physicalAddr PhysicalAddress;
   bool bankGroupSwitch  = false;
-  std::vector<uint64_t> bankPointer(nbrOfBankGroups, 0);
-  std::vector<int64_t>  bankAccessNum(nBanks, -1);
-  std::vector<bool> ACTSchedule(nBanks, false);
-  int64_t bankAddr    = -1;
+  std::vector<uint64_t> bankPointer(static_cast<size_t>(nbrOfBankGroups), 0);
+  std::vector<int64_t>  bankAccessNum(static_cast<size_t>(nBanks), -1);
+  std::vector<bool> ACTSchedule(static_cast<size_t>(nBanks), false);
+  uint64_t bankAddr   = 0;
   int64_t endTime     = 0;
   int64_t tComing_REF = 0;
 
@@ -219,23 +219,26 @@ void cmdScheduler::analyticalScheduling(const MemorySpecification& memSpec)
   for (uint64_t t = 0; t < transTrace.size(); t++) {
     cmdScheduling.erase(cmdScheduling.begin(), cmdScheduling.end());
 
-    for (int64_t i = 0; i < nBanks; i++) {
-      ACTSchedule[i]   = false;
-      bankAccessNum[i] = -1;
+    for (auto a : ACTSchedule) {
+      a = false;
+    }
+
+    for (auto& b : bankAccessNum) {
+      b = -1;
     }
 
     timingsGet      = false;
     timer           = transTrace[t].timeStamp;
 
     PhysicalAddress = memoryMap(transTrace[t], memSpec);
 
-    for (int64_t i = 0; i < nbrOfBankGroups; i++) {
-      bankPointer[i] = PhysicalAddress.bankAddr; // the bank pointer per group.
+    for (auto& b : bankPointer) {
+      b = PhysicalAddress.bankAddr; // the bank pointer per group.
     }
     bankGroupPointer = PhysicalAddress.bankGroupAddr;
 
-    endTime          = max(transFinish.time, PRE[transFinish.bank].time +
-                           static_cast<int>(memTimingSpec.RP));
+    endTime = max(transFinish.time, PRE[static_cast<size_t>(transFinish.bank)].time +
+                                    static_cast<int>(memTimingSpec.RP));
 
     // Before starting the scheduling for the next transaction, it has to
     // check whether it is necessary for implementing power down.
@@ -252,7 +255,7 @@ void cmdScheduler::analyticalScheduling(const MemorySpecification& memSpec)
                                memTimingSpec.REFI : 0); i++) {
         cmd.bank = 0;
         cmd.name = "REF";
-        cmd.time = max(max(max(transFinish.time, PRE[transFinish.bank].time + memTimingSpec.RP), tREF), startTime);
+        cmd.time = max(max(max(transFinish.time, PRE[static_cast<size_t>(transFinish.bank)].time + memTimingSpec.RP), tREF), startTime);
         if ((power_down == SELF_REFRESH && !Inselfrefresh) || power_down != SELF_REFRESH) {
           cmdScheduling.push_back(cmd);
           startTime = cmd.time + memTimingSpec.RFC;
@@ -264,7 +267,7 @@ void cmdScheduler::analyticalScheduling(const MemorySpecification& memSpec)
       }
     }
     ///////////////Execution Transactions///////////////////
-    Bs        = PhysicalAddress.bankAddr;
+    uint64_t Bs = PhysicalAddress.bankAddr;
     transType = transTrace[t].type;
 
     tRWTP     = getRWTP(transType, memSpec);
@@ -282,9 +285,8 @@ void cmdScheduler::analyticalScheduling(const MemorySpecification& memSpec)
               bankGroupSwitch = true;
             }
             // update to the current bank group address.
-            bankGroupAddr = PhysicalAddress.bankGroupAddr + j;
-            bankAddr      = bankGroupAddr * nBanks / nbrOfBankGroups +
-                            bankPointer[bankGroupAddr];
+            bankGroupAddr = PhysicalAddress.bankGroupAddr + static_cast<uint64_t>(j);
+            bankAddr = bankGroupAddr * static_cast<uint64_t>(nBanks) / nbrOfBankGroups + bankPointer[bankGroupAddr];
           } else   {
             bankAddr = Bs + i;
           }
@@ -314,7 +316,7 @@ void cmdScheduler::analyticalScheduling(const MemorySpecification& memSpec)
                              static_cast<int>(memTimingSpec.TAW));
             }
 
-            if ((i == 0) && (j == 0)) {
+            if (i == 0 && j == 0) {
               cmd.time = max(cmd.time, PreRDWR.time + 1);
               cmd.time = max(cmd.time, timer);
               cmd.time = max(startTime, cmd.time);
@@ -360,7 +362,7 @@ void cmdScheduler::analyticalScheduling(const MemorySpecification& memSpec)
           }
           for (int ACTBank = static_cast<int>(ACT.size() - 1);
                ACTBank >= 0; ACTBank--) {
-            if (ACT[ACTBank].bank == bankAddr) {
+            if (ACT[ACTBank].bank == static_cast<int64_t>(bankAddr)) {
               cmd.time = max(PreRDWR.time + tSwitch_init, ACT.back().time
                              + static_cast<int>(memTimingSpec.RCD));
               break;
@@ -394,7 +396,7 @@ void cmdScheduler::analyticalScheduling(const MemorySpecification& memSpec)
             PRE[bankAddr].name = "PRE";
             for (int ACTBank = static_cast<int>(ACT.size() - 1);
                  ACTBank >= 0; ACTBank--) {
-              if (ACT[ACTBank].bank == bankAddr) {
+              if (ACT[ACTBank].bank == static_cast<int64_t>(bankAddr)) {
                 PRE[bankAddr].time = max(ACT.back().time +
                                          static_cast<int>(memTimingSpec.RAS),
                                          PreRDWR.time + tRWTP);