/
Z80.java
2983 lines (2684 loc) · 83.7 KB
/
Z80.java
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/*
* Copyright (C) 2014-2019 Igor Maznitsa
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
package com.igormaznitsa.z80;
import static java.lang.System.arraycopy;
import java.util.Arrays;
import java.util.Locale;
/**
* Tables and some flag set algorithms were copied and adapted from
* https://github.com/anotherlin/z80emu project, opcode decoding is based on
* http://www.z80.info/decoding.htm
*/
public final class Z80 {
public static final int REG_UNKNOWN = -1;
public static final int REG_A = 0;
public static final int REG_F = 1;
public static final int REG_B = 2;
public static final int REG_C = 3;
public static final int REG_D = 4;
public static final int REG_E = 5;
public static final int REG_H = 6;
public static final int REG_L = 7;
public static final int REG_IX = 8;
public static final int REG_IY = 9;
public static final int REG_SP = 10;
public static final int REG_PC = 11;
public static final int REG_I = 12;
public static final int REG_R = 13;
public static final int REGPAIR_AF = REG_A;
public static final int REGPAIR_BC = REG_B;
public static final int REGPAIR_DE = REG_D;
public static final int REGPAIR_HL = REG_H;
public static final int SIGNAL_IN_nINT = 1;
public static final int SIGNAL_IN_nNMI = 2;
public static final int SIGNAL_IN_nRESET = 4;
public static final int SIGNAL_IN_nWAIT = 8;
public static final int SIGNAL_IN_ALL_INACTIVE =
SIGNAL_IN_nINT | SIGNAL_IN_nNMI | SIGNAL_IN_nRESET | SIGNAL_IN_nWAIT;
public static final int SIGNAL_OUT_nM1 = 1;
public static final int SIGNAL_OUT_nHALT = 2;
public static final int SIGNAL_OUT_ALL_INACTIVE = SIGNAL_OUT_nHALT | SIGNAL_OUT_nM1;
// if the flag is true then it makes green z80bltst.tap v5.0 2022-01-11 by Ped7g
// but in the same time FUSE Z80 tests are red for block commands
private static final boolean FLAG_EXPERIMENTAL_IMPROVE_BLOCK_FLAGS = true;
private static final byte[] FTABLE_SZYX;
private static final byte[] FTABLE_SZYXP;
private static final int FLAG_S_SHIFT = 7;
public static final int FLAG_S = 1 << FLAG_S_SHIFT;
private static final int FLAG_Z_SHIFT = 6;
public static final int FLAG_Z = 1 << FLAG_Z_SHIFT;
private static final int FLAG_SZ = FLAG_S | FLAG_Z;
private static final int FLAG_Y_SHIFT = 5;
public static final int FLAG_Y = 1 << FLAG_Y_SHIFT;
private static final int FLAG_H_SHIFT = 4;
public static final int FLAG_H = 1 << FLAG_H_SHIFT;
private static final int FLAG_X_SHIFT = 3;
public static final int FLAG_X = 1 << FLAG_X_SHIFT;
private static final int FLAG_XY = FLAG_X | FLAG_Y;
private static final int FLAG_SYX = FLAG_S | FLAG_X | FLAG_Y;
private static final int FLAG_PV_SHIFT = 2;
public static final int FLAG_PV = 1 << FLAG_PV_SHIFT;
private static final int FLAG_SZPV = FLAG_S | FLAG_Z | FLAG_PV;
private static final byte[] FTABLE_OVERFLOW = new byte[] {
0, (byte) FLAG_PV, (byte) FLAG_PV, 0
};
private static final int FLAG_N_SHIFT = 1;
public static final int FLAG_N = 1 << FLAG_N_SHIFT;
private static final int FLAG_C_SHIFT = 0;
public static final int FLAG_C = 1 << FLAG_C_SHIFT;
private static final int FLAG_SZC = FLAG_SZ | FLAG_C;
private static final int FLAG_HC = FLAG_H | FLAG_C;
static {
// fill tables SZYX and SZYXP
FTABLE_SZYX = new byte[0x100];
FTABLE_SZYXP = new byte[0x100];
for (int i = 0; i < 256; i++) {
final int szyx = i & (FLAG_X | FLAG_Y | FLAG_S);
FTABLE_SZYX[i] = (byte) szyx;
int j = i;
int parity = 0;
for (int k = 0; k < 8; k++) {
parity ^= (j & 1);
j >>>= 1;
}
FTABLE_SZYXP[i] = (byte) (szyx | (parity != 0 ? 0 : FLAG_PV));
}
FTABLE_SZYX[0] |= FLAG_Z;
FTABLE_SZYXP[0] |= FLAG_Z;
}
private final Z80CPUBus bus;
private final byte[] regSet = new byte[8];
private final byte[] altRegSet = new byte[8];
private int memptr;
private boolean iff1;
private boolean iff2;
private int im;
private int regIX;
private int regIY;
private int regSP;
private int regPC;
private int regI;
private int regR;
private int tiStates;
private int lastM1InstructionByte = -1;
private int lastInstructionByte = -1;
private int cbDisplacementByte = -1;
private int prefix;
private int outSignals = 0xFFFFFFFF;
private int prevInSignals = 0xFFFFFFFF;
private boolean stepAllowsInterruption;
private boolean nmiTrigger;
private int resetCycle = 0;
private int internalRegQ;
private int internalRegLastQ;
public Z80(final Z80CPUBus bus) {
if (bus == null) {
throw new NullPointerException("The CPU BUS must not be null");
}
this.bus = bus;
_reset(0);
_reset(1);
_reset(2);
this.tiStates = 0;
}
/**
* Make full copy of state of the source CPU. NB! pointer to bus will be
* copied!
*
* @param cpu source CPU which state should be copied, must not be null
*/
public Z80(final Z80 cpu) {
this.prefix = cpu.prefix;
this.internalRegQ = cpu.internalRegQ;
this.internalRegLastQ = cpu.internalRegLastQ;
this.resetCycle = cpu.resetCycle;
this.iff1 = cpu.iff1;
this.iff2 = cpu.iff2;
this.im = cpu.im;
this.regI = cpu.regI;
this.regIX = cpu.regIX;
this.regIY = cpu.regIY;
this.regPC = cpu.regPC;
this.regR = cpu.regR;
this.regSP = cpu.regSP;
arraycopy(cpu.regSet, 0, this.regSet, 0, cpu.regSet.length);
arraycopy(cpu.altRegSet, 0, this.altRegSet, 0, cpu.altRegSet.length);
this.lastM1InstructionByte = cpu.lastM1InstructionByte;
this.lastInstructionByte = cpu.lastInstructionByte;
this.tiStates = cpu.tiStates;
this.cbDisplacementByte = cpu.cbDisplacementByte;
this.outSignals = cpu.outSignals;
this.prevInSignals = cpu.prevInSignals;
this.stepAllowsInterruption = cpu.stepAllowsInterruption;
this.nmiTrigger = cpu.nmiTrigger;
this.bus = cpu.bus;
}
private static int extractX(final int cmndByte) {
return cmndByte >>> 6;
}
private static int extractY(final int cmndByte) {
return (cmndByte >>> 3) & 7;
}
private static int extractZ(final int cmndByte) {
return cmndByte & 7;
}
private static int extractP(final int cmndByte) {
return (cmndByte >>> 4) & 3;
}
private static int extractQ(final int cmndByte) {
return (cmndByte >>> 3) & 1;
}
/**
* Parse string with id of registers and prepare bit vector for it.
* main set: <b>A,F,B,C,D,E,H,L,1(F without C)</b>
* alt.set: <b>sa,f,b,c,d,e,h,l,0(F' without C)</b>
* special: <b>T(use PTR reg values from main CPU)</b>
* index: <b>X(high byte IX), x(lower byte IX),Y(high byte IY), y(lower byte IY)</b>
* spec: <b>P(PC),S(high byte SP),s(lower byte SP)</b>
*
* @param regs string where each char means register or its part
* @return formed bit vector
* @see #alignRegisterValuesWith(Z80, int)
* @since 2.0.1
*/
public static int parseAndPackRegAlignValue(final String regs) {
final String allowedPositions = "AFBCDEHLXxYy10PSsafbcdehl";
final String trimmed = regs.trim();
int result = 0;
for (final char c : trimmed.toCharArray()) {
if (c == 'T') {
continue;
}
final int index = allowedPositions.indexOf(c);
if (index < 0) {
throw new IllegalArgumentException(
"Unexpected char: " + c + " expected one from '" + allowedPositions + "'");
} else {
result |= 1 << index;
}
}
return result;
}
private static boolean isLoHiFront(final int oldValue, final int newValue, final int mask) {
final int xored = oldValue ^ newValue;
return (xored & mask) == mask && (newValue & mask) == mask;
}
private static boolean isHiLoFront(final int oldValue, final int newValue, final int mask) {
final int xored = oldValue ^ newValue;
return (xored & mask) == mask && (oldValue & mask) == mask;
}
public Z80 fillByState(final Z80 sourceCpu) {
this.prefix = sourceCpu.prefix;
this.resetCycle = sourceCpu.resetCycle;
this.iff1 = sourceCpu.iff1;
this.iff2 = sourceCpu.iff2;
this.im = sourceCpu.im;
this.regI = sourceCpu.regI;
this.regIX = sourceCpu.regIX;
this.regIY = sourceCpu.regIY;
this.regPC = sourceCpu.regPC;
this.regR = sourceCpu.regR;
this.regSP = sourceCpu.regSP;
arraycopy(sourceCpu.regSet, 0, this.regSet, 0, sourceCpu.regSet.length);
arraycopy(sourceCpu.altRegSet, 0, this.altRegSet, 0, sourceCpu.altRegSet.length);
this.lastM1InstructionByte = sourceCpu.lastM1InstructionByte;
this.lastInstructionByte = sourceCpu.lastInstructionByte;
this.tiStates = sourceCpu.tiStates;
this.cbDisplacementByte = sourceCpu.cbDisplacementByte;
this.outSignals = sourceCpu.outSignals;
this.prevInSignals = sourceCpu.prevInSignals;
this.stepAllowsInterruption = sourceCpu.stepAllowsInterruption;
this.nmiTrigger = sourceCpu.nmiTrigger;
return this;
}
public int getMemPtr() {
return this.memptr;
}
public void setMemPtr(final int value) {
this.memptr = value & 0xFFFF;
}
public int getIM() {
return this.im;
}
public void setIM(final int im) {
this.im = im & 3;
}
public boolean isIFF1() {
return this.iff1;
}
public boolean isIFF2() {
return this.iff2;
}
public int getPrefixInProcessing() {
return this.prefix;
}
public int getPrevInSignals() {
return this.prevInSignals;
}
public int getPC() {
return this.regPC;
}
public void setIFF(final boolean iff1, final boolean iff2) {
this.iff1 = iff1;
this.iff2 = iff2;
}
public void setRegisterPair(final int regPair, final int value) {
this.setRegisterPair(regPair, value, false);
}
public void setRegisterPair(final int regPair, final int value, final boolean alt) {
if (alt) {
this.altRegSet[regPair] = (byte) (value >>> 8);
this.altRegSet[regPair + 1] = (byte) value;
} else {
this.regSet[regPair] = (byte) (value >>> 8);
this.regSet[regPair + 1] = (byte) value;
}
}
public int getRegisterPair(final int regPair) {
return this.getRegisterPair(regPair, false);
}
public int getRegisterPair(final int regPair, final boolean alt) {
final byte[] regset = alt ? altRegSet : regSet;
return ((regset[regPair] & 0xFF) << 8) | (regset[regPair + 1] & 0xFF);
}
public void setRegister(final int reg, final int value) {
this.setRegister(reg, value, false);
}
public void setRegister(final int reg, final int value, final boolean alt) {
switch (reg) {
case REG_IX:
this.regIX = value & 0xFFFF;
break;
case REG_IY:
this.regIY = value & 0xFFFF;
break;
case REG_PC:
this.regPC = value & 0xFFFF;
break;
case REG_SP:
this.regSP = value & 0xFFFF;
break;
case REG_I:
this.regI = value & 0xFF;
break;
case REG_R:
this.regR = value & 0xFF;
break;
default: {
if (alt) {
this.altRegSet[reg] = (byte) value;
} else {
this.regSet[reg] = (byte) value;
}
}
}
}
public int getRegister(final int reg) {
return this.getRegister(reg, false);
}
public int getRegister(final int reg, final boolean alt) {
final byte[] regset = alt ? altRegSet : regSet;
final int result;
switch (reg) {
case REG_IX:
result = this.regIX;
break;
case REG_IY:
result = this.regIY;
break;
case REG_PC:
result = this.regPC;
break;
case REG_SP:
result = this.regSP;
break;
case REG_I:
result = this.regI;
break;
case REG_R:
result = this.regR;
break;
default: {
result = regset[reg] & 0xFF;
}
}
return result;
}
public int getState() {
return this.outSignals;
}
public Z80CPUBus getBus() {
return this.bus;
}
public void setTstates(final int tiStates) {
this.tiStates = Math.max(0, tiStates);
}
public void addTstates(final int tiStates) {
this.tiStates += tiStates;
}
public int getStepTstates() {
return this.tiStates;
}
private void _reset(final int cycle) {
switch (cycle % 3) {
case 0: {
this.internalRegQ = 0;
this.internalRegLastQ = 0;
this.iff1 = false;
this.iff2 = false;
this.regI = 0;
this.regR = 0;
}
break;
case 1: {
this.regPC = 0;
this.regSP = 0;
}
break;
case 2: {
// set AF and AF' by 0xFFFF
this.regSet[REG_A] = (byte) 0xFF;
this.regSet[REG_F] = (byte) 0xFF;
this.altRegSet[REG_A] = (byte) 0xFF;
this.altRegSet[REG_F] = (byte) 0xFF;
}
break;
default: {
throw new Error("Unexpected call");
}
}
this.im = 0;
this.cbDisplacementByte = -1;
this.stepAllowsInterruption = false;
this.prefix = 0;
this.outSignals = SIGNAL_OUT_ALL_INACTIVE;
this.tiStates += 3;
}
private void _resetHalt() {
if ((this.outSignals & SIGNAL_OUT_nHALT) == 0) {
this.outSignals |= SIGNAL_OUT_nHALT;
this.regPC = (this.regPC + 1) & 0xFFFF;
}
}
private void _int(final int ctx) {
_resetHalt();
this.iff1 = false;
this.iff2 = false;
this.bus.onInterrupt(this, ctx, false);
switch (this.im) {
case 0: {
_step(ctx, this.bus.onCPURequestDataLines(this, ctx) & 0xFF, true);
}
break;
case 1: {
_step(ctx, 0xFF, true);
}
break;
case 2: {
final int vector = ((_readSpecRegValue(ctx, REG_I, this.regI) & 0xFF) << 8)
| (this.bus.onCPURequestDataLines(this, ctx) & 0xFF);
final int address = _readmem16(ctx, vector);
this.setMemPtr(address);
_call(ctx, address);
this.tiStates++;
}
break;
default:
throw new Error("Unexpected IM mode [" + this.im + ']');
}
this.tiStates += 6;
}
private void _incR() {
final int r = this.getRegister(REG_R);
this.setRegister(REG_R, (r & 0x80) | ((r + 1) & 0x7F));
}
public int getSP() {
return this.regSP;
}
private void _nmi(final int ctx) {
this.bus.onInterrupt(this, ctx, true);
_resetHalt();
this.iff1 = false;
this.nmiTrigger = false;
_call(ctx, 0x66);
this.tiStates += 5;
}
private void _writemem8(final int ctx, final int address, final byte value) {
this.bus.writeMemory(this, ctx, address & 0xFFFF, value);
this.tiStates += 3;
}
private int _readNextPcAddressedWord(final int ctx) {
return readInstrOrPrefix(ctx, false) | (readInstrOrPrefix(ctx, false) << 8);
}
private void _writemem16(final int ctx, final int address, final int value) {
this._writemem8(ctx, address, (byte) value);
this._writemem8(ctx, address + 1, (byte) (value >> 8));
}
private void _call(final int ctx, final int address) {
final int sp = (_readPtr(ctx, REG_SP, this.regSP) - 2) & 0xFFFF;
_writemem8(ctx, sp, (byte) this.regPC);
_writemem8(ctx, sp + 1, (byte) (this.regPC >> 8));
this.regPC = address;
this.regSP = sp;
}
private int _readSpecRegValue(final int ctx, final int reg, final int origValue) {
return this.bus.readSpecRegValue(this, ctx, reg, origValue);
}
private int _readSpecRegPairValue(final int ctx, final int regPair, final int origValue) {
return this.bus.readSpecRegPairValue(this, ctx, regPair, origValue);
}
private int _portAddrFromReg(final int ctx, final int reg, final int origValue) {
return this.bus.readRegPortAddr(this, ctx, reg, origValue);
}
private int _readport(final int ctx, final int port) {
this.tiStates += 4;
return this.bus.readPort(this, ctx, port & 0xFFFF) & 0xFF;
}
private void _writeport(final int ctx, final int port, final int value) {
this.bus.writePort(this, ctx, port & 0xFFFF, (byte) value);
this.tiStates += 4;
}
private int _readmem8(final int ctx, final int address) {
this.tiStates += 3;
return this.bus.readMemory(this, ctx, address & 0xFFFF, false, false) & 0xFF;
}
private int _readmem8withM1(final int ctx, final int address) {
this.tiStates += 3;
return this.bus.readMemory(this, ctx, address & 0xFFFF, true, false) & 0xFF;
}
private int _readmem16(final int ctx, final int address) {
return _readmem8(ctx, address) | (_readmem8(ctx, address + 1) << 8);
}
private int _read_ixiy_d(final int ctx) {
if (this.cbDisplacementByte < 0) {
return readInstrOrPrefix(ctx, false);
} else {
this.tiStates -= 5;
return this.cbDisplacementByte;
}
}
private int readInstrOrPrefix(final int ctx, final boolean m1) {
final boolean nonDisplacementByte = (this.prefix & 0xFF00) == 0;
final int pc = this.regPC;
this.regPC = (this.regPC + 1) & 0xFFFF;
this.outSignals =
(m1 ? this.outSignals & (~SIGNAL_OUT_nM1) : this.outSignals | SIGNAL_OUT_nM1) & 0xFF;
final int result = this.bus.readMemory(this, ctx, pc, m1 && nonDisplacementByte, true) & 0xFF;
this.outSignals = this.outSignals | SIGNAL_OUT_nM1;
this.tiStates += m1 ? 4 : 3;
if (m1) {
this.lastM1InstructionByte = result;
if (nonDisplacementByte) {
_incR();
}
}
this.lastInstructionByte = result;
return result;
}
private int normalizedPrefix() {
return (this.prefix & 0xFF) == 0xCB ? this.prefix >>> 8 : this.prefix;
}
private boolean checkCondition(final int cc) {
final boolean result;
final int flags = this.regSet[REG_F];
switch (cc) {
case 0: // NZ
result = (flags & FLAG_Z) == 0;
break;
case 1: // Z
result = (flags & FLAG_Z) != 0;
break;
case 2: // NC
result = (flags & FLAG_C) == 0;
break;
case 3: // C
result = (flags & FLAG_C) != 0;
break;
case 4: // PO
result = (flags & FLAG_PV) == 0;
break;
case 5: // PE
result = (flags & FLAG_PV) != 0;
break;
case 6: // P
result = (flags & FLAG_S) == 0;
break;
case 7: // M
result = (flags & FLAG_S) != 0;
break;
default:
throw new Error("Unexpected condition");
}
return result;
}
private int _readPtr(final int ctx, final int reg, final int origValue) {
return this.bus.readPtr(this, ctx, reg, origValue);
}
/**
* Set value of some registers from source CPU.
*
* @param src source CPU must not be null
* @param packedRegisterFlags bit flags describe needed registers
* @return the instance
* @see #parseAndPackRegAlignValue(String)
* @since 2.0.1
*/
public Z80 alignRegisterValuesWith(final Z80 src, int packedRegisterFlags) {
this.cbDisplacementByte = src.cbDisplacementByte;
this.prefix = src.prefix;
this.iff1 = src.iff1;
this.iff2 = src.iff2;
this.im = src.im;
this.regI = src.regI;
this.regR = src.regR;
this.lastInstructionByte = src.lastInstructionByte;
this.lastM1InstructionByte = src.lastM1InstructionByte;
this.prevInSignals = src.prevInSignals;
this.stepAllowsInterruption = src.stepAllowsInterruption;
this.nmiTrigger = src.nmiTrigger;
if (packedRegisterFlags == 0) {
this.regPC = src.regPC;
this.regSP = src.regSP;
} else {
//"AFBCDEHL XxYy10PSs afbcdehl"
int pos = 0;
while (packedRegisterFlags != 0) {
if ((packedRegisterFlags & 1) != 0) {
if (pos < 8) {
this.regSet[pos] = src.regSet[pos];
} else if (pos < 17) {
switch (pos - 8) {
case 0:
this.regIX = (this.regIX & 0xFF) | (src.regIX & 0xFF00);
break;
case 1:
this.regIX = (this.regIX & 0xFF00) | (src.regIX & 0xFF);
break;
case 2:
this.regIY = (this.regIY & 0xFF) | (src.regIY & 0xFF00);
break;
case 3:
this.regIY = (this.regIY & 0xFF00) | (src.regIY & 0xFF);
break;
case 4:
this.regSet[REG_F] =
(byte) ((this.regSet[REG_F] & FLAG_C) | (src.regSet[REG_F] & ~FLAG_C));
break;
case 5:
this.altRegSet[REG_F] =
(byte) ((this.altRegSet[REG_F] & FLAG_C) | (src.altRegSet[REG_F] & ~FLAG_C));
break;
case 6:
this.regPC = src.regPC;
break;
case 7:
this.regSP = (this.regSP & 0xFF) | (src.regSP & 0xFF00);
break;
case 8:
this.regSP = (this.regSP & 0xFF00) | (src.regSP & 0xFF);
break;
default:
throw new Error("Unexpected state");
}
} else {
final int reg = pos - 17;
this.altRegSet[reg] = src.altRegSet[reg];
}
}
packedRegisterFlags >>>= 1;
pos++;
}
}
return this;
}
private int readReg8(final int ctx, final int r) {
switch (r) {
case 0:
return getRegister(REG_B);
case 1:
return getRegister(REG_C);
case 2:
return getRegister(REG_D);
case 3:
return getRegister(REG_E);
case 4: { // H
switch (normalizedPrefix()) {
case 0x00:
return getRegister(REG_H);
case 0xDD:
return (this.regIX >> 8) & 0xFF;
case 0xFD:
return (this.regIY >> 8) & 0xFF;
}
}
break;
case 5: { // L
switch (normalizedPrefix()) {
case 0x00:
return getRegister(REG_L);
case 0xDD:
return this.regIX & 0xFF;
case 0xFD:
return this.regIY & 0xFF;
}
}
break;
case 6: { // (HL)
switch (normalizedPrefix()) {
case 0x00: {
final int address = _readPtr(ctx, REGPAIR_HL, this.getRegisterPair(REGPAIR_HL));
return _readmem8(ctx, address);
}
case 0xDD: {
this.tiStates += 5;
final int address = _readPtr(ctx, REG_IX, this.regIX) + (byte) _read_ixiy_d(ctx);
this.setMemPtr(address);
return _readmem8(ctx, address);
}
case 0xFD: {
this.tiStates += 5;
final int address = _readPtr(ctx, REG_IY, this.regIY) + (byte) _read_ixiy_d(ctx);
this.setMemPtr(address);
return _readmem8(ctx, address);
}
}
}
break;
case 7:
return getRegister(REG_A);
}
throw new Error("Unexpected prefix or R index [" + this.prefix + ':' + r + ']');
}
private void writeReg16(final int p, final int value) {
switch (p) {
case 0:
setRegisterPair(REGPAIR_BC, value);
return;
case 1:
setRegisterPair(REGPAIR_DE, value);
return;
case 2: {
switch (normalizedPrefix()) {
case 0x00:
setRegisterPair(REGPAIR_HL, value);
return;
case 0xDD:
setRegister(REG_IX, value);
return;
case 0xFD:
setRegister(REG_IY, value);
return;
}
}
break;
case 3:
setRegister(REG_SP, value);
return;
}
throw new Error("unexpected P index or prefix [" + this.prefix + ':' + p + ']');
}
private void writeReg16_2(final int p, final int value) {
switch (p) {
case 0:
setRegisterPair(REGPAIR_BC, value);
return;
case 1:
setRegisterPair(REGPAIR_DE, value);
return;
case 2: {
switch (normalizedPrefix()) {
case 0x00:
setRegisterPair(REGPAIR_HL, value);
return;
case 0xDD:
setRegister(REG_IX, value);
return;
case 0xFD:
setRegister(REG_IY, value);
return;
}
}
break;
case 3:
setRegisterPair(REGPAIR_AF, value);
return;
}
throw new Error("unexpected P index or prefix [" + this.prefix + ':' + p + ']');
}
private int readHlPtr(final int ctx) {
switch (normalizedPrefix()) {
case 0x00:
return _readPtr(ctx, REGPAIR_HL, getRegisterPair(REGPAIR_HL));
case 0xDD:
return _readPtr(ctx, REG_IX, getRegister(REG_IX));
case 0xFD:
return _readPtr(ctx, REG_IY, getRegister(REG_IY));
}
throw new Error("Unexpected prefix:" + this.prefix);
}
private int readReg16(final int p) {
switch (p) {
case 0:
return getRegisterPair(REGPAIR_BC);
case 1:
return getRegisterPair(REGPAIR_DE);
case 2: {
switch (normalizedPrefix()) {
case 0x00:
return getRegisterPair(REGPAIR_HL);
case 0xDD:
return getRegister(REG_IX);
case 0xFD:
return getRegister(REG_IY);
}
}
break;
case 3:
return this.getSP();
}
throw new Error("Unexpected P index or prefix [" + this.prefix + ':' + p + ']');
}
private int readReg16_2(final int p) {
switch (p) {
case 0:
return getRegisterPair(REGPAIR_BC);
case 1:
return getRegisterPair(REGPAIR_DE);
case 2: {
switch (normalizedPrefix()) {
case 0x00:
return getRegisterPair(REGPAIR_HL);
case 0xDD:
return getRegister(REG_IX);
case 0xFD:
return getRegister(REG_IY);
}
}
break;
case 3:
return getRegisterPair(REGPAIR_AF);
}
throw new Error("Unexpected P index or prefix [" + this.prefix + ':' + p + ']');
}
private void writeReg8(final int ctx, final int r, final int value) {
switch (r) {
case 0:
setRegister(REG_B, value);
return;
case 1:
setRegister(REG_C, value);
return;
case 2:
setRegister(REG_D, value);
return;
case 3:
setRegister(REG_E, value);
return;
case 4:
if (this.cbDisplacementByte < 0) {
switch (normalizedPrefix()) {
case 0x00:
setRegister(REG_H, value);
break;
case 0xDD: {
this.regIX = (this.regIX & 0xFF) | ((value & 0xFF) << 8);
}
break;
case 0xFD: {
this.regIY = (this.regIY & 0xFF) | ((value & 0xFF) << 8);
}
break;
}
} else {
setRegister(REG_H, value);
}
return;
case 5:
if (this.cbDisplacementByte < 0) {
switch (normalizedPrefix()) {
case 0x00:
setRegister(REG_L, value);
break;
case 0xDD: {
this.regIX = (this.regIX & 0xFF00) | (value & 0xFF);
}
break;
case 0xFD: {
this.regIY = (this.regIY & 0xFF00) | (value & 0xFF);
}
break;
}
} else {
setRegister(REG_L, value);
}
return;
case 6: { // (HL)
switch (normalizedPrefix()) {
case 0x00: {
final int address = _readPtr(ctx, REGPAIR_HL, this.getRegisterPair(REGPAIR_HL));
_writemem8(ctx, address,
(byte) value);
return;
}
case 0xDD: {
final int address = _readPtr(ctx, REG_IX, this.regIX) + (byte) value;
_writemem8(ctx, address, (byte) readInstrOrPrefix(ctx, false));
this.setMemPtr(address);
this.tiStates += 2;
return;
}
case 0xFD: {
final int address = _readPtr(ctx, REG_IY, this.regIY) + (byte) value;
_writemem8(ctx, address, (byte) readInstrOrPrefix(ctx, false));
this.setMemPtr(address);
this.tiStates += 2;
return;
}
}
}
break;
case 7:
setRegister(REG_A, value);
return;
}
throw new Error("unexpected P index or prefix [" + this.prefix + ':' + r + ']');
}
public int getLastM1InstructionByte() {
return this.lastM1InstructionByte;
}
public int getLastInstructionByte() {
return this.lastInstructionByte;
}