/
0001-drm-rcar-du-Add-DU-CMM-support.patch
2805 lines (2755 loc) · 78.2 KB
/
0001-drm-rcar-du-Add-DU-CMM-support.patch
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From 89a6e56072d2970741413e6c118f7062a72a0979 Mon Sep 17 00:00:00 2001
From: Sojiro Kusunoki <sojiro.kusunoki.zj@ps.hitachi-solutions.com>
Date: Tue, 21 May 2019 09:23:49 +0900
Subject: [PATCH] drm: rcar-du: Add DU CMM support
Signed-off-by: Sojiro Kusunoki <sojiro.kusunoki.zj@ps.hitachi-solutions.com>
---
.../boot/dts/renesas/r8a7795-es1-salvator-x.dts | 5 +
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 5 +
.../arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 5 +
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 25 +-
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 4 +
.../boot/dts/renesas/r8a7796-salvator-xs-2x4g.dts | 4 +
.../arm64/boot/dts/renesas/r8a7796-salvator-xs.dts | 4 +
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 22 +-
.../arm64/boot/dts/renesas/r8a77965-salvator-x.dts | 4 +
.../boot/dts/renesas/r8a77965-salvator-xs.dts | 4 +
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 22 +-
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 6 +-
.../arm64/boot/dts/renesas/r8a77990-es10-ebisu.dts | 6 +-
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 17 +-
drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 +
drivers/clk/renesas/r8a7796-cpg-mssr.c | 3 +
drivers/clk/renesas/r8a77965-cpg-mssr.c | 3 +
drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 +
drivers/gpu/drm/rcar-du/Makefile | 2 +
drivers/gpu/drm/rcar-du/rcar_du_cmm.c | 1757 ++++++++++++++++++++
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 26 +
drivers/gpu/drm/rcar-du/rcar_du_crtc.h | 31 +
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 53 +-
drivers/gpu/drm/rcar-du/rcar_du_drv.h | 7 +
drivers/gpu/drm/rcar-du/rcar_du_group.c | 5 +
drivers/gpu/drm/rcar-du/rcar_du_regs.h | 90 +
drivers/gpu/drm/rcar-du/rcar_lvds.c | 13 +
include/uapi/drm/rcar_du_drm.h | 131 +-
28 files changed, 2231 insertions(+), 29 deletions(-)
create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_cmm.c
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
index 5c3935e..c6eb0c9 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
@@ -92,11 +92,16 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 709>,
+ <&cpg CPG_MOD 708>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3",
+ "cmm.0", "cmm.1", "cmm.2", "cmm.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 6928afb..dacdb98 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -92,11 +92,16 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 709>,
+ <&cpg CPG_MOD 708>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3",
+ "cmm.0", "cmm.1", "cmm.2", "cmm.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index 498f788..b96ccf4 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -92,11 +92,16 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 709>,
+ <&cpg CPG_MOD 708>,
<&versaclock6 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2", "du.3",
+ "cmm.0", "cmm.1", "cmm.2", "cmm.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 2cf1ae6..1be004f 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -3438,7 +3438,12 @@
du: display@feb00000 {
compatible = "renesas,du-r8a7795";
- reg = <0 0xfeb00000 0 0x80000>;
+ reg = <0 0xfeb00000 0 0x80000>,
+ <0 0xfea40000 0 0x00001000>,
+ <0 0xfea50000 0 0x00001000>,
+ <0 0xfea60000 0 0x00001000>,
+ <0 0xfea70000 0 0x00001000>;
+ reg-names = "du", "cmm.0", "cmm.1", "cmm.2", "cmm.3";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@@ -3446,13 +3451,23 @@
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
- <&cpg CPG_MOD 721>;
- clock-names = "du.0", "du.1", "du.2", "du.3";
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 709>,
+ <&cpg CPG_MOD 708>;
+ clock-names = "du.0", "du.1", "du.2", "du.3",
+ "cmm.0", "cmm.1", "cmm.2", "cmm.3";
resets = <&cpg 724>,
<&cpg 724>,
<&cpg 722>,
- <&cpg 722>;
- reset-names = "du.0", "du.1", "du.2", "du.3";
+ <&cpg 722>,
+ <&cpg 711>,
+ <&cpg 710>,
+ <&cpg 709>,
+ <&cpg 708>;
+ reset-names = "du.0", "du.1", "du.2", "du.3",
+ "cmm.0", "cmm.1", "cmm.2", "cmm.3";
vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index cf92aa3..8530489 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -81,10 +81,14 @@
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 709>,
<&versaclock5 1>,
<&x21_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2",
+ "cmm.0", "cmm.1", "cmm.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs-2x4g.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs-2x4g.dts
index 664dc92..1cd7873 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs-2x4g.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs-2x4g.dts
@@ -89,10 +89,14 @@
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 709>,
<&versaclock6 1>,
<&x21_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2",
+ "cmm.0", "cmm.1", "cmm.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
index 7d39dc9..f098f6e 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
@@ -81,10 +81,14 @@
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 709>,
<&versaclock6 1>,
<&x21_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2",
+ "cmm.0", "cmm.1", "cmm.2",
"dclkin.0", "dclkin.1", "dclkin.2";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 4de0920..d214860 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -3118,18 +3118,30 @@
du: display@feb00000 {
compatible = "renesas,du-r8a7796";
- reg = <0 0xfeb00000 0 0x70000>;
+ reg = <0 0xfeb00000 0 0x70000>,
+ <0 0xfea40000 0 0x00001000>,
+ <0 0xfea50000 0 0x00001000>,
+ <0 0xfea60000 0 0x00001000>;
+ reg-names = "du", "cmm.0", "cmm.1", "cmm.2";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 722>;
- clock-names = "du.0", "du.1", "du.2";
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 709>;
+ clock-names = "du.0", "du.1", "du.2",
+ "cmm.0", "cmm.1", "cmm.2";
resets = <&cpg 724>,
<&cpg 724>,
- <&cpg 722>;
- reset-names = "du.0", "du.1", "du.2";
+ <&cpg 722>,
+ <&cpg 711>,
+ <&cpg 710>,
+ <&cpg 709>;
+ reset-names = "du.0", "du.1", "du.2",
+ "cmm.0", "cmm.1", "cmm.2";
status = "disabled";
vsps = <&vspd0 &vspd1 &vspd2>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
index d9fb0df..9e2be07 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
@@ -76,10 +76,14 @@
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 708>,
<&versaclock5 1>,
<&x21_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
+ "cmm.0", "cmm.1", "cmm.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
index d645612..1d0fd40 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -76,10 +76,14 @@
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 708>,
<&versaclock6 1>,
<&x21_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.3",
+ "cmm.0", "cmm.1", "cmm.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 74f3369..0ae843a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -2356,18 +2356,30 @@
du: display@feb00000 {
compatible = "renesas,du-r8a77965";
- reg = <0 0xfeb00000 0 0x80000>;
+ reg = <0 0xfeb00000 0 0x80000>,
+ <0 0xfea40000 0 0x00001000>,
+ <0 0xfea50000 0 0x00001000>,
+ <0 0xfea70000 0 0x00001000>;
+ reg-names = "du", "cmm.0", "cmm.1", "cmm.3";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
- <&cpg CPG_MOD 721>;
- clock-names = "du.0", "du.1", "du.3";
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>,
+ <&cpg CPG_MOD 708>;
+ clock-names = "du.0", "du.1", "du.3",
+ "cmm.0", "cmm.1", "cmm.3";
resets = <&cpg 724>,
<&cpg 724>,
- <&cpg 722>;
- reset-names = "du.0", "du.1", "du.3";
+ <&cpg 722>,
+ <&cpg 711>,
+ <&cpg 710>,
+ <&cpg 708>;
+ reset-names = "du.0", "du.1", "du.3",
+ "cmm.0", "cmm.1", "cmm.3";
status = "disabled";
vsps = <&vspd0 0 &vspd1 0 &vspd0 1>;
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index f52f0f2..5ff707e 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -390,8 +390,10 @@
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
- <&x13_clk>;
- clock-names = "du.0", "du.1", "dclkin.0";
+ <&x13_clk>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>;
+ clock-names = "du.0", "du.1", "dclkin.0", "cmm.0", "cmm.1";
};
&ehci0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-es10-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-es10-ebisu.dts
index f860fcb..5012789 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-es10-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-es10-ebisu.dts
@@ -390,8 +390,10 @@
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
- <&x13_clk>;
- clock-names = "du.0", "du.1", "dclkin.0";
+ <&x13_clk>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>;
+ clock-names = "du.0", "du.1", "dclkin.0", "cmm.0", "cmm.1";
};
&ehci0 {
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 7cfa102..73e30c5 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1826,15 +1826,22 @@
du: display@feb00000 {
compatible = "renesas,du-r8a77990";
- reg = <0 0xfeb00000 0 0x40000>;
+ reg = <0 0xfeb00000 0 0x40000>,
+ <0 0xfea40000 0 0x00001000>,
+ <0 0xfea50000 0 0x00001000>;
+ reg-names = "du", "cmm.0", "cmm.1";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
- <&cpg CPG_MOD 723>;
- clock-names = "du.0", "du.1";
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 711>,
+ <&cpg CPG_MOD 710>;
+ clock-names = "du.0", "du.1", "cmm.0", "cmm.1";
resets = <&cpg 724>,
- <&cpg 724>;
- reset-names = "du.0", "du.1";
+ <&cpg 724>,
+ <&cpg 711>,
+ <&cpg 710>;
+ reset-names = "du.0", "du.1", "cmm.0", "cmm.1";
vsps = <&vspd0 0 &vspd1 0>;
status = "disabled";
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 5b09453..869030c 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -207,6 +207,10 @@ enum clk_ids {
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
+ DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1),
+ DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
+ DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
+ DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index ad1e3f8..d70f2f2 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -187,6 +187,9 @@ enum clk_ids {
DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2),
+ DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1),
+ DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1),
+ DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1),
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index b3b637f..5238069 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -182,6 +182,9 @@ enum clk_ids {
DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),
+ DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1),
+ DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1),
+ DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1),
DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index a5d0d00..4129d57 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -186,6 +186,8 @@ enum clk_ids {
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2),
+ DEF_MOD("cmm1", 710, R8A77990_CLK_S1D1),
+ DEF_MOD("cmm0", 711, R8A77990_CLK_S1D1),
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 9bd2fe3..bcc3789 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -6,6 +6,8 @@ rcar-du-drm-y := rcar_du_crtc.o \
rcar_du_kms.o \
rcar_du_plane.o
+rcar-du-drm-y += rcar_du_cmm.o
+
rcar-du-drm-$(CONFIG_DRM_RCAR_VSP) += rcar_du_vsp.o
obj-$(CONFIG_DRM_RCAR_DU) += rcar-du-drm.o
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_cmm.c b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c
new file mode 100644
index 0000000..49a929e
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rcar_du_cmm.c
@@ -0,0 +1,1757 @@
+/*************************************************************************/ /*
+ * DU CMM
+ *
+ * Copyright (C) 2018 Renesas Electronics Corporation
+ *
+ * License Dual MIT/GPLv2
+ *
+ * The contents of this file are subject to the MIT license as set out below.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Alternatively, the contents of this file may be used under the terms of
+ * the GNU General Public License Version 2 ("GPL") in which case the provisions
+ * of GPL are applicable instead of those above.
+ *
+ * If you wish to allow use of your version of this file only under the terms of
+ * GPL, and not to allow others to use your version of this file under the terms
+ * of the MIT license, indicate your decision by deleting the provisions above
+ * and replace them with the notice and other provisions required by GPL as set
+ * out in the file called "GPL-COPYING" included in this distribution. If you do
+ * not delete the provisions above, a recipient may use your version of this
+ * file under the terms of either the MIT license or GPL.
+ *
+ * This License is also included in this distribution in the file called
+ * "MIT-COPYING".
+ *
+ * EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
+ * PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS
+ * OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
+ * IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ * GPLv2:
+ * If you wish to use this file under the terms of GPL, following terms are
+ * effective.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */ /*************************************************************************/
+
+#include <linux/workqueue.h>
+#include <linux/syscalls.h>
+#include <linux/reset.h>
+#include <linux/sys_soc.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/rcar_du_drm.h>
+
+#include "rcar_du_crtc.h"
+#include "rcar_du_drv.h"
+#include "rcar_du_kms.h"
+#include "rcar_du_plane.h"
+#include "rcar_du_regs.h"
+#include <linux/clk.h>
+
+/* #define DEBUG_PROCE_TIME 1 */
+
+#define CMM_CLU_SAMPLES 17
+#define CMM_LUT_NUM 256
+#define CMM_CLU_NUM (CMM_CLU_SAMPLES * CMM_CLU_SAMPLES * CMM_CLU_SAMPLES)
+#define CMM_HGO_NUM 64
+
+enum {
+ QUE_STAT_PENDING,
+ QUE_STAT_ACTIVE,
+ QUE_STAT_DONE,
+};
+
+static const struct soc_device_attribute rcar_du_cmm_r8a7795_es1[] = {
+ { .soc_id = "r8a7795", .revision = "ES1.*" },
+ { /* sentinel */ }
+};
+
+struct rcar_du_cmm;
+struct rcar_du_cmm_file_priv;
+
+struct rcar_du_cmm_pending_event {
+ struct list_head link;
+ struct list_head fpriv_link;
+ unsigned int event;
+ unsigned int stat;
+ unsigned long callback_data;
+ struct drm_gem_object *gem_obj;
+ struct rcar_du_cmm *du_cmm;
+ struct rcar_du_cmm_file_priv *fpriv;
+};
+
+struct cmm_module_t {
+ struct list_head list;
+ union {
+ struct {
+ struct rcar_du_cmm_pending_event *p;
+ int buf_mode;
+ bool one_side;
+ };
+ int reset;
+ };
+};
+
+struct cmm_reg_save {
+#ifdef CONFIG_PM_SLEEP
+ u32 *lut_table;
+ u32 *clu_table;
+#endif /* CONFIG_PM_SLEEP */
+ wait_queue_head_t wait;
+
+ u32 cm2_ctl0; /* CM2_CTL0 */
+ u32 hgo_offset; /* CM2_HGO_OFFSET */
+ u32 hgo_size; /* CM2_HGO_SIZE */
+ u32 hgo_mode; /* CM2_HGO_MODE */
+};
+
+struct rcar_du_cmm {
+ struct rcar_du_crtc *rcrtc;
+
+ /* CMM base address */
+ void __iomem *cmm_base;
+ struct clk *clock;
+
+ struct cmm_module_t lut;
+ struct cmm_module_t clu;
+ struct cmm_module_t hgo;
+
+ struct mutex lock; /* lock for register setting */
+ struct workqueue_struct *workqueue;
+ struct work_struct work;
+
+ struct cmm_reg_save reg_save;
+ bool active;
+ bool dbuf;
+ bool clu_dbuf;
+ bool init;
+ bool direct;
+ bool vsync;
+ bool authority;
+ pid_t pid;
+ bool soc_support;
+};
+
+struct rcar_du_cmm_file_priv {
+ wait_queue_head_t event_wait;
+ struct list_head list;
+ struct list_head active_list;
+ struct list_head *done_list;
+};
+
+static DEFINE_MUTEX(cmm_event_lock);
+static DEFINE_SPINLOCK(cmm_direct_lock);
+
+static inline void event_prev_cancel_locked(struct cmm_module_t *module);
+
+static inline u32 cmm_index(struct rcar_du_cmm *_cmm)
+{
+ struct rcar_du_device *rcdu = _cmm->rcrtc->group->dev;
+
+ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_R8A77965_REGS)) {
+ if ((_cmm)->rcrtc->index == 3)
+ return 2;
+ }
+ return (_cmm)->rcrtc->index;
+}
+
+#define cmm_done_list(_cmm, _fpriv) \
+ (&((_fpriv)->done_list[cmm_index(_cmm)]))
+
+static inline u32 rcar_du_cmm_read(struct rcar_du_cmm *du_cmm, u32 reg)
+{
+ return ioread32(du_cmm->cmm_base + reg);
+}
+
+static inline void rcar_du_cmm_write(struct rcar_du_cmm *du_cmm,
+ u32 reg, u32 data)
+{
+ iowrite32(data, du_cmm->cmm_base + reg);
+}
+
+/* create default CLU table data */
+static inline u32 index_to_clu_data(int index)
+{
+ int r, g, b;
+
+ r = index % CMM_CLU_SAMPLES;
+ index /= CMM_CLU_SAMPLES;
+ g = index % CMM_CLU_SAMPLES;
+ index /= CMM_CLU_SAMPLES;
+ b = index % CMM_CLU_SAMPLES;
+
+ r = (r << 20);
+ if (r > (255 << 16))
+ r = (255 << 16);
+ g = (g << 12);
+ if (g > (255 << 8))
+ g = (255 << 8);
+ b = (b << 4);
+ if (b > (255 << 0))
+ b = (255 << 0);
+
+ return r | g | b;
+}
+
+static struct rcar_du_crtc *id_to_rcrtc(struct drm_device *dev, int crtc_id)
+{
+ struct drm_mode_object *obj;
+ struct drm_crtc *crtc;
+
+ obj = drm_mode_object_find(dev, crtc_id, DRM_MODE_OBJECT_CRTC);
+ if (!obj)
+ return NULL;
+
+ crtc = obj_to_crtc(obj);
+
+ return to_rcar_crtc(crtc);
+}
+
+static struct rcar_du_cmm *id_to_cmm(struct drm_device *dev, int crtc_id)
+{
+ struct rcar_du_crtc *rcrtc = id_to_rcrtc(dev, crtc_id);
+ struct rcar_du_cmm *du_cmm;
+
+ if (!rcrtc)
+ return NULL;
+
+ du_cmm = rcrtc->cmm_handle;
+
+ if (!du_cmm)
+ return NULL;
+
+ if (!du_cmm->active)
+ return NULL;
+
+ return du_cmm;
+}
+
+#ifdef DEBUG_PROCE_TIME
+static long long diff_timevals(struct timeval *start, struct timeval *end)
+{
+ return (end->tv_sec * 1000000LL + end->tv_usec) -
+ (start->tv_sec * 1000000LL + start->tv_usec);
+}
+#endif
+
+int rcar_du_cmm_config(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct rcar_du_cmm_config *config;
+ struct rcar_du_cmm *du_cmm;
+ u32 cm2_ctl0;
+
+ if (!data)
+ return -ENOMEM;
+
+ config = (struct rcar_du_cmm_config *)data;
+
+ du_cmm = id_to_cmm(dev, config->crtc_id);
+ if (!du_cmm)
+ return -EINVAL;
+
+ mutex_lock(&cmm_event_lock);
+
+ if (du_cmm->authority) {
+ if (du_cmm->pid != sys_getpid()) {
+ mutex_unlock(&cmm_event_lock);
+ return -EBUSY;
+ }
+ }
+ du_cmm->authority = config->authority;
+ du_cmm->pid = sys_getpid();
+
+ mutex_unlock(&cmm_event_lock);
+
+ cm2_ctl0 = du_cmm->reg_save.cm2_ctl0;
+ cm2_ctl0 &= ~(CM2_CTL0_TM1_MASK | CM2_CTL0_TM0_MASK |
+ CM2_CTL0_YC | CM2_CTL0_DBUF | CM2_CTL0_CLUDB);
+
+ switch (config->csc) {
+ case CSC_CONVERT_NONE:
+ break;
+
+ case CSC_CONVERT_BT601_YCbCr240:
+ cm2_ctl0 |= (CM2_CTL0_TM_BT601_YC240 | CM2_CTL0_YC);
+ break;
+
+ case CSC_CONVERT_BT601_YCbCr255:
+ cm2_ctl0 |= (CM2_CTL0_TM_BT601_YC255 | CM2_CTL0_YC);
+ break;
+
+ case CSC_CONVERT_BT709_RGB255:
+ cm2_ctl0 |= (CM2_CTL0_TM_BT709_RG255 | CM2_CTL0_YC);
+ break;
+
+ case CSC_CONVERT_BT709_RGB235:
+ cm2_ctl0 |= (CM2_CTL0_TM_BT709_RG235 | CM2_CTL0_YC);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ if (du_cmm->dbuf) {
+ switch (config->lut_buf) {
+ case LUT_DOUBLE_BUFFER_AUTO:
+ case LUT_DOUBLE_BUFFER_A:
+ case LUT_DOUBLE_BUFFER_B:
+ cm2_ctl0 |= CM2_CTL0_DBUF;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ du_cmm->lut.buf_mode = config->lut_buf;
+ } else {
+ return -EINVAL;
+ }
+
+ if (du_cmm->clu_dbuf) {
+ switch (config->clu_buf) {
+ case CLU_DOUBLE_BUFFER_AUTO:
+ case CLU_DOUBLE_BUFFER_A:
+ case CLU_DOUBLE_BUFFER_B:
+ cm2_ctl0 |= CM2_CTL0_CLUDB;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ du_cmm->clu.buf_mode = config->clu_buf;
+ } else {
+ return -EINVAL;
+ }
+
+ rcar_du_cmm_write(du_cmm, CM2_CTL0, cm2_ctl0);
+ du_cmm->reg_save.cm2_ctl0 = cm2_ctl0;
+
+ return 0;
+}
+
+int rcar_du_cmm_lut_set(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct rcar_du_cmm_table *table;
+ struct rcar_du_cmm_file_priv *fpriv = file_priv->driver_priv;
+ struct rcar_du_cmm *du_cmm;
+ struct rcar_du_cmm_pending_event *p;
+ struct drm_gem_object *gem_obj;
+
+ if (!data)
+ return -ENOMEM;
+ table = (struct rcar_du_cmm_table *)data;
+
+ if (table->buff_len < (CMM_LUT_NUM * 4))
+ return -EINVAL;
+
+ du_cmm = id_to_cmm(dev, table->crtc_id);
+ if (!du_cmm)
+ return -EINVAL;
+
+ mutex_lock(&cmm_event_lock);
+
+ if (du_cmm->authority) {
+ if (du_cmm->pid != sys_getpid()) {
+ mutex_unlock(&cmm_event_lock);
+ return -EBUSY;
+ }
+ }
+
+ mutex_unlock(&cmm_event_lock);
+
+ gem_obj = drm_gem_object_lookup(file_priv, table->buff);
+ if (!gem_obj)
+ return -ENOMEM;
+
+ p = kzalloc(sizeof(*p), GFP_KERNEL);
+ if (!p) {
+ drm_gem_object_unreference_unlocked(gem_obj);
+ return -ENOMEM;
+ }
+
+ p->gem_obj = gem_obj;
+ p->event = CMM_EVENT_LUT_DONE;
+ p->stat = QUE_STAT_PENDING;
+ p->callback_data = (uint64_t)table->user_data;
+ p->du_cmm = du_cmm;
+ p->fpriv = fpriv;
+
+ mutex_lock(&cmm_event_lock);
+
+ list_add_tail(&p->link, &du_cmm->lut.list);
+ list_add_tail(&p->fpriv_link, &fpriv->list);
+
+ event_prev_cancel_locked(&du_cmm->lut);
+
+ if (du_cmm->direct)
+ queue_work(du_cmm->workqueue, &du_cmm->work);
+
+ drm_crtc_vblank_get(&du_cmm->rcrtc->crtc);
+
+ mutex_unlock(&cmm_event_lock);
+
+ return 0;
+}
+
+int rcar_du_cmm_clu_set(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct rcar_du_cmm_table *table;
+ struct rcar_du_cmm_file_priv *fpriv = file_priv->driver_priv;
+ struct rcar_du_cmm *du_cmm;
+ struct rcar_du_cmm_pending_event *p;
+ struct drm_gem_object *gem_obj;
+ struct rcar_du_device *rcdu;
+
+ if (!data)
+ return -ENOMEM;
+ table = (struct rcar_du_cmm_table *)data;
+
+ du_cmm = id_to_cmm(dev, table->crtc_id);
+ if (!du_cmm)
+ return -EINVAL;
+
+ if (!du_cmm->soc_support) {
+ rcdu = du_cmm->rcrtc->group->dev;
+ dev_err(rcdu->dev, "Double buffer of CLU is not supported in H3 ES1.x.\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&cmm_event_lock);
+
+ if (du_cmm->authority) {
+ if (du_cmm->pid != sys_getpid()) {
+ mutex_unlock(&cmm_event_lock);
+ return -EBUSY;
+ }
+ }
+
+ mutex_unlock(&cmm_event_lock);
+
+ if (table->buff_len < (CMM_CLU_NUM * 4))
+ return -EINVAL;
+
+ gem_obj = drm_gem_object_lookup(file_priv, table->buff);
+ if (!gem_obj)
+ return -ENOMEM;
+
+ p = kzalloc(sizeof(*p), GFP_KERNEL);
+ if (!p) {
+ drm_gem_object_unreference_unlocked(gem_obj);
+ return -ENOMEM;
+ }
+
+ p->gem_obj = gem_obj;
+ p->event = CMM_EVENT_CLU_DONE;
+ p->stat = QUE_STAT_PENDING;
+ p->callback_data = (uint64_t)table->user_data;
+ p->du_cmm = du_cmm;
+ p->fpriv = fpriv;
+
+ mutex_lock(&cmm_event_lock);
+
+ list_add_tail(&p->link, &du_cmm->clu.list);
+ list_add_tail(&p->fpriv_link, &fpriv->list);
+
+ event_prev_cancel_locked(&du_cmm->clu);
+
+ if (du_cmm->direct)
+ queue_work(du_cmm->workqueue, &du_cmm->work);
+
+ drm_crtc_vblank_get(&du_cmm->rcrtc->crtc);
+
+ mutex_unlock(&cmm_event_lock);
+
+ return 0;
+}
+
+int rcar_du_cmm_hgo_set(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct rcar_du_cmm_hgo_config *hgo;
+ struct rcar_du_cmm *du_cmm;
+ const struct drm_display_mode *mode;
+ u32 hists;
+ u32 cm2_ctl0;
+
+ if (!data)
+ return -ENOMEM;
+ hgo = (struct rcar_du_cmm_hgo_config *)data;
+
+ du_cmm = id_to_cmm(dev, hgo->crtc_id);
+ if (!du_cmm)
+ return -EINVAL;
+
+ mutex_lock(&cmm_event_lock);
+
+ if (du_cmm->authority) {
+ if (du_cmm->pid != sys_getpid()) {
+ mutex_unlock(&cmm_event_lock);
+ return -EBUSY;
+ }
+ }
+
+ mutex_unlock(&cmm_event_lock);
+
+ mode = &du_cmm->rcrtc->crtc.mode;
+
+ if (hgo->width < 1 || hgo->height < 1 ||
+ (mode->hdisplay < (hgo->x_offset + hgo->width)) ||
+ (mode->vdisplay < (hgo->y_offset + hgo->height)))
+ return -EINVAL;
+
+ if ((hgo->mode & ~CM2_HGO_MODE_MASK) ||
+ ((hgo->mode & (0x3 << 0)) == (0x3 << 0)) ||
+ ((hgo->mode & (0x3 << 2)) == (0x3 << 2)))
+ return -EINVAL;
+
+ switch (hgo->ctrl) {