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cpc_backplane_edge.v
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cpc_backplane_edge.v
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//
//
// netlister.py format
//
// (c) Revaldinho, 2020
//
module cpc_backplane_edge ();
// wire declarations
supply0 VSS;
supply1 VDD_CPC;
supply1 VDD_EXT;
supply1 VDD1;
wire Sound;
wire A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 ;
wire D7,D6,D5,D4,D3,D2,D1,D0 ;
wire MREQ_B;
wire M1_B;
wire RFSH_B;
wire IOREQ_B;
wire RD_B;
wire WR_B;
wire HALT_B;
wire INT_B ;
wire NMI_B ;
wire BUSRQ_B;
wire BUSACK_B;
wire READY;
wire BUSRESET_B;
wire RESET_B;
wire ROMEN_B;
wire ROMDIS ;
wire RAMRD_B;
wire RAMDIS;
wire CURSOR;
wire LPEN;
wire EXP_B;
wire CLK;
// 3 pin header with link to use either CPC or external 5V power for the board
hdr1x03 L0 (
.p1(VDD_CPC),
.p2(VDD1),
.p3(VDD_EXT)
);
// 3 pin Tabbed power connector for external 5V power
powerheader3 PCONN (
.vdd1(VDD_EXT),
.vdd2(VDD_EXT),
.gnd(VSS)
);
// Radial electolytics
cap22uf CAP22UF_0(.minus(VSS),.plus(VDD1));
cap22uf CAP22UF_1(.minus(VSS),.plus(VDD1));
// Amstrad CPC Edge Connector
//
// V1.01 Corrected upper and lower rows for male header.
idc_hdr_50w CONN0 (
.p50(Sound), .p49(VSS),
.p48(A15), .p47(A14),
.p46(A13), .p45(A12),
.p44(A11), .p43(A10),
.p42(A9), .p41(A8)
.p40(A7), .p39(A6),
.p38(A5), .p37(A4),
.p36(A3), .p35(A2),
.p34(A1), .p33(A0),
.p32(D7), .p31(D6)
.p30(D5), .p29(D4),
.p28(D3), .p27(D2),
.p26(D1), .p25(D0),
.p24(VDD_CPC), .p23(MREQ_B),
.p22(M1_B), .p21(RFSH_B),
.p20(IOREQ_B), .p19(RD_B),
.p18(WR_B), .p17(HALT_B),
.p16(INT_B), .p15(NMI_B),
.p14(BUSRQ_B), .p13(BUSACK_B),
.p12(READY), .p11(BUSRESET_B),
.p10(RESET_B), .p9 (ROMEN_B),
.p8 (ROMDIS), .p7 (RAMRD_B),
.p6 (RAMDIS), .p5 (CURSOR),
.p4 (LPEN), .p3 (EXP_B),
.p2 (VSS), .p1 (CLK)
) ;
// Female sockets have pins reversed by orientation on the board so keep the same
// logical connections and the male header above.
idc_skt_50w CONN1 (
.p50(Sound), .p49(VSS),
.p48(A15), .p47(A14),
.p46(A13), .p45(A12),
.p44(A11), .p43(A10),
.p42(A9), .p41(A8)
.p40(A7), .p39(A6),
.p38(A5), .p37(A4),
.p36(A3), .p35(A2),
.p34(A1), .p33(A0),
.p32(D7), .p31(D6)
.p30(D5), .p29(D4),
.p28(D3), .p27(D2),
.p26(D1), .p25(D0),
.p24(VDD1), .p23(MREQ_B),
.p22(M1_B), .p21(RFSH_B),
.p20(IOREQ_B), .p19(RD_B),
.p18(WR_B), .p17(HALT_B),
.p16(INT_B), .p15(NMI_B),
.p14(BUSRQ_B), .p13(BUSACK_B),
.p12(READY), .p11(BUSRESET_B),
.p10(RESET_B), .p9 (ROMEN_B),
.p8 (ROMDIS), .p7 (RAMRD_B),
.p6 (RAMDIS), .p5 (CURSOR),
.p4 (LPEN), .p3 (EXP_B),
.p2 (VSS), .p1 (CLK)
) ;
idc_skt_50w CONN2 (
.p50(Sound), .p49(VSS),
.p48(A15), .p47(A14),
.p46(A13), .p45(A12),
.p44(A11), .p43(A10),
.p42(A9), .p41(A8)
.p40(A7), .p39(A6),
.p38(A5), .p37(A4),
.p36(A3), .p35(A2),
.p34(A1), .p33(A0),
.p32(D7), .p31(D6)
.p30(D5), .p29(D4),
.p28(D3), .p27(D2),
.p26(D1), .p25(D0),
.p24(VDD1), .p23(MREQ_B),
.p22(M1_B), .p21(RFSH_B),
.p20(IOREQ_B), .p19(RD_B),
.p18(WR_B), .p17(HALT_B),
.p16(INT_B), .p15(NMI_B),
.p14(BUSRQ_B), .p13(BUSACK_B),
.p12(READY), .p11(BUSRESET_B),
.p10(RESET_B), .p9 (ROMEN_B),
.p8 (ROMDIS), .p7 (RAMRD_B),
.p6 (RAMDIS), .p5 (CURSOR),
.p4 (LPEN), .p3 (EXP_B),
.p2 (VSS), .p1 (CLK)
) ;
idc_skt_50w CONN3 (
.p50(Sound), .p49(VSS),
.p48(A15), .p47(A14),
.p46(A13), .p45(A12),
.p44(A11), .p43(A10),
.p42(A9), .p41(A8)
.p40(A7), .p39(A6),
.p38(A5), .p37(A4),
.p36(A3), .p35(A2),
.p34(A1), .p33(A0),
.p32(D7), .p31(D6)
.p30(D5), .p29(D4),
.p28(D3), .p27(D2),
.p26(D1), .p25(D0),
.p24(VDD1), .p23(MREQ_B),
.p22(M1_B), .p21(RFSH_B),
.p20(IOREQ_B), .p19(RD_B),
.p18(WR_B), .p17(HALT_B),
.p16(INT_B), .p15(NMI_B),
.p14(BUSRQ_B), .p13(BUSACK_B),
.p12(READY), .p11(BUSRESET_B),
.p10(RESET_B), .p9 (ROMEN_B),
.p8 (ROMDIS), .p7 (RAMRD_B),
.p6 (RAMDIS), .p5 (CURSOR),
.p4 (LPEN), .p3 (EXP_B),
.p2 (VSS), .p1 (CLK)
) ;
idc_skt_50w CONN4 (
.p50(Sound), .p49(VSS),
.p48(A15), .p47(A14),
.p46(A13), .p45(A12),
.p44(A11), .p43(A10),
.p42(A9), .p41(A8)
.p40(A7), .p39(A6),
.p38(A5), .p37(A4),
.p36(A3), .p35(A2),
.p34(A1), .p33(A0),
.p32(D7), .p31(D6)
.p30(D5), .p29(D4),
.p28(D3), .p27(D2),
.p26(D1), .p25(D0),
.p24(VDD1), .p23(MREQ_B),
.p22(M1_B), .p21(RFSH_B),
.p20(IOREQ_B), .p19(RD_B),
.p18(WR_B), .p17(HALT_B),
.p16(INT_B), .p15(NMI_B),
.p14(BUSRQ_B), .p13(BUSACK_B),
.p12(READY), .p11(BUSRESET_B),
.p10(RESET_B), .p9 (ROMEN_B),
.p8 (ROMDIS), .p7 (RAMRD_B),
.p6 (RAMDIS), .p5 (CURSOR),
.p4 (LPEN), .p3 (EXP_B),
.p2 (VSS), .p1 (CLK)
) ;
// Edge connector pin numbering is upside down cf the standard IDC headers
edge50w CONN5 (
.p1 (Sound), .p2 (VSS),
.p3 (A15), .p4 (A14),
.p5 (A13), .p6 (A12),
.p7 (A11), .p8 (A10),
.p9 (A9), .p10(A8)
.p11(A7), .p12(A6),
.p13(A5), .p14(A4),
.p15(A3), .p16(A2),
.p17(A1), .p18(A0),
.p19(D7), .p20(D6)
.p21(D5), .p22(D4),
.p23(D3), .p24(D2),
.p25(D1), .p26(D0),
.p27(VDD1), .p28(MREQ_B),
.p29(M1_B), .p30(RFSH_B),
.p31(IOREQ_B), .p32(RD_B),
.p33(WR_B), .p34(HALT_B),
.p35(INT_B), .p36(NMI_B),
.p37(BUSRQ_B), .p38(BUSACK_B),
.p39(READY), .p40(BUSRESET_B),
.p41(RESET_B), .p42(ROMEN_B),
.p43(ROMDIS), .p44(RAMRD_B),
.p45(RAMDIS), .p46(CURSOR),
.p47(LPEN), .p48(EXP_B),
.p49(VSS), .p50(CLK)
) ;
endmodule