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DRC errors with Vivado 2023.2 #56

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gonsolo opened this issue Apr 22, 2024 · 4 comments
Closed

DRC errors with Vivado 2023.2 #56

gonsolo opened this issue Apr 22, 2024 · 4 comments

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@gonsolo
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gonsolo commented Apr 22, 2024

I get the following errors using Vivado 2023.2 on Linux running build.tcl:

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 6 out of 6 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: code[2:0], clk, led, and ok.

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 6 out of 6 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: code[2:0], clk, led, and ok.

Any advice?

@gonsolo gonsolo changed the title DRC errors with Vivao 2023.2 DRC errors with Vivado 2023.2 Apr 22, 2024
@makslevental
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Did you manage to figure this out?

@gonsolo
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gonsolo commented Apr 30, 2024

Yes. I manually fixed the ports (clk, led, ok) in Vivado.

@gonsolo gonsolo closed this as completed Apr 30, 2024
@makslevental
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Yes. I manually fixed the ports (clk, led, ok) in Vivado.

Which IOSTANDARD did you set?

@gonsolo
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gonsolo commented Apr 30, 2024

Ha, hard to remember after one week. 🙄
I just played around until it worked but I believe it was just a matter of setting it explicitly to the default. I have no idea why that would make a difference.

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