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ira.c
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ira.c
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/* Integrated Register Allocator (IRA) entry point.
Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011
Free Software Foundation, Inc.
Contributed by Vladimir Makarov <vmakarov@redhat.com>.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* The integrated register allocator (IRA) is a
regional register allocator performing graph coloring on a top-down
traversal of nested regions. Graph coloring in a region is based
on Chaitin-Briggs algorithm. It is called integrated because
register coalescing, register live range splitting, and choosing a
better hard register are done on-the-fly during coloring. Register
coalescing and choosing a cheaper hard register is done by hard
register preferencing during hard register assigning. The live
range splitting is a byproduct of the regional register allocation.
Major IRA notions are:
o *Region* is a part of CFG where graph coloring based on
Chaitin-Briggs algorithm is done. IRA can work on any set of
nested CFG regions forming a tree. Currently the regions are
the entire function for the root region and natural loops for
the other regions. Therefore data structure representing a
region is called loop_tree_node.
o *Cover class* is a register class belonging to a set of
non-intersecting register classes containing all of the
hard-registers available for register allocation. The set of
all cover classes for a target is defined in the corresponding
machine-description file according some criteria. Such notion
is needed because Chaitin-Briggs algorithm works on
non-intersected register classes.
o *Allocno* represents the live range of a pseudo-register in a
region. Besides the obvious attributes like the corresponding
pseudo-register number, cover class, conflicting allocnos and
conflicting hard-registers, there are a few allocno attributes
which are important for understanding the allocation algorithm:
- *Live ranges*. This is a list of ranges of *program
points* where the allocno lives. Program points represent
places where a pseudo can be born or become dead (there are
approximately two times more program points than the insns)
and they are represented by integers starting with 0. The
live ranges are used to find conflicts between allocnos of
different cover classes. They also play very important role
for the transformation of the IRA internal representation of
several regions into a one region representation. The later is
used during the reload pass work because each allocno
represents all of the corresponding pseudo-registers.
- *Hard-register costs*. This is a vector of size equal to the
number of available hard-registers of the allocno's cover
class. The cost of a callee-clobbered hard-register for an
allocno is increased by the cost of save/restore code around
the calls through the given allocno's life. If the allocno
is a move instruction operand and another operand is a
hard-register of the allocno's cover class, the cost of the
hard-register is decreased by the move cost.
When an allocno is assigned, the hard-register with minimal
full cost is used. Initially, a hard-register's full cost is
the corresponding value from the hard-register's cost vector.
If the allocno is connected by a *copy* (see below) to
another allocno which has just received a hard-register, the
cost of the hard-register is decreased. Before choosing a
hard-register for an allocno, the allocno's current costs of
the hard-registers are modified by the conflict hard-register
costs of all of the conflicting allocnos which are not
assigned yet.
- *Conflict hard-register costs*. This is a vector of the same
size as the hard-register costs vector. To permit an
unassigned allocno to get a better hard-register, IRA uses
this vector to calculate the final full cost of the
available hard-registers. Conflict hard-register costs of an
unassigned allocno are also changed with a change of the
hard-register cost of the allocno when a copy involving the
allocno is processed as described above. This is done to
show other unassigned allocnos that a given allocno prefers
some hard-registers in order to remove the move instruction
corresponding to the copy.
o *Cap*. If a pseudo-register does not live in a region but
lives in a nested region, IRA creates a special allocno called
a cap in the outer region. A region cap is also created for a
subregion cap.
o *Copy*. Allocnos can be connected by copies. Copies are used
to modify hard-register costs for allocnos during coloring.
Such modifications reflects a preference to use the same
hard-register for the allocnos connected by copies. Usually
copies are created for move insns (in this case it results in
register coalescing). But IRA also creates copies for operands
of an insn which should be assigned to the same hard-register
due to constraints in the machine description (it usually
results in removing a move generated in reload to satisfy
the constraints) and copies referring to the allocno which is
the output operand of an instruction and the allocno which is
an input operand dying in the instruction (creation of such
copies results in less register shuffling). IRA *does not*
create copies between the same register allocnos from different
regions because we use another technique for propagating
hard-register preference on the borders of regions.
Allocnos (including caps) for the upper region in the region tree
*accumulate* information important for coloring from allocnos with
the same pseudo-register from nested regions. This includes
hard-register and memory costs, conflicts with hard-registers,
allocno conflicts, allocno copies and more. *Thus, attributes for
allocnos in a region have the same values as if the region had no
subregions*. It means that attributes for allocnos in the
outermost region corresponding to the function have the same values
as though the allocation used only one region which is the entire
function. It also means that we can look at IRA work as if the
first IRA did allocation for all function then it improved the
allocation for loops then their subloops and so on.
IRA major passes are:
o Building IRA internal representation which consists of the
following subpasses:
* First, IRA builds regions and creates allocnos (file
ira-build.c) and initializes most of their attributes.
* Then IRA finds a cover class for each allocno and calculates
its initial (non-accumulated) cost of memory and each
hard-register of its cover class (file ira-cost.c).
* IRA creates live ranges of each allocno, calulates register
pressure for each cover class in each region, sets up
conflict hard registers for each allocno and info about calls
the allocno lives through (file ira-lives.c).
* IRA removes low register pressure loops from the regions
mostly to speed IRA up (file ira-build.c).
* IRA propagates accumulated allocno info from lower region
allocnos to corresponding upper region allocnos (file
ira-build.c).
* IRA creates all caps (file ira-build.c).
* Having live-ranges of allocnos and their cover classes, IRA
creates conflicting allocnos of the same cover class for each
allocno. Conflicting allocnos are stored as a bit vector or
array of pointers to the conflicting allocnos whatever is
more profitable (file ira-conflicts.c). At this point IRA
creates allocno copies.
o Coloring. Now IRA has all necessary info to start graph coloring
process. It is done in each region on top-down traverse of the
region tree (file ira-color.c). There are following subpasses:
* Putting allocnos onto the coloring stack. IRA uses Briggs
optimistic coloring which is a major improvement over
Chaitin's coloring. Therefore IRA does not spill allocnos at
this point. There is some freedom in the order of putting
allocnos on the stack which can affect the final result of
the allocation. IRA uses some heuristics to improve the order.
* Popping the allocnos from the stack and assigning them hard
registers. If IRA can not assign a hard register to an
allocno and the allocno is coalesced, IRA undoes the
coalescing and puts the uncoalesced allocnos onto the stack in
the hope that some such allocnos will get a hard register
separately. If IRA fails to assign hard register or memory
is more profitable for it, IRA spills the allocno. IRA
assigns the allocno the hard-register with minimal full
allocation cost which reflects the cost of usage of the
hard-register for the allocno and cost of usage of the
hard-register for allocnos conflicting with given allocno.
* After allono assigning in the region, IRA modifies the hard
register and memory costs for the corresponding allocnos in
the subregions to reflect the cost of possible loads, stores,
or moves on the border of the region and its subregions.
When default regional allocation algorithm is used
(-fira-algorithm=mixed), IRA just propagates the assignment
for allocnos if the register pressure in the region for the
corresponding cover class is less than number of available
hard registers for given cover class.
o Spill/restore code moving. When IRA performs an allocation
by traversing regions in top-down order, it does not know what
happens below in the region tree. Therefore, sometimes IRA
misses opportunities to perform a better allocation. A simple
optimization tries to improve allocation in a region having
subregions and containing in another region. If the
corresponding allocnos in the subregion are spilled, it spills
the region allocno if it is profitable. The optimization
implements a simple iterative algorithm performing profitable
transformations while they are still possible. It is fast in
practice, so there is no real need for a better time complexity
algorithm.
o Code change. After coloring, two allocnos representing the same
pseudo-register outside and inside a region respectively may be
assigned to different locations (hard-registers or memory). In
this case IRA creates and uses a new pseudo-register inside the
region and adds code to move allocno values on the region's
borders. This is done during top-down traversal of the regions
(file ira-emit.c). In some complicated cases IRA can create a
new allocno to move allocno values (e.g. when a swap of values
stored in two hard-registers is needed). At this stage, the
new allocno is marked as spilled. IRA still creates the
pseudo-register and the moves on the region borders even when
both allocnos were assigned to the same hard-register. If the
reload pass spills a pseudo-register for some reason, the
effect will be smaller because another allocno will still be in
the hard-register. In most cases, this is better then spilling
both allocnos. If reload does not change the allocation
for the two pseudo-registers, the trivial move will be removed
by post-reload optimizations. IRA does not generate moves for
allocnos assigned to the same hard register when the default
regional allocation algorithm is used and the register pressure
in the region for the corresponding allocno cover class is less
than number of available hard registers for given cover class.
IRA also does some optimizations to remove redundant stores and
to reduce code duplication on the region borders.
o Flattening internal representation. After changing code, IRA
transforms its internal representation for several regions into
one region representation (file ira-build.c). This process is
called IR flattening. Such process is more complicated than IR
rebuilding would be, but is much faster.
o After IR flattening, IRA tries to assign hard registers to all
spilled allocnos. This is impelemented by a simple and fast
priority coloring algorithm (see function
ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
created during the code change pass can be assigned to hard
registers.
o At the end IRA calls the reload pass. The reload pass
communicates with IRA through several functions in file
ira-color.c to improve its decisions in
* sharing stack slots for the spilled pseudos based on IRA info
about pseudo-register conflicts.
* reassigning hard-registers to all spilled pseudos at the end
of each reload iteration.
* choosing a better hard-register to spill based on IRA info
about pseudo-register live ranges and the register pressure
in places where the pseudo-register lives.
IRA uses a lot of data representing the target processors. These
data are initilized in file ira.c.
If function has no loops (or the loops are ignored when
-fira-algorithm=CB is used), we have classic Chaitin-Briggs
coloring (only instead of separate pass of coalescing, we use hard
register preferencing). In such case, IRA works much faster
because many things are not made (like IR flattening, the
spill/restore optimization, and the code change).
Literature is worth to read for better understanding the code:
o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
Graph Coloring Register Allocation.
o David Callahan, Brian Koblenz. Register allocation via
hierarchical graph coloring.
o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
Coloring Register Allocation: A Study of the Chaitin-Briggs and
Callahan-Koblenz Algorithms.
o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
Register Allocation Based on Graph Fusion.
o Vladimir Makarov. The Integrated Register Allocator for GCC.
o Vladimir Makarov. The top-down register allocator for irregular
register file architectures.
*/
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "regs.h"
#include "rtl.h"
#include "tm_p.h"
#include "target.h"
#include "flags.h"
#include "obstack.h"
#include "bitmap.h"
#include "hard-reg-set.h"
#include "basic-block.h"
#include "df.h"
#include "expr.h"
#include "recog.h"
#include "params.h"
#include "timevar.h"
#include "tree-pass.h"
#include "output.h"
#include "except.h"
#include "reload.h"
#include "diagnostic-core.h"
#include "integrate.h"
#include "ggc.h"
#include "ira-int.h"
struct target_ira default_target_ira;
struct target_ira_int default_target_ira_int;
#if SWITCHABLE_TARGET
struct target_ira *this_target_ira = &default_target_ira;
struct target_ira_int *this_target_ira_int = &default_target_ira_int;
#endif
/* A modified value of flag `-fira-verbose' used internally. */
int internal_flag_ira_verbose;
/* Dump file of the allocator if it is not NULL. */
FILE *ira_dump_file;
/* The number of elements in the following array. */
int ira_spilled_reg_stack_slots_num;
/* The following array contains info about spilled pseudo-registers
stack slots used in current function so far. */
struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots;
/* Correspondingly overall cost of the allocation, cost of the
allocnos assigned to hard-registers, cost of the allocnos assigned
to memory, cost of loads, stores and register move insns generated
for pseudo-register live range splitting (see ira-emit.c). */
int ira_overall_cost;
int ira_reg_cost, ira_mem_cost;
int ira_load_cost, ira_store_cost, ira_shuffle_cost;
int ira_move_loops_num, ira_additional_jumps_num;
/* All registers that can be eliminated. */
HARD_REG_SET eliminable_regset;
/* Temporary hard reg set used for a different calculation. */
static HARD_REG_SET temp_hard_regset;
/* The function sets up the map IRA_REG_MODE_HARD_REGSET. */
static void
setup_reg_mode_hard_regset (void)
{
int i, m, hard_regno;
for (m = 0; m < NUM_MACHINE_MODES; m++)
for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++)
{
CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]);
for (i = hard_regno_nregs[hard_regno][m] - 1; i >= 0; i--)
if (hard_regno + i < FIRST_PSEUDO_REGISTER)
SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m],
hard_regno + i);
}
}
#define no_unit_alloc_regs \
(this_target_ira_int->x_no_unit_alloc_regs)
/* The function sets up the three arrays declared above. */
static void
setup_class_hard_regs (void)
{
int cl, i, hard_regno, n;
HARD_REG_SET processed_hard_reg_set;
ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER);
for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
{
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
CLEAR_HARD_REG_SET (processed_hard_reg_set);
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
ira_non_ordered_class_hard_regs[cl][i] = -1;
ira_class_hard_reg_index[cl][i] = -1;
}
for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
#ifdef REG_ALLOC_ORDER
hard_regno = reg_alloc_order[i];
#else
hard_regno = i;
#endif
if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno))
continue;
SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno);
if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno))
ira_class_hard_reg_index[cl][hard_regno] = -1;
else
{
ira_class_hard_reg_index[cl][hard_regno] = n;
ira_class_hard_regs[cl][n++] = hard_regno;
}
}
ira_class_hard_regs_num[cl] = n;
for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (TEST_HARD_REG_BIT (temp_hard_regset, i))
ira_non_ordered_class_hard_regs[cl][n++] = i;
ira_assert (ira_class_hard_regs_num[cl] == n);
}
}
/* Set up IRA_AVAILABLE_CLASS_REGS. */
static void
setup_available_class_regs (void)
{
int i, j;
memset (ira_available_class_regs, 0, sizeof (ira_available_class_regs));
for (i = 0; i < N_REG_CLASSES; i++)
{
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
if (TEST_HARD_REG_BIT (temp_hard_regset, j))
ira_available_class_regs[i]++;
}
}
/* Set up global variables defining info about hard registers for the
allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
that we can use the hard frame pointer for the allocation. */
static void
setup_alloc_regs (bool use_hard_frame_p)
{
#ifdef ADJUST_REG_ALLOC_ORDER
ADJUST_REG_ALLOC_ORDER;
#endif
COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set);
if (! use_hard_frame_p)
SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM);
setup_class_hard_regs ();
setup_available_class_regs ();
}
/* Set up IRA_MEMORY_MOVE_COST, IRA_REGISTER_MOVE_COST. */
static void
setup_class_subset_and_memory_move_costs (void)
{
int cl, cl2, mode;
HARD_REG_SET temp_hard_regset2;
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
ira_memory_move_cost[mode][NO_REGS][0]
= ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX;
for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
{
if (cl != (int) NO_REGS)
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
{
ira_memory_move_cost[mode][cl][0] =
memory_move_cost ((enum machine_mode) mode,
(enum reg_class) cl, false);
ira_memory_move_cost[mode][cl][1] =
memory_move_cost ((enum machine_mode) mode,
(enum reg_class) cl, true);
/* Costs for NO_REGS are used in cost calculation on the
1st pass when the preferred register classes are not
known yet. In this case we take the best scenario. */
if (ira_memory_move_cost[mode][NO_REGS][0]
> ira_memory_move_cost[mode][cl][0])
ira_memory_move_cost[mode][NO_REGS][0]
= ira_memory_move_cost[mode][cl][0];
if (ira_memory_move_cost[mode][NO_REGS][1]
> ira_memory_move_cost[mode][cl][1])
ira_memory_move_cost[mode][NO_REGS][1]
= ira_memory_move_cost[mode][cl][1];
}
for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--)
{
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]);
AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
ira_class_subset_p[cl][cl2]
= hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2);
}
}
}
/* Define the following macro if allocation through malloc if
preferable. */
#define IRA_NO_OBSTACK
#ifndef IRA_NO_OBSTACK
/* Obstack used for storing all dynamic data (except bitmaps) of the
IRA. */
static struct obstack ira_obstack;
#endif
/* Obstack used for storing all bitmaps of the IRA. */
static struct bitmap_obstack ira_bitmap_obstack;
/* Allocate memory of size LEN for IRA data. */
void *
ira_allocate (size_t len)
{
void *res;
#ifndef IRA_NO_OBSTACK
res = obstack_alloc (&ira_obstack, len);
#else
res = xmalloc (len);
#endif
return res;
}
/* Reallocate memory PTR of size LEN for IRA data. */
void *
ira_reallocate (void *ptr, size_t len)
{
void *res;
#ifndef IRA_NO_OBSTACK
res = obstack_alloc (&ira_obstack, len);
#else
res = xrealloc (ptr, len);
#endif
return res;
}
/* Free memory ADDR allocated for IRA data. */
void
ira_free (void *addr ATTRIBUTE_UNUSED)
{
#ifndef IRA_NO_OBSTACK
/* do nothing */
#else
free (addr);
#endif
}
/* Allocate and returns bitmap for IRA. */
bitmap
ira_allocate_bitmap (void)
{
return BITMAP_ALLOC (&ira_bitmap_obstack);
}
/* Free bitmap B allocated for IRA. */
void
ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED)
{
/* do nothing */
}
/* Output information about allocation of all allocnos (except for
caps) into file F. */
void
ira_print_disposition (FILE *f)
{
int i, n, max_regno;
ira_allocno_t a;
basic_block bb;
fprintf (f, "Disposition:");
max_regno = max_reg_num ();
for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
for (a = ira_regno_allocno_map[i];
a != NULL;
a = ALLOCNO_NEXT_REGNO_ALLOCNO (a))
{
if (n % 4 == 0)
fprintf (f, "\n");
n++;
fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
fprintf (f, "b%-3d", bb->index);
else
fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop->num);
if (ALLOCNO_HARD_REGNO (a) >= 0)
fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a));
else
fprintf (f, " mem");
}
fprintf (f, "\n");
}
/* Outputs information about allocation of all allocnos into
stderr. */
void
ira_debug_disposition (void)
{
ira_print_disposition (stderr);
}
#define alloc_reg_class_subclasses \
(this_target_ira_int->x_alloc_reg_class_subclasses)
/* Initialize the table of subclasses of each reg class. */
static void
setup_reg_subclasses (void)
{
int i, j;
HARD_REG_SET temp_hard_regset2;
for (i = 0; i < N_REG_CLASSES; i++)
for (j = 0; j < N_REG_CLASSES; j++)
alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES;
for (i = 0; i < N_REG_CLASSES; i++)
{
if (i == (int) NO_REGS)
continue;
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (hard_reg_set_empty_p (temp_hard_regset))
continue;
for (j = 0; j < N_REG_CLASSES; j++)
if (i != j)
{
enum reg_class *p;
COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]);
AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
if (! hard_reg_set_subset_p (temp_hard_regset,
temp_hard_regset2))
continue;
p = &alloc_reg_class_subclasses[j][0];
while (*p != LIM_REG_CLASSES) p++;
*p = (enum reg_class) i;
}
}
}
/* Set the four global variables defined above. */
static void
setup_cover_and_important_classes (void)
{
int i, j, n, cl;
bool set_p;
const reg_class_t *cover_classes;
HARD_REG_SET temp_hard_regset2;
static enum reg_class classes[LIM_REG_CLASSES + 1];
if (targetm.ira_cover_classes == NULL)
cover_classes = NULL;
else
cover_classes = targetm.ira_cover_classes ();
if (cover_classes == NULL)
ira_assert (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY);
else
{
for (i = 0; (cl = cover_classes[i]) != LIM_REG_CLASSES; i++)
classes[i] = (enum reg_class) cl;
classes[i] = LIM_REG_CLASSES;
}
if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY)
{
n = 0;
for (i = 0; i <= LIM_REG_CLASSES; i++)
{
if (i == NO_REGS)
continue;
#ifdef CONSTRAINT_NUM_DEFINED_P
for (j = 0; j < CONSTRAINT__LIMIT; j++)
if ((int) REG_CLASS_FOR_CONSTRAINT ((enum constraint_num) j) == i)
break;
if (j < CONSTRAINT__LIMIT)
{
classes[n++] = (enum reg_class) i;
continue;
}
#endif
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
for (j = 0; j < LIM_REG_CLASSES; j++)
{
if (i == j)
continue;
COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]);
AND_COMPL_HARD_REG_SET (temp_hard_regset2,
no_unit_alloc_regs);
if (hard_reg_set_equal_p (temp_hard_regset,
temp_hard_regset2))
break;
}
if (j >= i)
classes[n++] = (enum reg_class) i;
}
classes[n] = LIM_REG_CLASSES;
}
ira_reg_class_cover_size = 0;
for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++)
{
for (j = 0; j < i; j++)
if (flag_ira_algorithm != IRA_ALGORITHM_PRIORITY
&& reg_classes_intersect_p ((enum reg_class) cl, classes[j]))
gcc_unreachable ();
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (! hard_reg_set_empty_p (temp_hard_regset))
ira_reg_class_cover[ira_reg_class_cover_size++] = (enum reg_class) cl;
}
ira_important_classes_num = 0;
for (cl = 0; cl < N_REG_CLASSES; cl++)
{
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (! hard_reg_set_empty_p (temp_hard_regset))
{
set_p = false;
for (j = 0; j < ira_reg_class_cover_size; j++)
{
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
COPY_HARD_REG_SET (temp_hard_regset2,
reg_class_contents[ira_reg_class_cover[j]]);
AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
if ((enum reg_class) cl == ira_reg_class_cover[j]
|| hard_reg_set_equal_p (temp_hard_regset,
temp_hard_regset2))
break;
else if (hard_reg_set_subset_p (temp_hard_regset,
temp_hard_regset2))
set_p = true;
}
if (set_p && j >= ira_reg_class_cover_size)
ira_important_classes[ira_important_classes_num++]
= (enum reg_class) cl;
}
}
for (j = 0; j < ira_reg_class_cover_size; j++)
ira_important_classes[ira_important_classes_num++]
= ira_reg_class_cover[j];
}
/* Set up array IRA_CLASS_TRANSLATE. */
static void
setup_class_translate (void)
{
int cl, mode;
enum reg_class cover_class, best_class, *cl_ptr;
int i, cost, min_cost, best_cost;
for (cl = 0; cl < N_REG_CLASSES; cl++)
ira_class_translate[cl] = NO_REGS;
if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY)
for (cl = 0; cl < LIM_REG_CLASSES; cl++)
{
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
for (i = 0; i < ira_reg_class_cover_size; i++)
{
HARD_REG_SET temp_hard_regset2;
cover_class = ira_reg_class_cover[i];
COPY_HARD_REG_SET (temp_hard_regset2,
reg_class_contents[cover_class]);
AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
if (hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2))
ira_class_translate[cl] = cover_class;
}
}
for (i = 0; i < ira_reg_class_cover_size; i++)
{
cover_class = ira_reg_class_cover[i];
if (flag_ira_algorithm != IRA_ALGORITHM_PRIORITY)
for (cl_ptr = &alloc_reg_class_subclasses[cover_class][0];
(cl = *cl_ptr) != LIM_REG_CLASSES;
cl_ptr++)
{
if (ira_class_translate[cl] == NO_REGS)
ira_class_translate[cl] = cover_class;
#ifdef ENABLE_IRA_CHECKING
else
{
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (! hard_reg_set_empty_p (temp_hard_regset))
gcc_unreachable ();
}
#endif
}
ira_class_translate[cover_class] = cover_class;
}
/* For classes which are not fully covered by a cover class (in
other words covered by more one cover class), use the cheapest
cover class. */
for (cl = 0; cl < N_REG_CLASSES; cl++)
{
if (cl == NO_REGS || ira_class_translate[cl] != NO_REGS)
continue;
best_class = NO_REGS;
best_cost = INT_MAX;
for (i = 0; i < ira_reg_class_cover_size; i++)
{
cover_class = ira_reg_class_cover[i];
COPY_HARD_REG_SET (temp_hard_regset,
reg_class_contents[cover_class]);
AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (! hard_reg_set_empty_p (temp_hard_regset))
{
min_cost = INT_MAX;
for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
{
cost = (ira_memory_move_cost[mode][cl][0]
+ ira_memory_move_cost[mode][cl][1]);
if (min_cost > cost)
min_cost = cost;
}
if (best_class == NO_REGS || best_cost > min_cost)
{
best_class = cover_class;
best_cost = min_cost;
}
}
}
ira_class_translate[cl] = best_class;
}
}
/* Order numbers of cover classes in original target cover class
array, -1 for non-cover classes. This is only live during
reorder_important_classes. */
static int cover_class_order[N_REG_CLASSES];
/* The function used to sort the important classes. */
static int
comp_reg_classes_func (const void *v1p, const void *v2p)
{
enum reg_class cl1 = *(const enum reg_class *) v1p;
enum reg_class cl2 = *(const enum reg_class *) v2p;
int diff;
cl1 = ira_class_translate[cl1];
cl2 = ira_class_translate[cl2];
if (cl1 != NO_REGS && cl2 != NO_REGS
&& (diff = cover_class_order[cl1] - cover_class_order[cl2]) != 0)
return diff;
return (int) cl1 - (int) cl2;
}
/* Reorder important classes according to the order of their cover
classes. */
static void
reorder_important_classes (void)
{
int i;
for (i = 0; i < N_REG_CLASSES; i++)
cover_class_order[i] = -1;
for (i = 0; i < ira_reg_class_cover_size; i++)
cover_class_order[ira_reg_class_cover[i]] = i;
qsort (ira_important_classes, ira_important_classes_num,
sizeof (enum reg_class), comp_reg_classes_func);
}
/* Set up the above reg class relations. */
static void
setup_reg_class_relations (void)
{
int i, cl1, cl2, cl3;
HARD_REG_SET intersection_set, union_set, temp_set2;
bool important_class_p[N_REG_CLASSES];
memset (important_class_p, 0, sizeof (important_class_p));
for (i = 0; i < ira_important_classes_num; i++)
important_class_p[ira_important_classes[i]] = true;
for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++)
{
ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES;
for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++)
{
ira_reg_classes_intersect_p[cl1][cl2] = false;
ira_reg_class_intersect[cl1][cl2] = NO_REGS;
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]);
AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
if (hard_reg_set_empty_p (temp_hard_regset)
&& hard_reg_set_empty_p (temp_set2))
{
for (i = 0;; i++)
{
cl3 = reg_class_subclasses[cl1][i];
if (cl3 == LIM_REG_CLASSES)
break;
if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2],
(enum reg_class) cl3))
ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
}
ira_reg_class_union[cl1][cl2] = reg_class_subunion[cl1][cl2];
continue;
}
ira_reg_classes_intersect_p[cl1][cl2]
= hard_reg_set_intersect_p (temp_hard_regset, temp_set2);
if (important_class_p[cl1] && important_class_p[cl2]
&& hard_reg_set_subset_p (temp_hard_regset, temp_set2))
{
enum reg_class *p;
p = &ira_reg_class_super_classes[cl1][0];
while (*p != LIM_REG_CLASSES)
p++;
*p++ = (enum reg_class) cl2;
*p = LIM_REG_CLASSES;
}
ira_reg_class_union[cl1][cl2] = NO_REGS;
COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]);
AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]);
AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs);
COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]);
IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]);
AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs);
for (i = 0; i < ira_important_classes_num; i++)
{
cl3 = ira_important_classes[i];
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (hard_reg_set_subset_p (temp_hard_regset, intersection_set))
{
COPY_HARD_REG_SET
(temp_set2,
reg_class_contents[(int)
ira_reg_class_intersect[cl1][cl2]]);
AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2)
/* Ignore unavailable hard registers and prefer
smallest class for debugging purposes. */
|| (hard_reg_set_equal_p (temp_hard_regset, temp_set2)
&& hard_reg_set_subset_p
(reg_class_contents[cl3],
reg_class_contents
[(int) ira_reg_class_intersect[cl1][cl2]])))
ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
}
if (hard_reg_set_subset_p (temp_hard_regset, union_set))
{
COPY_HARD_REG_SET
(temp_set2,
reg_class_contents[(int) ira_reg_class_union[cl1][cl2]]);
AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
if (ira_reg_class_union[cl1][cl2] == NO_REGS
|| (hard_reg_set_subset_p (temp_set2, temp_hard_regset)
&& (! hard_reg_set_equal_p (temp_set2,
temp_hard_regset)
/* Ignore unavailable hard registers and
prefer smallest class for debugging
purposes. */
|| hard_reg_set_subset_p
(reg_class_contents[cl3],
reg_class_contents
[(int) ira_reg_class_union[cl1][cl2]]))))
ira_reg_class_union[cl1][cl2] = (enum reg_class) cl3;
}
}
}
}
}
/* Output all cover classes and the translation map into file F. */
static void
print_class_cover (FILE *f)
{
static const char *const reg_class_names[] = REG_CLASS_NAMES;
int i;