New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Error: unrecognized opcode csrw #1053
Comments
In the old ISA spec, the csr instructions are part of the base I instruction set. In the new ISA spec, the csr instructions are part of the zicsr extension. If -march=rv32imac doesn't work, then try -march=rv32imac_zicsr. Old toolchains won't accept zicsr though as it is new. So you may need to experiment to see what options your version of the assembler needs. You can get the assembler version by running "riscv64-unknown-elf-as --version". Worst case, you might need different arch options for gcc and gas if you have mismatched versions of them. |
We using GCC 11 and binutils 2.38 for riscv-gnu-toolchain, and they are using different default ISA spec version. I guess I should add an option for riscv-gnu-toolchain script to set the default ISA spec version :( |
Then I would suggest using a version of riscv-gnu-toolchain from before this change was made. |
Thank you for the quick reply @jim-wilson @kito-cheng. I will report this to WD. |
Kito merged in a patch to fix this, so the top of the riscv-gnu-toolchain git tree should handle this correctly now. |
Hi all,
I am trying to install the RISC-V GNU toolchain in order to compile for WD SweRV-EL2 core.
I followed the guidelines to install the toolchain (2022.03.25 version), opting for the multilib option.
After that, when I execute the following command to see the supported archs:
Then, I cloned the SweRV-EL2 RISC-V core, and try to run the hello_world simulation, the following error appeared when I build hello_world.o:
Did I forget something in the configuration stage?
Thank you in advance!
The text was updated successfully, but these errors were encountered: