ORI instruction ELF RUN exiting as unhandled exception when tried to write at x0

[bharishb]

ori x0, x17, 1 # icount 40

//ELF RUN
insn: 0x0000a0 --- _start -UNHANDLED EXTENSION: 35

I want to the limitations of ELF RUN simulator. Thanks

[TommyMurphyTM1234]

Please provide full details on how to reproduce this including details of the toolchain that you are using, where you obtained it from, how you are compiling your code, the code that you are compiling, the default arch/abi of your toolchain, the flags that you are passing when compiling, an objdump disassembly of your code etc.

Be aware that the only extensions supported by the GDB sim/run simulator seem to be I, M and A.

• https://github.com/bminor/binutils-gdb/blob/26c294bd1b8d95b421487294863eb1560b65580d/sim/riscv/sim-main.c#L998
• riscv32-unknown-elf-run exit issue #1186
• How to use riscv64-unknown-elf-run #1176

You might be better off using one of the other simulators available as mentioned in the linked issues.

[bharishb]

Hi, I am using the Base Instruction set rv32I. I use the following command to generate my trace. For 32I, I dont think we need to give arch/abi since they are the default.

riscv32-unknown-elf-run -t output.o 2> output.golden_run

//OBJDUMP
objdump.txt

[TommyMurphyTM1234]

You haven't said where you got the toolchain from, how it was built etc.

[bharishb]

https://github.com/riscv-collab/riscv-gnu-toolchain
Apologies I missed it. I took it from here. Followed the README steps

Git Versions of submodules.

[submodule "binutils"]
path = binutils
url = https://sourceware.org/git/binutils-gdb.git
branch = binutils-2_39-branch
[submodule "gcc"]
path = gcc
url = https://gcc.gnu.org/git/gcc.git
branch = releases/gcc-12.1.0
[submodule "glibc"]
path = glibc
url = https://sourceware.org/git/glibc.git
[submodule "dejagnu"]
path = dejagnu
url = https://git.savannah.gnu.org/git/dejagnu.git
branch = dejagnu-1.6.3
[submodule "newlib"]
path = newlib
url = https://sourceware.org/git/newlib-cygwin.git
branch = master
[submodule "gdb"]
path = gdb
url = https://sourceware.org/git/binutils-gdb.git
branch = gdb-12-branch
[submodule "qemu"]
path = qemu
url = https://gitlab.com/qemu-project/qemu.git
[submodule "musl"]
path = musl
url = git://git.musl-libc.org/musl
branch = master
[submodule "spike"]
path = spike
url = https://github.com/riscv-software-src/riscv-isa-sim.git
branch = master
[submodule "pk"]
path = pk
url = https://github.com/riscv-software-src/riscv-pk.git
branch = master

[TommyMurphyTM1234]

You still haven't provided the relevant info.
The git clone, configure and make commands used to build the toolchain.

[TommyMurphyTM1234]

Hi, I am using the Base Instruction set rv32I. I use the following command to generate my trace. For 32I, I dont think we need to give arch/abi since they are the default.

riscv32-unknown-elf-run -t output.o 2> output.golden_run

//OBJDUMP objdump.txt

Where did you get or how exactly did you build the toolchain?
What is your source code?
How are you compiling/linking it?
You need to provide full details a reproducible test case if you want assistance.
Otherwise the issue will be closed as invalid.
As disassembly of your compiled and linked program is of no use on its own.

[bharishb]

Hi,
I think this issue should be tool chain build independent atleast any 32i build should give it. I am trying to write into hardwired register x0 with the help of ORI instruction. I have literally nothing in my code
FAIL at highlighted instructiion by gdb simulator riscv32-unknown-elf-run by throwing unhandled exception.
When I replace x0 destination with x1. it passes. So do the toolchain expects to throw error or it silently ignores ? When I replace 0x101 with 0x2, it passes. So handling X0 write is not consistent ??
.global _start
_start:
ori x0,x0,0x0101
j exit

exit:
li a7,93
ecall

PASS output of elf-run
insn: 0x000000 --- _start -ori ra, zero, 257; // ra = zero | 0x101
2 insn: 0x000004 --- _start -jal zero, 4;
3 insn: 0x000008 --- exit -addi a7, zero, 0x5d; // a7 = zero + 0x5d
4 insn: 0x00000c --- exit -ecall;

FAIL output
insn: 0x000000 --- _start -UNHANDLED EXTENSION: 35

2 program stopped with signal 4 (Illegal instruction).
PASS OUTPUT when ored with 0x2
1 insn: 0x000000 --- _start -ori zero, zero, 2; // zero = zero | 0x2
2 insn: 0x000004 --- _start -jal zero, 4;
3 insn: 0x000008 --- exit -addi a7, zero, 0x5d; // a7 = zero + 0x5d
4 insn: 0x00000c --- exit -ecall;

Git Clone Command :
git clone https://github.com/riscv/riscv-gnu-toolchain --recursive
Configure Command : .
/configure --prefix=/home/batchu/riscv_tool_chain_git --with-arch=rv32i --with-abi=ilp32
Build Command ::
make
Compile :
riscv32-unknown-elf-gcc -nostartfiles -Wl,-T,./riscv32.ld $1.s -o output.o
Simulate
riscv32-unknown-elf-run -t output.o 2> output.golden_run
riscv32.ld.txt

[TommyMurphyTM1234]

.global _start _start: ori x0,x0,0x0101 j exit

exit: li a7,93 ecall

PASS output of elf-run insn: 0x000000 --- _start -ori ra, zero, 257; // ra = zero | 0x101 2 insn: 0x000004 --- _start -jal zero, 4; 3 insn: 0x000008 --- exit -addi a7, zero, 0x5d; // a7 = zero + 0x5d 4 insn: 0x00000c --- exit -ecall;

FAIL output insn: 0x000000 --- _start -UNHANDLED EXTENSION: 35

I don't understand this - you seem to be getting both a pass and a fail result with the same code?

2 program stopped with signal 4 (Illegal instruction). PASS OUTPUT when ored with 0x2 1 insn: 0x000000 --- _start -ori zero, zero, 2; // zero = zero | 0x2 2 insn: 0x000004 --- _start -jal zero, 4; 3 insn: 0x000008 --- exit -addi a7, zero, 0x5d; // a7 = zero + 0x5d 4 insn: 0x00000c --- exit -ecall;

And the same here?

I seem to get the same error/fail result no matter what ori x0, x0, imm instruction I use.

Looks like a bug alright - it seems to be decoding such instructions as the wrong class - this:

• https://github.com/bminor/binutils-gdb/blob/master/include/opcode/riscv.h#L404

instead of this:

• https://github.com/bminor/binutils-gdb/blob/master/include/opcode/riscv.h#L369

You probably need to log this upstream or sumbit a fix there if you have one:

• https://www.sourceware.org/gdb/bugs/
• https://www.sourceware.org/gdb/contribute/

But, bear in mind, as far as I know, there is nobody actively working on maintaining the RISC-V port of the GDB simulator.
As such, you might be better advised to use another, more reliable and better maintained, simulator,
E.g. Spike, QEMU, Renode etc.

[bharishb]

ohh Thanks.. I will start to migration to other simulators then ,.. Thanks for the help :)

[TommyMurphyTM1234]

Logged upstream now

• https://sourceware.org/bugzilla/show_bug.cgi?id=30494

so I am closing this issue.

[TommyMurphyTM1234]

Logged upstream now

• https://sourceware.org/bugzilla/show_bug.cgi?id=30494

so I am closing this issue.

Somebody else pointed out that it should probably be logged against binutils/libopcodes and not gdb/sim so I logged it here instead:

• https://sourceware.org/bugzilla/show_bug.cgi?id=30495

[Temperature-block]

I have updated patch on bugzilla https://sourceware.org/bugzilla/show_bug.cgi?id=30495