/
misalign-lw-01.S
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misalign-lw-01.S
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// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version : 0.4.1
// timestamp : Tue Dec 15 15:45:45 2020 GMT
// usage : riscv_ctg \
// -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv32i_priv.cgf') \
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the lw instruction of the RISC-V I extension for the misalign-lw covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zicsr")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True; def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",misalign-lw)
RVTEST_CASE(1,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",misalign-lw)
RVTEST_SIGBASE( x1,signature_x1_1)
inst_0:
// ea_align == 1,
// opcode:lw op1:x10; dest:x11; immval:0x0; align:1
TEST_LOAD(x1,x2,0,x10,x11,0x0,0,lw,1)
inst_1:
// ea_align == 2,
// opcode:lw op1:x10; dest:x11; immval:0x100; align:2
TEST_LOAD(x1,x2,0,x10,x11,0x100,4,lw,2)
inst_2:
// ea_align == 3,
// opcode:lw op1:x10; dest:x11; immval:-0x800; align:3
TEST_LOAD(x1,x2,0,x10,x11,-0x800,8,lw,3)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*(XLEN/32),4,0xdeadbeef
signature_x1_1:
.fill 3*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END