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We don't currently have an asm constraint to require an even register (for an input or output in a register pair) and I don't believe there's a cross-target constraint already defined. We should likely decide on one. This could be used with the proposed zacas extension (amocas.d on rv32 or amocas.q on rv64), for zdinx, and IIRC the P extension.
The text was updated successfully, but these errors were encountered:
This implements the v1.0-rc1 draft extension.
amocas.d on RV32 and amocas.q have the restriction that rd and rs2 must
be even registers. I've opted to implement this restriction in
RISCVAsmParser::validateInstruction even though for codegen we'll need a
new register class and can then remove this validation. This also
sidesteps, for now, the issue of amocas.d being different on rv32 vs
rv64.
See <riscv-non-isa/riscv-c-api-doc#37> for the
issue of needing an agreed asm register constraint for register pairs.
Differential Revision: https://reviews.llvm.org/D149248
We don't currently have an asm constraint to require an even register (for an input or output in a register pair) and I don't believe there's a cross-target constraint already defined. We should likely decide on one. This could be used with the proposed zacas extension (amocas.d on rv32 or amocas.q on rv64), for zdinx, and IIRC the P extension.
The text was updated successfully, but these errors were encountered: