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Note
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Standard extensions are merged into riscv/riscv-isa-manual after ratification. There is an on-going pull request 26 for the "V" extension to be merged. At this moment this intrinsics specification still references the frozen draft 0. This reference will be updated in the future once the pull request has been merged.
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4Section 3.4.1 (Vector selected element width vsew[2:0]) in the specification 0
5Section 3.4.2 (Vector Register Grouping (vlmul[2:0]`)) in the specification 0
6Section 3.4.3 (Vector Tail Agnostic and Vector Mask Agnostic vta and vma) in the specification 0
7Section 5.3 (Vector Masking) in the specification 0
8Section 3.8 (Vector Fixed-Point Rounding Mode Register vxrm) in the specification 0
11Section 3.5 (Vector Length Register) in the specification 0
12Section 3.4.2 in the specification 0
13Section 11.13, 11.14, 13.6, 13.7 in the specification 0
14Section 4.5 (Mask Register Layout) in the specification 0
15Section 7.5 in the specification 0
16Section 7.8 in the specification 0
17Section 5.2 (Vector Operands) in the specification 0
18Section 6 (Configuration-Setting Instructions) in the specification 0
19Section 18 (Standrad Vector Extensions) in the specification 0
20Section 18.2 (Zve*: Vector Extensions for Embedded Processors) in the specification 0
21Section 12 (Vector Fixed-Point Arithmetic Instructions) in the specification 0
22Section 3.9 (3.9. Vector Fixed-Point Saturation Flag vxsat) in the specification 0
23Section 13 (Vector Floating-Point Instructions) in the specification 0
24Section 16.3.1 (Vector Slideup Instructions) in the specification 0
25Section 3.7 (Vector Start Index CSR vstart) in the specification 0
27Section 6.3 (Constraints on Setting vl) in the specficiation 0
28Section 6.4 (Example of stripmining and changes to SEW) in the specification 0
29Section 3.6 (Vector Byte Length vlenb) in the specification 0
30Section 16.6 (Whole Vector Register Move) in the specification 0