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RISC-V Semihosting

License

Copyright © 2020 Krste Asanovic, Palmer Dabbelt, Liviu Ionescu, Keith Packard, Megan Wachs

This document is released under a Creative Commons Attribution 4.0 International License.

Abstract

Semihosting is a technique where an application running in a debug or simulation environment can access elements of the system hosting the debugger or simulator including console, file system, time and other functions. This allows for diagnostics, interaction and measurement of a target system without requiring significant infrastructure to exist in that target environment.

1. RISC-V Semihosting

RISC-V semihosting borrows from the design of the ARM semihosting mechanism to minimize the development effort required. The RISC-V semihosting is based on the "Semihosting for AArch32 and AArch64" specification available here:

https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst

Referring to Chapter Three in that document, the following extensions are needed to provide RISC-V support.

1.1. Semihosting Trap Instruction Sequence

Semihosting operations are requested using a sequence of instructions including EBREAK. Because the RISC-V base ISA does not provide more than one EBREAK instruction, RISC-V semihosting uses a special sequence of instructions to distinguish a semihosting EBREAK from a debugger inserted EBREAK. RISC-V Semihosting Trap Sequence shows the instruction sequence used to invoke a Semihosting operation.

RISC-V Semihosting Trap Sequence
slli x0, x0, 0x1f       # 0x01f01013    Entry NOP
ebreak                  # 0x00100073    Break to debugger
srai x0, x0, 7          # 0x40705013    NOP encoding the semihosting call number 7

These three instructions must be 32-bit-wide instructions, they may not be compressed 16-bit instructions. This same sequence is used on all RISC-V architectures. On systems with paging support, this sequence must not cross a page boundary as the semihosting system must be able to check for the semihosting sequence without needing data from potentially missing pages. RISC-V Semihosting Trap Function shows how this can be done by placing the sequence in a separate function and aligning that to prevent that from spanning a page boundary.

RISC-V Semihosting Trap Function
        .option norvc
        .text
        .balign 16
        .global sys_semihost
        .type sys_semihost @function
sys_semihost:
        slli zero, zero, 0x1f
        ebreak
        srai zero, zero, 0x7
        ret

1.2. Semihosting Register Definitions

RISC-V Registers and field size shows the specific registers that are used, and the size of the fields in the data block, which depend on whether the caller is 32-bit or 64-bit.

Table 1. RISC-V Registers and field size

32-bit

64-bit

OPERATION NUMBER REGISTER

A0

A0

PARAMETER REGISTER

A1

A1

RETURN REGISTER

A0

A0

Data block field size

32 bits

64 bits