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riscv-tdep.c
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riscv-tdep.c
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/* Target-dependent code for the RISC-V architecture, for GDB.
Copyright (C) 1988-2015 Free Software Foundation, Inc.
Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
and by Todd Snyder <todd@bluespec.com>
and by Mike Frysinger <vapier@gentoo.org>.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "frame.h"
#include "inferior.h"
#include "symtab.h"
#include "value.h"
#include "gdbcmd.h"
#include "language.h"
#include "gdbcore.h"
#include "symfile.h"
#include "objfiles.h"
#include "gdbtypes.h"
#include "target.h"
#include "arch-utils.h"
#include "regcache.h"
#include "osabi.h"
#include "riscv-tdep.h"
#include "block.h"
#include "reggroups.h"
#include "opcode/riscv.h"
#include "elf/riscv.h"
#include "elf-bfd.h"
#include "symcat.h"
#include "sim-regno.h"
#include "gdb/sim-riscv.h"
#include "dis-asm.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "trad-frame.h"
#include "infcall.h"
#include "floatformat.h"
#include "remote.h"
#include "target-descriptions.h"
#include "dwarf2-frame.h"
#include "user-regs.h"
#include "valprint.h"
#include "common-defs.h"
#include "opcode/riscv-opc.h"
#include <algorithm>
#include <map>
#define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
static inline bool is_ ## INSN_NAME ## _insn (long insn) \
{ \
return (insn & INSN_MASK) == INSN_MATCH; \
}
#include "opcode/riscv-opc.h"
#undef DECLARE_INSN
struct riscv_frame_cache
{
CORE_ADDR base;
struct trad_frame_saved_reg *saved_regs;
};
struct riscv_reg_info
{
int number;
// The first name in this list is the one that is considered the canonical
// name of the register. This is both the name used internally when possible
// as well as the name the user sees. (gdb does not have a concept of
// separating those two.)
std::vector<const char*> names;
// We can't debug a target that doesn't have this register.
bool required;
// This register must be saved/restored by gdb around function calls.
bool save_restore;
const char *feature_name;
struct reggroup *group;
};
static std::vector<struct riscv_reg_info> riscv_reg_info = {
{RISCV_ZERO_REGNUM, {"zero", "x0"}, false, false, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_RA_REGNUM, {"ra", "x1"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_SP_REGNUM, {"sp", "x2"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_GP_REGNUM, {"gp", "x3"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_TP_REGNUM, {"tp", "x4"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_T0_REGNUM, {"t0", "x5"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_T1_REGNUM, {"t1", "x6"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_T2_REGNUM, {"t2", "x7"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_FP_REGNUM, {"s0", "x8", "fp"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S1_REGNUM, {"s1", "x9"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_A0_REGNUM, {"a0", "x10"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_A1_REGNUM, {"a1", "x11"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_A2_REGNUM, {"a2", "x12"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_A3_REGNUM, {"a3", "x13"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_A4_REGNUM, {"a4", "x14"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_A5_REGNUM, {"a5", "x15"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_A6_REGNUM, {"a6", "x16"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_A7_REGNUM, {"a7", "x17"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S2_REGNUM, {"s2", "x18"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S3_REGNUM, {"s3", "x19"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S4_REGNUM, {"s4", "x20"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S5_REGNUM, {"s5", "x21"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S6_REGNUM, {"s6", "x22"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S7_REGNUM, {"s7", "x23"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S8_REGNUM, {"s8", "x24"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S9_REGNUM, {"s9", "x25"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S10_REGNUM, {"s10", "x26"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_S11_REGNUM, {"s11", "x27"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_T3_REGNUM, {"t3", "x28"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_T4_REGNUM, {"t4", "x29"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_T5_REGNUM, {"t5", "x30"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_T6_REGNUM, {"t6", "x31"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_PC_REGNUM, {"pc"}, true, true, "org.gnu.gdb.riscv.cpu", general_reggroup},
{RISCV_FT0_REGNUM, {"f0", "ft0"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT1_REGNUM, {"f1", "ft1"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT2_REGNUM, {"f2", "ft2"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT3_REGNUM, {"f3", "ft3"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT4_REGNUM, {"f4", "ft4"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT5_REGNUM, {"f5", "ft5"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT6_REGNUM, {"f6", "ft6"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT7_REGNUM, {"f7", "ft7"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS0_REGNUM, {"f8", "fs0"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS1_REGNUM, {"f9", "fs1"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FA0_REGNUM, {"f10", "fa0"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FA1_REGNUM, {"f11", "fa1"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FA2_REGNUM, {"f12", "fa2"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FA3_REGNUM, {"f13", "fa3"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FA4_REGNUM, {"f14", "fa4"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FA5_REGNUM, {"f15", "fa5"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FA6_REGNUM, {"f16", "fa6"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FA7_REGNUM, {"f17", "fa7"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS2_REGNUM, {"f18", "fs2"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS3_REGNUM, {"f19", "fs3"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS4_REGNUM, {"f20", "fs4"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS5_REGNUM, {"f21", "fs5"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS6_REGNUM, {"f22", "fs6"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS7_REGNUM, {"f23", "fs7"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS8_REGNUM, {"f24", "fs8"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS9_REGNUM, {"f25", "fs9"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS10_REGNUM, {"f26", "fs10"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FS11_REGNUM, {"f27", "fs11"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT8_REGNUM, {"f28", "ft8"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT9_REGNUM, {"f29", "ft9"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT10_REGNUM, {"f30", "ft10"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_FT11_REGNUM, {"f31", "ft11"}, false, true, "org.gnu.gdb.riscv.fpu", float_reggroup},
{RISCV_PRIV_REGNUM, {"priv"}, false, false, "org.gnu.gdb.riscv.virtual", general_reggroup},
};
// Map from fixed register number to register's info.
static std::map<int, struct riscv_reg_info *> riscv_reg_map;
struct register_alias
{
const char *name;
int regnum;
};
/* Controls whether the debugger should step over hardware watchpoints before
checking if the watched variable has changed. If true, then the debugger
will step over the watchpoint. */
static int riscv_have_nonsteppable_watchpoint = 1;
/* The set callback for 'set riscv have-nonsteppable-watchpoint'. */
static void
set_have_nonsteppable_watchpoint (char *args, int from_tty,
struct cmd_list_element *c)
{
struct gdbarch *gdbarch = target_gdbarch ();
set_gdbarch_have_nonsteppable_watchpoint(gdbarch,
riscv_have_nonsteppable_watchpoint);
}
/* The show callback for 'show riscv have-nonsteppable-watchpoint'. */
static void
show_have_nonsteppable_watchpoint (struct ui_file *file, int from_tty,
struct cmd_list_element *c,
const char *value)
{
fprintf_filtered (file,
_("Debugger must step over hardware watchpoints is set to "
"%s.\n"), value);
}
static enum auto_boolean use_compressed_breakpoints;
/*
static void
show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
struct cmd_list_element *c,
const char *value)
{
fprintf_filtered (file,
_("Debugger's behavior regarding "
"compressed breakpoints is %s.\n"),
value);
}
*/
static struct cmd_list_element *setriscvcmdlist = NULL;
static struct cmd_list_element *showriscvcmdlist = NULL;
static void
show_riscv_command (char *args, int from_tty)
{
help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
}
static void
set_riscv_command (char *args, int from_tty)
{
printf_unfiltered
("\"set riscv\" must be followed by an appropriate subcommand.\n");
help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
}
static uint32_t
cached_misa ()
{
static bool read = false;
static uint32_t value = 0;
if (!read) {
struct frame_info *frame = get_current_frame ();
TRY
{
value = get_frame_register_unsigned (frame, RISCV_CSR_MISA_REGNUM);
}
CATCH (ex, RETURN_MASK_ERROR)
{
// In old cores, $misa might live at 0xf10
value = get_frame_register_unsigned (frame,
RISCV_CSR_MISA_REGNUM - 0x301 + 0xf10);
}
END_CATCH
read = true;
}
return value;
}
/* Implement the breakpoint_kind_from_pc gdbarch method. */
static int
riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
{
if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) {
if (gdbarch_tdep (gdbarch)->supports_compressed_isa == AUTO_BOOLEAN_AUTO)
{
/* TODO: Because we try to read misa, it is not possible to set a
breakpoint before connecting to a live target. A suggested workaround is
to look at the ELF file in this case. */
uint32_t misa = cached_misa();
if (misa & (1<<2))
gdbarch_tdep (gdbarch)->supports_compressed_isa = AUTO_BOOLEAN_TRUE;
else
gdbarch_tdep (gdbarch)->supports_compressed_isa = AUTO_BOOLEAN_FALSE;
}
if (gdbarch_tdep (gdbarch)->supports_compressed_isa == AUTO_BOOLEAN_TRUE)
return 2;
else
return 4;
} else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE) {
return 2;
} else {
return 4;
}
}
/* Implement the sw_breakpoint_from_kind gdbarch method. */
static const gdb_byte *
riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
{
static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
*size = kind;
switch (kind)
{
case 2:
return c_ebreak;
case 4:
return ebreak;
default:
gdb_assert(0);
}
}
static struct value *
value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
{
const int *reg_p = (const int *)baton;
return value_of_register (*reg_p, frame);
}
/* Implement the register_name gdbarch method. */
static const char *
riscv_register_name (struct gdbarch *gdbarch,
int regnum)
{
int i;
static char buf[20];
auto match = riscv_reg_map.find(regnum);
if (match == riscv_reg_map.end())
return NULL;
return match->second->names[0];
}
/* Reads a function return value of type TYPE. */
static void
riscv_extract_return_value (struct type *type,
struct regcache *regs,
gdb_byte *dst,
int regnum)
{
struct gdbarch *gdbarch = get_regcache_arch (regs);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int regsize = riscv_isa_regsize (gdbarch);
bfd_byte *valbuf = dst;
int len = TYPE_LENGTH (type);
int st_len = std::min (regsize, len);
ULONGEST tmp;
gdb_assert (len <= 2 * regsize);
while (len > 0)
{
regcache_cooked_read_unsigned (regs, regnum++, &tmp);
store_unsigned_integer (valbuf, st_len, byte_order, tmp);
len -= regsize;
valbuf += regsize;
}
}
/* Write into appropriate registers a function return value of type
TYPE, given in virtual format. */
static void
riscv_store_return_value (struct type *type,
struct regcache *regs,
const gdb_byte *src,
int regnum)
{
struct gdbarch *gdbarch = get_regcache_arch (regs);
int regsize = riscv_isa_regsize (gdbarch);
const bfd_byte *valbuf = src;
/* Integral values greater than one word are stored in consecutive
registers starting with R0. This will always be a multiple of
the register size. */
int len = TYPE_LENGTH (type);
gdb_assert (len <= 2 * regsize);
while (len > 0)
{
regcache_cooked_write (regs, regnum++, valbuf);
len -= regsize;
valbuf += regsize;
}
}
/* Implement the return_value gdbarch method. */
static enum return_value_convention
riscv_return_value (struct gdbarch *gdbarch,
struct value *function,
struct type *type,
struct regcache *regcache,
gdb_byte *readbuf,
const gdb_byte *writebuf)
{
enum type_code rv_type = TYPE_CODE (type);
unsigned int rv_size = TYPE_LENGTH (type);
int fp, regnum;
ULONGEST tmp;
/* Paragraph on return values taken from RISC-V specification (post v2.0):
Values are returned from functions in integer registers a0 and a1 and
floating-point registers fa0 and fa1. Floating-point values are returned
in floating-point registers only if they are primitives or members of a
struct consisting of only one or two floating-point values. Other return
values that fit into two pointer-words are returned in a0 and a1. Larger
return values are passed entirely in memory; the caller allocates this
memory region and passes a pointer to it as an implicit first parameter
to the callee. */
/* Deal with struct/unions first that are passed via memory. */
if (rv_size > 2 * riscv_isa_regsize (gdbarch))
{
if (readbuf || writebuf)
regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, &tmp);
if (readbuf)
read_memory (tmp, readbuf, rv_size);
if (writebuf)
write_memory (tmp, writebuf, rv_size);
return RETURN_VALUE_ABI_RETURNS_ADDRESS;
}
/* Are we dealing with a floating point value? */
fp = 0;
if (rv_type == TYPE_CODE_FLT)
fp = 1;
else if (rv_type == TYPE_CODE_STRUCT || rv_type == TYPE_CODE_UNION)
{
unsigned int rv_fields = TYPE_NFIELDS (type);
if (rv_fields == 1)
{
struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
fp = 1;
}
else if (rv_fields == 2)
{
struct type *fieldtype0 = TYPE_FIELD_TYPE (type, 0);
struct type *fieldtype1 = TYPE_FIELD_TYPE (type, 1);
if (TYPE_CODE (check_typedef (fieldtype0)) == TYPE_CODE_FLT
&& TYPE_CODE (check_typedef (fieldtype1)) == TYPE_CODE_FLT)
fp = 1;
}
}
/* Handle return value in a register. */
regnum = fp ? RISCV_FA0_REGNUM : RISCV_A0_REGNUM;
if (readbuf)
riscv_extract_return_value (type, regcache, readbuf, regnum);
if (writebuf)
riscv_store_return_value (type, regcache, writebuf, regnum);
return RETURN_VALUE_REGISTER_CONVENTION;
}
/* Implement the register_type gdbarch method. */
static struct type *
riscv_register_type (struct gdbarch *gdbarch,
int regnum)
{
int regsize = riscv_isa_regsize (gdbarch);
if (regnum < RISCV_FIRST_FP_REGNUM)
{
/*
* GPRs and especially the PC are listed as unsigned so that gdb can
* interpret them as addresses without any problems. Specifically, if a
* user runs "x/i $pc" then they should see the instruction at the PC.
* But on a 32-bit system, with a signed PC of eg. 0x8000_0000, gdb will
* internally sign extend the value and then attempt to read from
* 0xffff_ffff_8000_0000, which it then concludes it can't read.
*/
switch (regsize)
{
case 4:
return builtin_type (gdbarch)->builtin_uint32;
case 8:
return builtin_type (gdbarch)->builtin_uint64;
case 16:
return builtin_type (gdbarch)->builtin_uint128;
default:
internal_error (__FILE__, __LINE__,
_("unknown isa regsize %i"), regsize);
}
}
else if (regnum <= RISCV_LAST_FP_REGNUM)
{
switch (regsize)
{
case 4:
return builtin_type (gdbarch)->builtin_float;
case 8:
case 16:
return builtin_type (gdbarch)->builtin_double;
default:
internal_error (__FILE__, __LINE__,
_("unknown isa regsize %i"), regsize);
}
}
else if (regnum == RISCV_PRIV_REGNUM)
{
return builtin_type (gdbarch)->builtin_int8;
}
else
{
if (regnum == RISCV_CSR_FFLAGS_REGNUM
|| regnum == RISCV_CSR_FRM_REGNUM
|| regnum == RISCV_CSR_FCSR_REGNUM)
return builtin_type (gdbarch)->builtin_int32;
switch (regsize)
{
case 4:
return builtin_type (gdbarch)->builtin_int32;
case 8:
return builtin_type (gdbarch)->builtin_int64;
case 16:
return builtin_type (gdbarch)->builtin_int128;
default:
internal_error (__FILE__, __LINE__,
_("unknown isa regsize %i"), regsize);
}
}
}
static void
riscv_print_fp_register (struct ui_file *file, struct frame_info *frame,
int regnum)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
struct value_print_options opts;
const char *regname;
value *val = NULL;
TRY
{
val = get_frame_register_value(frame, regnum);
}
CATCH (ex, RETURN_MASK_ERROR)
{
fprintf_filtered (file, "%-15s%s",
gdbarch_register_name (gdbarch, regnum),
ex.message);
return;
}
fprintf_filtered (file, "%-15s", gdbarch_register_name (gdbarch, regnum));
get_formatted_print_options (&opts, 'f');
val_print_scalar_formatted (value_type (val),
value_embedded_offset (val),
val,
&opts, 0, file);
}
static void
riscv_print_register_formatted (struct ui_file *file, struct frame_info *frame,
int regnum)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
gdb_byte raw_buffer[MAX_REGISTER_SIZE];
struct value_print_options opts;
if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
riscv_print_fp_register (file, frame, regnum);
else
{
/* Integer type. */
int offset, size;
unsigned long long d;
int prefer_alias = regnum >= RISCV_FIRST_CSR_REGNUM;
int read_result = -1;
TRY
{
read_result = deprecated_frame_register_read (frame, regnum, raw_buffer);
}
CATCH (ex, RETURN_MASK_ERROR)
{
fprintf_filtered (file, "%-15s%s\n",
gdbarch_register_name (gdbarch, regnum),
ex.message);
return;
}
if (!read_result)
{
fprintf_filtered (file, "%-15s[Invalid]\n",
gdbarch_register_name (gdbarch, regnum));
return;
}
fprintf_filtered (file, "%-15s", gdbarch_register_name (gdbarch, regnum));
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
offset = register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
else
offset = 0;
size = register_size (gdbarch, regnum);
get_formatted_print_options (&opts, 'x');
print_scalar_formatted (raw_buffer + offset,
register_type (gdbarch, regnum), &opts,
size == 8 ? 'g' : 'w', file);
fprintf_filtered (file, "\t");
if (size == 4 && riscv_isa_regsize (gdbarch) == 8)
fprintf_filtered (file, "\t");
if (regnum == RISCV_CSR_MSTATUS_REGNUM)
{
if (size == 4)
d = unpack_long (builtin_type (gdbarch)->builtin_uint32, raw_buffer);
else if (size == 8)
d = unpack_long (builtin_type (gdbarch)->builtin_uint64, raw_buffer);
else
internal_error (__FILE__, __LINE__, _("unknown size for mstatus"));
unsigned xlen = size * 4;
fprintf_filtered (file, "SD:%X", (int)((d >> (xlen-1)) & 0x1));
if (size > 4)
fprintf_filtered (file, " SXL:%X UXL:%X",
(int)((d >> 34) & 3), (int)((d >> 32) & 3));
fprintf_filtered (file,
" TSR:%X TW:%X TVM:%X MXR:%X SUM:%X MPRV:%X XS:%X "
"FS:%X MPP:%X SPP:%X MPIE:%X SPIE:%X UPIE:%X MIE:%X "
"SIE:%X UIE:%X",
(int)((d >> 22) & 0x1f),
(int)((d >> 21) & 0x1),
(int)((d >> 20) & 0x1),
(int)((d >> 19) & 0x1),
(int)((d >> 18) & 0x1),
(int)((d >> 17) & 0x1),
(int)((d >> 15) & 0x3),
(int)((d >> 13) & 0x3),
(int)((d >> 11) & 0x3),
(int)((d >> 8) & 0x1),
(int)((d >> 7) & 0x1),
(int)((d >> 5) & 0x1),
(int)((d >> 4) & 0x1),
(int)((d >> 3) & 0x1),
(int)((d >> 1) & 0x1),
(int)((d >> 0) & 0x1));
}
else if (regnum == RISCV_CSR_MISA_REGNUM)
{
int base;
if (size == 4) {
d = unpack_long (builtin_type (gdbarch)->builtin_uint32, raw_buffer);
base = d >> 30;
} else if (size == 8) {
d = unpack_long (builtin_type (gdbarch)->builtin_uint64, raw_buffer);
base = d >> 62;
} else {
internal_error (__FILE__, __LINE__, _("unknown size for misa"));
}
unsigned xlen = 16;
for (; base > 0; base--) {
xlen *= 2;
}
fprintf_filtered (file, "RV%d", xlen);
for (unsigned i = 0; i < 26; i++) {
if (d & (1<<i)) {
fprintf_filtered (file, "%c", 'A' + i);
}
}
}
else if (regnum == RISCV_CSR_FCSR_REGNUM
|| regnum == RISCV_CSR_FFLAGS_REGNUM
|| regnum == RISCV_CSR_FRM_REGNUM)
{
d = unpack_long (builtin_type (gdbarch)->builtin_int32, raw_buffer);
if (regnum != RISCV_CSR_FRM_REGNUM)
fprintf_filtered (file, "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d ",
(int)((d >> 5) & 0x7),
(int)((d >> 4) & 0x1),
(int)((d >> 3) & 0x1),
(int)((d >> 2) & 0x1),
(int)((d >> 1) & 0x1),
(int)((d >> 0) & 0x1));
if (regnum != RISCV_CSR_FFLAGS_REGNUM)
{
static const char * const sfrm[] = {
"RNE (round to nearest; ties to even)",
"RTZ (Round towards zero)",
"RDN (Round down towards -∞)",
"RUP (Round up towards +∞)",
"RMM (Round to nearest; tiest to max magnitude)",
"INVALID[5]",
"INVALID[6]",
"dynamic rounding mode",
};
int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) ? (d >> 5) : d) & 0x3;
fprintf_filtered (file, "FRM:%i [%s]", frm, sfrm[frm]);
}
}
else if (regnum == RISCV_PRIV_REGNUM)
{
uint8_t priv = raw_buffer[0];
if (priv >= 0 && priv < 4)
{
static const char * const sprv[] = {
"User/Application",
"Supervisor",
"Hypervisor",
"Machine"
};
fprintf_filtered (file, "prv:%d [%s]", priv, sprv[priv]);
}
else
{
fprintf_filtered (file, "prv:%d [INVALID]", priv);
}
}
else
{
get_formatted_print_options (&opts, 'd');
print_scalar_formatted (raw_buffer + offset,
register_type (gdbarch, regnum),
&opts, 0, file);
}
}
fprintf_filtered (file, "\n");
}
/* Implement the register_reggroup_p gdbarch method.
* This is only called when there is no target description. */
static int
riscv_register_reggroup_p (struct gdbarch *gdbarch,
int regnum,
struct reggroup *reggroup)
{
auto match = riscv_reg_map.find(regnum);
if (match == riscv_reg_map.end())
return 0;
struct riscv_reg_info *reg = match->second;
if (reggroup == all_reggroup)
return 1;
if (reggroup == restore_reggroup || reggroup == save_reggroup)
{
if (reg->number >= RISCV_FIRST_FP_REGNUM && reg->number
<= RISCV_LAST_FP_REGNUM)
return (cached_misa() & ((1<<('F'-'A')) | (1<<('D'-'A')) |
(1<<('Q'-'A')))) ? 1 : 0;
return reg->save_restore;
}
return reg->group == reggroup;
}
/* Implement the print_registers_info gdbarch method. */
static void
riscv_print_registers_info (struct gdbarch *gdbarch,
struct ui_file *file,
struct frame_info *frame,
int regnum,
int all)
{
/* Use by 'info all-registers'. */
struct reggroup *reggroup;
if (regnum != -1)
{
/* Print one specified register.
* gdb might ask us to print a register that we don't know about, because
* it's in the target description. That still works, because we can ask
* gdb to give us register name and contents by number. */
if (NULL == gdbarch_register_name (gdbarch, regnum))
error (_("Not a valid register for the current processor type"));
riscv_print_register_formatted (file, frame, regnum);
return;
}
if (all)
reggroup = all_reggroup;
else
reggroup = general_reggroup;
for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
{
/* Zero never changes, so might as well hide by default. */
if (regnum == RISCV_ZERO_REGNUM && !all)
continue;
if (gdbarch_register_reggroup_p(gdbarch, regnum, reggroup))
riscv_print_register_formatted (file, frame, regnum);
}
}
static ULONGEST
riscv_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr)
{
enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
gdb_byte buf[8];
int instlen, status;
/* All insns are at least 16 bits. */
status = target_read_memory (addr, buf, 2);
if (status)
memory_error (TARGET_XFER_E_IO, addr);
/* If we need more, grab it now. */
instlen = riscv_insn_length (buf[0]);
if (instlen > sizeof (buf))
internal_error (__FILE__, __LINE__, _("%s: riscv_insn_length returned %i"),
__func__, instlen);
else if (instlen > 2)
{
status = target_read_memory (addr + 2, buf + 2, instlen - 2);
if (status)
memory_error (TARGET_XFER_E_IO, addr + 2);
}
return extract_unsigned_integer (buf, instlen, byte_order);
}
static void
set_reg_offset (struct gdbarch *gdbarch, struct riscv_frame_cache *this_cache,
int regnum, CORE_ADDR offset)
{
if (this_cache != NULL && this_cache->saved_regs[regnum].addr == -1)
this_cache->saved_regs[regnum].addr = offset;
}
static void
reset_saved_regs (struct gdbarch *gdbarch, struct riscv_frame_cache *this_cache)
{
const int num_regs = gdbarch_num_regs (gdbarch);
int i;
if (this_cache == NULL || this_cache->saved_regs == NULL)
return;
for (i = 0; i < num_regs; ++i)
this_cache->saved_regs[i].addr = 0;
}
static int riscv_decode_register_index(unsigned long opcode, int offset)
{
return (opcode >> offset) & 0x1F;
}
static CORE_ADDR
riscv_scan_prologue (struct gdbarch *gdbarch,
CORE_ADDR start_pc, CORE_ADDR limit_pc,
struct frame_info *this_frame,
struct riscv_frame_cache *this_cache)
{
CORE_ADDR cur_pc;
CORE_ADDR frame_addr = 0;
CORE_ADDR sp;
long frame_offset;
int frame_reg = RISCV_SP_REGNUM;
CORE_ADDR end_prologue_addr = 0;
int seen_sp_adjust = 0;
int load_immediate_bytes = 0;
/* Can be called when there's no process, and hence when there's no THIS_FRAME. */
if (this_frame != NULL)
sp = get_frame_register_signed (this_frame, RISCV_SP_REGNUM);
else
sp = 0;
if (limit_pc > start_pc + 200)
limit_pc = start_pc + 200;
restart:
frame_offset = 0;
/* TODO: Handle compressed extensions. */
for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += 4)
{
ULONGEST inst;
unsigned long opcode;
int reg, rs1, imm12, rs2, offset12, funct3;
/* Fetch the instruction. */
inst = riscv_fetch_instruction (gdbarch, cur_pc);
/* Decode the instruction. These offsets are defined in the RISC-V ISA
* manual. */
reg = riscv_decode_register_index(inst, 7);
rs1 = riscv_decode_register_index(inst, 15);
rs2 = riscv_decode_register_index(inst, 20);
imm12 = (inst >> 20) & 0xFFF;
offset12 = (((inst >> 25) & 0x7F) << 5) + ((inst >> 7) & 0x1F);
/* Look for common stack adjustment insns. */
if ((is_addi_insn(inst) || is_addiw_insn(inst))
&& reg == RISCV_SP_REGNUM && rs1 == RISCV_SP_REGNUM)
{
/* addi sp, sp, -i */
/* addiw sp, sp, -i */
if (imm12 & 0x800)
frame_offset += 0x1000 - imm12;
else
break;
seen_sp_adjust = 1;
}
else if (is_sw_insn(inst) && rs1 == RISCV_SP_REGNUM)
{
/* sw reg, offset(sp) */
set_reg_offset (gdbarch, this_cache, rs1, sp + offset12);
}
else if (is_sd_insn(inst) && rs1 == RISCV_SP_REGNUM)
{
/* sd reg, offset(sp) */
set_reg_offset (gdbarch, this_cache, rs1, sp + offset12);
}
else if (is_addi_insn(inst) && reg == RISCV_FP_REGNUM
&& rs1 == RISCV_SP_REGNUM)
{
/* addi s0, sp, size */
if ((long)imm12 != frame_offset)
frame_addr = sp + imm12;
}
else if (this_frame && frame_reg == RISCV_SP_REGNUM)
{
unsigned alloca_adjust;
frame_reg = RISCV_FP_REGNUM;
frame_addr = get_frame_register_signed (this_frame, RISCV_FP_REGNUM);
alloca_adjust = (unsigned)(frame_addr - (sp - imm12));
if (alloca_adjust > 0)
{
sp += alloca_adjust;
reset_saved_regs (gdbarch, this_cache);
goto restart;
}
}
else if ((is_add_insn(inst) || is_addw_insn(inst))
&& reg == RISCV_FP_REGNUM && rs1 == RISCV_SP_REGNUM
&& rs2 == RISCV_ZERO_REGNUM)
{
/* add s0, sp, 0 */
/* addw s0, sp, 0 */
if (this_frame && frame_reg == RISCV_SP_REGNUM)
{
unsigned alloca_adjust;
frame_reg = RISCV_FP_REGNUM;
frame_addr = get_frame_register_signed (this_frame,
RISCV_FP_REGNUM);
alloca_adjust = (unsigned)(frame_addr - sp);
if (alloca_adjust > 0)
{
sp = frame_addr;
reset_saved_regs (gdbarch, this_cache);
goto restart;
}
}
}
else if (is_sw_insn(inst) && rs1 == RISCV_FP_REGNUM)
{
/* sw reg, offset(s0) */
set_reg_offset (gdbarch, this_cache, rs1, frame_addr + offset12);
}
else if (reg == RISCV_GP_REGNUM
&& (is_auipc_insn(inst)
|| is_lui_insn(inst)
|| (is_addi_insn(inst) && rs1 == RISCV_GP_REGNUM)
|| (is_add_insn(inst) && (rs1 == RISCV_GP_REGNUM
|| rs2 == RISCV_GP_REGNUM))))
{
/* auipc gp, n */
/* addi gp, gp, n */
/* add gp, gp, reg */
/* add gp, reg, gp */
/* lui gp, n */
/* These instructions are part of the prologue, but we don't need to
do anything special to handle them. */
}
else
{
if (end_prologue_addr == 0)
end_prologue_addr = cur_pc;
}
}
if (this_cache != NULL)
{
this_cache->base = get_frame_register_signed (this_frame, frame_reg)
+ frame_offset;
this_cache->saved_regs[RISCV_PC_REGNUM] =