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tc-riscv.c
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tc-riscv.c
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/* tc-riscv.c -- RISC-V assembler
Copyright (C) 2011-2020 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#include "as.h"
#include "config.h"
#include "subsegs.h"
#include "safe-ctype.h"
#include "itbl-ops.h"
#include "dwarf2dbg.h"
#include "dw2gencfi.h"
#include "bfd/elfxx-riscv.h"
#include "elf/riscv.h"
#include "opcode/riscv.h"
#include <stdint.h>
/* Information about an instruction, including its format, operands
and fixups. */
struct riscv_cl_insn
{
/* The opcode's entry in riscv_opcodes. */
const struct riscv_opcode *insn_mo;
/* The encoded instruction bits. */
insn_t insn_opcode;
/* The frag that contains the instruction. */
struct frag *frag;
/* The offset into FRAG of the first instruction byte. */
long where;
/* The relocs associated with the instruction, if any. */
fixS *fixp;
};
#ifndef DEFAULT_ARCH
#define DEFAULT_ARCH "riscv64"
#endif
#ifndef DEFAULT_RISCV_ATTR
#define DEFAULT_RISCV_ATTR 0
#endif
static const char default_arch[] = DEFAULT_ARCH;
static unsigned xlen = 0; /* width of an x-register */
static unsigned abi_xlen = 0; /* width of a pointer in the ABI */
static bfd_boolean rve_abi = FALSE;
#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
static unsigned elf_flags = 0;
/* This is the set of options which the .option pseudo-op may modify. */
struct riscv_set_options
{
int pic; /* Generate position-independent code. */
int rvc; /* Generate RVC code. */
int rve; /* Generate RVE code. */
int relax; /* Emit relocs the linker is allowed to relax. */
int arch_attr; /* Emit arch attribute. */
};
static struct riscv_set_options riscv_opts =
{
0, /* pic */
0, /* rvc */
0, /* rve */
1, /* relax */
DEFAULT_RISCV_ATTR, /* arch_attr */
};
static void
riscv_set_rvc (bfd_boolean rvc_value)
{
if (rvc_value)
elf_flags |= EF_RISCV_RVC;
riscv_opts.rvc = rvc_value;
}
static void
riscv_set_rve (bfd_boolean rve_value)
{
riscv_opts.rve = rve_value;
}
static riscv_subset_list_t riscv_subsets;
static bfd_boolean
riscv_subset_supports (const char *feature)
{
if (riscv_opts.rvc && (strcasecmp (feature, "c") == 0))
return TRUE;
return riscv_lookup_subset (&riscv_subsets, feature) != NULL;
}
static bfd_boolean
riscv_multi_subset_supports (enum riscv_insn_class insn_class)
{
switch (insn_class)
{
case INSN_CLASS_I: return riscv_subset_supports ("i");
case INSN_CLASS_C: return riscv_subset_supports ("c");
case INSN_CLASS_A: return riscv_subset_supports ("a");
case INSN_CLASS_M: return riscv_subset_supports ("m");
case INSN_CLASS_F: return riscv_subset_supports ("f");
case INSN_CLASS_D: return riscv_subset_supports ("d");
case INSN_CLASS_D_AND_C:
return riscv_subset_supports ("d") && riscv_subset_supports ("c");
case INSN_CLASS_F_AND_C:
return riscv_subset_supports ("f") && riscv_subset_supports ("c");
case INSN_CLASS_Q: return riscv_subset_supports ("q");
default:
as_fatal ("Unreachable");
return FALSE;
}
}
/* Set which ISA and extensions are available. */
static void
riscv_set_arch (const char *s)
{
riscv_parse_subset_t rps;
rps.subset_list = &riscv_subsets;
rps.error_handler = as_fatal;
rps.xlen = &xlen;
riscv_release_subset_list (&riscv_subsets);
riscv_parse_subset (&rps, s);
}
/* Handle of the OPCODE hash table. */
static struct hash_control *op_hash = NULL;
/* Handle of the type of .insn hash table. */
static struct hash_control *insn_type_hash = NULL;
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful */
const char comment_chars[] = "#";
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
.line and .file directives will appear in the pre-processed output */
/* Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
#NO_APP at the beginning of its output. */
/* Also note that C style comments are always supported. */
const char line_comment_chars[] = "#";
/* This array holds machine specific line separator characters. */
const char line_separator_chars[] = ";";
/* Chars that can be used to separate mant from exp in floating point nums */
const char EXP_CHARS[] = "eE";
/* Chars that mean this number is a floating point constant */
/* As in 0f12.456 */
/* or 0d1.2345e12 */
const char FLT_CHARS[] = "rRsSfFdDxXpP";
/* Indicate we are already assemble any instructions or not. */
static bfd_boolean start_assemble = FALSE;
/* Indicate arch attribute is explictly set. */
static bfd_boolean explicit_arch_attr = FALSE;
/* Macros for encoding relaxation state for RVC branches and far jumps. */
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
((relax_substateT) \
(0xc0000000 \
| ((uncond) ? 1 : 0) \
| ((rvc) ? 2 : 0) \
| ((length) << 2)))
#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
/* Is the given value a sign-extended 32-bit value? */
#define IS_SEXT_32BIT_NUM(x) \
(((x) &~ (offsetT) 0x7fffffff) == 0 \
|| (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
/* Is the given value a zero-extended 32-bit value? Or a negated one? */
#define IS_ZEXT_32BIT_NUM(x) \
(((x) &~ (offsetT) 0xffffffff) == 0 \
|| (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
#define INSERT_OPERAND(FIELD, INSN, VALUE) \
INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
/* Determine if an instruction matches an opcode. */
#define OPCODE_MATCHES(OPCODE, OP) \
(((OPCODE) & MASK_##OP) == MATCH_##OP)
static char *expr_end;
/* The default target format to use. */
const char *
riscv_target_format (void)
{
return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
}
/* Return the length of instruction INSN. */
static inline unsigned int
insn_length (const struct riscv_cl_insn *insn)
{
return riscv_insn_length (insn->insn_opcode);
}
/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
static void
create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
{
insn->insn_mo = mo;
insn->insn_opcode = mo->match;
insn->frag = NULL;
insn->where = 0;
insn->fixp = NULL;
}
/* Install INSN at the location specified by its "frag" and "where" fields. */
static void
install_insn (const struct riscv_cl_insn *insn)
{
char *f = insn->frag->fr_literal + insn->where;
md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
}
/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
and install the opcode in the new location. */
static void
move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
{
insn->frag = frag;
insn->where = where;
if (insn->fixp != NULL)
{
insn->fixp->fx_frag = frag;
insn->fixp->fx_where = where;
}
install_insn (insn);
}
/* Add INSN to the end of the output. */
static void
add_fixed_insn (struct riscv_cl_insn *insn)
{
char *f = frag_more (insn_length (insn));
move_insn (insn, frag_now, f - frag_now->fr_literal);
}
static void
add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
relax_substateT subtype, symbolS *symbol, offsetT offset)
{
frag_grow (max_chars);
move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
frag_var (rs_machine_dependent, max_chars, var,
subtype, symbol, offset, NULL);
}
/* Compute the length of a branch sequence, and adjust the stored length
accordingly. If FRAGP is NULL, the worst-case length is returned. */
static unsigned
relaxed_branch_length (fragS *fragp, asection *sec, int update)
{
int jump, rvc, length = 8;
if (!fragp)
return length;
jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
/* Assume jumps are in range; the linker will catch any that aren't. */
length = jump ? 4 : 8;
if (fragp->fr_symbol != NULL
&& S_IS_DEFINED (fragp->fr_symbol)
&& !S_IS_WEAK (fragp->fr_symbol)
&& sec == S_GET_SEGMENT (fragp->fr_symbol))
{
offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
val -= fragp->fr_address + fragp->fr_fix;
if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
length = 2;
else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
length = 4;
else if (!jump && rvc)
length = 6;
}
if (update)
fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
return length;
}
/* Information about an opcode name, mnemonics and its value. */
struct opcode_name_t
{
const char *name;
unsigned int val;
};
/* List for all supported opcode name. */
static const struct opcode_name_t opcode_name_list[] =
{
{"C0", 0x0},
{"C1", 0x1},
{"C2", 0x2},
{"LOAD", 0x03},
{"LOAD_FP", 0x07},
{"CUSTOM_0", 0x0b},
{"MISC_MEM", 0x0f},
{"OP_IMM", 0x13},
{"AUIPC", 0x17},
{"OP_IMM_32", 0x1b},
/* 48b 0x1f. */
{"STORE", 0x23},
{"STORE_FP", 0x27},
{"CUSTOM_1", 0x2b},
{"AMO", 0x2f},
{"OP", 0x33},
{"LUI", 0x37},
{"OP_32", 0x3b},
/* 64b 0x3f. */
{"MADD", 0x43},
{"MSUB", 0x47},
{"NMADD", 0x4f},
{"NMSUB", 0x4b},
{"OP_FP", 0x53},
/*reserved 0x57. */
{"CUSTOM_2", 0x5b},
/* 48b 0x5f. */
{"BRANCH", 0x63},
{"JALR", 0x67},
/*reserved 0x5b. */
{"JAL", 0x6f},
{"SYSTEM", 0x73},
/*reserved 0x77. */
{"CUSTOM_3", 0x7b},
/* >80b 0x7f. */
{NULL, 0}
};
/* Hash table for lookup opcode name. */
static struct hash_control *opcode_names_hash = NULL;
/* Initialization for hash table of opcode name. */
static void
init_opcode_names_hash (void)
{
const char *retval;
const struct opcode_name_t *opcode;
for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
{
retval = hash_insert (opcode_names_hash, opcode->name, (void *)opcode);
if (retval != NULL)
as_fatal (_("internal error: can't hash `%s': %s"),
opcode->name, retval);
}
}
/* Find `s` is a valid opcode name or not,
return the opcode name info if found. */
static const struct opcode_name_t *
opcode_name_lookup (char **s)
{
char *e;
char save_c;
struct opcode_name_t *o;
/* Find end of name. */
e = *s;
if (is_name_beginner (*e))
++e;
while (is_part_of_name (*e))
++e;
/* Terminate name. */
save_c = *e;
*e = '\0';
o = (struct opcode_name_t *) hash_find (opcode_names_hash, *s);
/* Advance to next token if one was recognized. */
if (o)
*s = e;
*e = save_c;
expr_end = e;
return o;
}
enum reg_class
{
RCLASS_GPR,
RCLASS_FPR,
RCLASS_CSR,
RCLASS_MAX
};
static struct hash_control *reg_names_hash = NULL;
#define ENCODE_REG_HASH(cls, n) \
((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
static void
hash_reg_name (enum reg_class class, const char *name, unsigned n)
{
void *hash = ENCODE_REG_HASH (class, n);
const char *retval = hash_insert (reg_names_hash, name, hash);
if (retval != NULL)
as_fatal (_("internal error: can't hash `%s': %s"), name, retval);
}
static void
hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
{
unsigned i;
for (i = 0; i < n; i++)
hash_reg_name (class, names[i], i);
}
static unsigned int
reg_lookup_internal (const char *s, enum reg_class class)
{
void *r = hash_find (reg_names_hash, s);
if (r == NULL || DECODE_REG_CLASS (r) != class)
return -1;
if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
return -1;
return DECODE_REG_NUM (r);
}
static bfd_boolean
reg_lookup (char **s, enum reg_class class, unsigned int *regnop)
{
char *e;
char save_c;
int reg = -1;
/* Find end of name. */
e = *s;
if (is_name_beginner (*e))
++e;
while (is_part_of_name (*e))
++e;
/* Terminate name. */
save_c = *e;
*e = '\0';
/* Look for the register. Advance to next token if one was recognized. */
if ((reg = reg_lookup_internal (*s, class)) >= 0)
*s = e;
*e = save_c;
if (regnop)
*regnop = reg;
return reg >= 0;
}
static bfd_boolean
arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop)
{
const char *p = strchr (*s, ',');
size_t i, len = p ? (size_t)(p - *s) : strlen (*s);
if (len == 0)
return FALSE;
for (i = 0; i < size; i++)
if (array[i] != NULL && strncmp (array[i], *s, len) == 0)
{
*regnop = i;
*s += len;
return TRUE;
}
return FALSE;
}
/* For consistency checking, verify that all bits are specified either
by the match/mask part of the instruction definition, or by the
operand list.
`length` could be 0, 4 or 8, 0 for auto detection. */
static bfd_boolean
validate_riscv_insn (const struct riscv_opcode *opc, int length)
{
const char *p = opc->args;
char c;
insn_t used_bits = opc->mask;
int insn_width;
insn_t required_bits;
if (length == 0)
insn_width = 8 * riscv_insn_length (opc->match);
else
insn_width = 8 * length;
required_bits = ~0ULL >> (64 - insn_width);
if ((used_bits & opc->match) != (opc->match & required_bits))
{
as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
opc->name, opc->args);
return FALSE;
}
#define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
while (*p)
switch (c = *p++)
{
case 'C': /* RVC */
switch (c = *p++)
{
case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
case 'c': break; /* RS1, constrained to equal sp */
case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
case 'w': break; /* RS1S, constrained to equal RD */
case 'x': break; /* RS2S, constrained to equal RD */
case 'z': break; /* RS2S, contrained to be x0 */
case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
case 'U': break; /* RS1, constrained to equal RD */
case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
case 'F': /* funct */
switch (c = *p++)
{
case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break;
case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break;
case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break;
default:
as_bad (_("internal: bad RISC-V opcode"
" (unknown operand type `CF%c'): %s %s"),
c, opc->name, opc->args);
return FALSE;
}
break;
default:
as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
c, opc->name, opc->args);
return FALSE;
}
break;
case ',': break;
case '(': break;
case ')': break;
case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
case 'A': break;
case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
case 'I': break;
case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* fallthru */
case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
case 'o':
case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
case 'z': break;
case '[': break;
case ']': break;
case '0': break;
case '1': break;
case 'F': /* funct */
switch (c = *p++)
{
case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
default:
as_bad (_("internal: bad RISC-V opcode"
" (unknown operand type `F%c'): %s %s"),
c, opc->name, opc->args);
return FALSE;
}
break;
case 'O': /* opcode */
switch (c = *p++)
{
case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break;
case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break;
default:
as_bad (_("internal: bad RISC-V opcode"
" (unknown operand type `F%c'): %s %s"),
c, opc->name, opc->args);
return FALSE;
}
break;
default:
as_bad (_("internal: bad RISC-V opcode "
"(unknown operand type `%c'): %s %s"),
c, opc->name, opc->args);
return FALSE;
}
#undef USE_BITS
if (used_bits != required_bits)
{
as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
~(unsigned long)(used_bits & required_bits),
opc->name, opc->args);
return FALSE;
}
return TRUE;
}
struct percent_op_match
{
const char *str;
bfd_reloc_code_real_type reloc;
};
/* Common hash table initialization function for
instruction and .insn directive. */
static struct hash_control *
init_opcode_hash (const struct riscv_opcode *opcodes,
bfd_boolean insn_directive_p)
{
int i = 0;
int length;
struct hash_control *hash = hash_new ();
while (opcodes[i].name)
{
const char *name = opcodes[i].name;
const char *hash_error =
hash_insert (hash, name, (void *) &opcodes[i]);
if (hash_error)
{
fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
opcodes[i].name, hash_error);
/* Probably a memory allocation problem? Give up now. */
as_fatal (_("Broken assembler. No assembly attempted."));
}
do
{
if (opcodes[i].pinfo != INSN_MACRO)
{
if (insn_directive_p)
length = ((name[0] == 'c') ? 2 : 4);
else
length = 0; /* Let assembler determine the length. */
if (!validate_riscv_insn (&opcodes[i], length))
as_fatal (_("Broken assembler. No assembly attempted."));
}
else
gas_assert (!insn_directive_p);
++i;
}
while (opcodes[i].name && !strcmp (opcodes[i].name, name));
}
return hash;
}
/* This function is called once, at assembler startup time. It should set up
all the tables, etc. that the MD part of the assembler will need. */
void
md_begin (void)
{
unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32;
if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))
as_warn (_("Could not set architecture and machine"));
op_hash = init_opcode_hash (riscv_opcodes, FALSE);
insn_type_hash = init_opcode_hash (riscv_insn_types, TRUE);
reg_names_hash = hash_new ();
hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR);
hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
/* Add "fp" as an alias for "s0". */
hash_reg_name (RCLASS_GPR, "fp", 8);
opcode_names_hash = hash_new ();
init_opcode_names_hash ();
#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
#define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
/* Set the default alignment for the text section. */
record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
}
static insn_t
riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
{
switch (reloc_type)
{
case BFD_RELOC_32:
return value;
case BFD_RELOC_RISCV_HI20:
return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value));
case BFD_RELOC_RISCV_LO12_S:
return ENCODE_STYPE_IMM (value);
case BFD_RELOC_RISCV_LO12_I:
return ENCODE_ITYPE_IMM (value);
default:
abort ();
}
}
/* Output an instruction. IP is the instruction information.
ADDRESS_EXPR is an operand of the instruction to be used with
RELOC_TYPE. */
static void
append_insn (struct riscv_cl_insn *ip, expressionS *address_expr,
bfd_reloc_code_real_type reloc_type)
{
dwarf2_emit_insn (0);
if (reloc_type != BFD_RELOC_UNUSED)
{
reloc_howto_type *howto;
gas_assert (address_expr);
if (reloc_type == BFD_RELOC_12_PCREL
|| reloc_type == BFD_RELOC_RISCV_JMP)
{
int j = reloc_type == BFD_RELOC_RISCV_JMP;
int best_case = riscv_insn_length (ip->insn_opcode);
unsigned worst_case = relaxed_branch_length (NULL, NULL, 0);
add_relaxed_insn (ip, worst_case, best_case,
RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case),
address_expr->X_add_symbol,
address_expr->X_add_number);
return;
}
else
{
howto = bfd_reloc_type_lookup (stdoutput, reloc_type);
if (howto == NULL)
as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type);
ip->fixp = fix_new_exp (ip->frag, ip->where,
bfd_get_reloc_size (howto),
address_expr, FALSE, reloc_type);
ip->fixp->fx_tcbit = riscv_opts.relax;
}
}
add_fixed_insn (ip);
install_insn (ip);
/* We need to start a new frag after any instruction that can be
optimized away or compressed by the linker during relaxation, to prevent
the assembler from computing static offsets across such an instruction.
This is necessary to get correct EH info. */
if (reloc_type == BFD_RELOC_RISCV_CALL
|| reloc_type == BFD_RELOC_RISCV_CALL_PLT
|| reloc_type == BFD_RELOC_RISCV_HI20
|| reloc_type == BFD_RELOC_RISCV_PCREL_HI20
|| reloc_type == BFD_RELOC_RISCV_TPREL_HI20
|| reloc_type == BFD_RELOC_RISCV_TPREL_ADD)
{
frag_wane (frag_now);
frag_new (0);
}
}
/* Build an instruction created by a macro expansion. This is passed
a pointer to the count of instructions created so far, an
expression, the name of the instruction to build, an operand format
string, and corresponding arguments. */
static void
macro_build (expressionS *ep, const char *name, const char *fmt, ...)
{
const struct riscv_opcode *mo;
struct riscv_cl_insn insn;
bfd_reloc_code_real_type r;
va_list args;
va_start (args, fmt);
r = BFD_RELOC_UNUSED;
mo = (struct riscv_opcode *) hash_find (op_hash, name);
gas_assert (mo);
/* Find a non-RVC variant of the instruction. append_insn will compress
it if possible. */
while (riscv_insn_length (mo->match) < 4)
mo++;
gas_assert (strcmp (name, mo->name) == 0);
create_insn (&insn, mo);
for (;;)
{
switch (*fmt++)
{
case 'd':
INSERT_OPERAND (RD, insn, va_arg (args, int));
continue;
case 's':
INSERT_OPERAND (RS1, insn, va_arg (args, int));
continue;
case 't':
INSERT_OPERAND (RS2, insn, va_arg (args, int));
continue;
case '>':
INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
continue;
case 'j':
case 'u':
case 'q':
gas_assert (ep != NULL);
r = va_arg (args, int);
continue;
case '\0':
break;
case ',':
continue;
default:
as_fatal (_("internal error: invalid macro"));
}
break;
}
va_end (args);
gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
append_insn (&insn, ep, r);
}
/* Build an instruction created by a macro expansion. Like md_assemble but
accept a printf-style format string and arguments. */
static void
md_assemblef (const char *format, ...)
{
char *buf = NULL;
va_list ap;
int r;
va_start (ap, format);
r = vasprintf (&buf, format, ap);
if (r < 0)
as_fatal (_("internal error: vasprintf failed"));
md_assemble (buf);
free(buf);
va_end (ap);
}
/* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
unset. */
static void
normalize_constant_expr (expressionS *ex)
{
if (xlen > 32)
return;
if ((ex->X_op == O_constant || ex->X_op == O_symbol)
&& IS_ZEXT_32BIT_NUM (ex->X_add_number))
ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
- 0x80000000);
}
/* Fail if an expression EX is not a constant. IP is the instruction using EX.
MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
static void
check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
bfd_boolean maybe_csr)
{
if (ex->X_op == O_big)
as_bad (_("unsupported large constant"));
else if (maybe_csr && ex->X_op == O_symbol)
as_bad (_("unknown CSR `%s'"),
S_GET_NAME (ex->X_add_symbol));
else if (ex->X_op != O_constant)
as_bad (_("Instruction %s requires absolute expression"),
ip->insn_mo->name);
normalize_constant_expr (ex);
}
static symbolS *
make_internal_label (void)
{
return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg,
(valueT) frag_now_fix (), frag_now);
}
/* Load an entry from the GOT. */
static void