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asm9.go
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/
asm9.go
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// cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova.
//
// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
// Portions Copyright © 1997-1999 Vita Nuova Limited
// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
// Portions Copyright © 2004,2006 Bruce Ellis
// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
// Portions Copyright © 2009 The Go Authors. All rights reserved.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
package ppc64
import (
"cmd/internal/obj"
"encoding/binary"
"fmt"
"log"
"sort"
)
// Instruction layout.
const (
funcAlign = 8
)
const (
r0iszero = 1
)
type Optab struct {
as obj.As // Opcode
a1 uint8
a2 uint8
a3 uint8
a4 uint8
type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r
size int8
param int16
}
var optab = []Optab{
{obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0},
{obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0},
{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0},
{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0},
/* move register */
{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0},
{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0},
{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0},
{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0},
{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0},
{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
{AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
{AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
{AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0},
{AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0},
{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0},
{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0},
{AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0},
{AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
{AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
{AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
{AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0},
{AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0},
{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */
{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
{AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
{AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
{AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0},
{AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0},
{AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0},
{AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0},
{AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0},
{AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0},
{AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0},
{AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
{AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
{AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
{AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
{AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
{AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0},
{AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0},
{ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0},
{ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0},
{ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0},
{ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0},
{AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */
{AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
{AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0},
{AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0},
{AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0},
{AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0},
{AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0},
{AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0},
{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */
{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */
{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0},
{ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
{ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
{ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
{ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
{ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0},
{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0},
{ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0},
{ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0},
{ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
{ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
{ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0},
{ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0},
{ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
{ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
{ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0},
{ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0},
{ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0},
{ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0},
{ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0},
{ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0},
{ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0},
{ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0},
{ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0},
{ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0},
{ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0},
{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0},
{AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0},
{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0},
{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0},
{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0},
{AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0},
{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0},
{AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0},
/* store, short offset */
{AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
{AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
{AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
{AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
{AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
{AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
{AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
{AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
{AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
{AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
{AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
{AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
{AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
{AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
{AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
{AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
{AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
{AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
{AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
{AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
{AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
/* load, short offset */
{AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
{AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
{AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
{AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
{AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
{AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO},
{AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO},
{AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
{AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
{AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
{AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
{AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB},
{AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
{AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
{AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
{AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
{AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP},
{AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
{AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
{AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
{AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
{AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
{AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO},
{AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO},
/* store, long offset */
{AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
{AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
{AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
{AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
/* load, long offset */
{AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
{AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
{AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
{AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
{AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB},
{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP},
{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO},
{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0},
{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0},
{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0},
{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0},
/* load constant */
{AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB},
{AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP},
{AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB},
{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP},
{AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
{AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */
{AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP},
{AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB},
{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP},
{AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
{AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */
{AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP},
{AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB},
{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP},
{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
/* load unsigned/long constants (TO DO: check) */
{AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
{AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0},
{AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
{AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0},
{AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
{AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0},
{AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0},
{AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
{AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0},
{AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0},
{ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0},
{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0},
{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0},
{ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0},
{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0},
{ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0},
{ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0},
{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0},
{ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0},
{ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0},
{ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0},
{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0},
{ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0},
{ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0},
{ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0},
{ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0},
{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0},
{AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB},
{AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP},
{AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO},
{AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB},
{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP},
{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO},
{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0},
{AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
{AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
{AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
{AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
{AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0},
{AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0},
{AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0},
{AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
{AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0},
{AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0},
{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0},
{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0},
{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0},
{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0},
{AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0},
{AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0},
{AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0},
{AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0},
{AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0},
{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0},
{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0},
{AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0},
{AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0},
{AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0},
{AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0},
{AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0},
{AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0},
{AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0},
{AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0},
{AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0},
{AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0},
{AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0},
{AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0},
{AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0},
{AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */
{AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */
{AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */
/* Vector instructions */
/* Vector load */
{ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */
/* Vector store */
{ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */
/* Vector logical */
{AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */
{AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */
/* Vector add */
{AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */
{AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */
{AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */
{AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */
{AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */
/* Vector subtract */
{AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */
{AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */
{AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */
{AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */
{AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */
/* Vector rotate */
{AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */
/* Vector shift */
{AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */
{AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */
{AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */
/* Vector count */
{AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */
{AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */
/* Vector compare */
{AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */
{AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */
/* Vector permute */
{AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */
/* Vector select */
{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */
/* Vector splat */
{AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */
{AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0},
{AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */
{AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0},
/* Vector AES */
{AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */
{AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */
{AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */
/* Vector SHA */
{AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */
/* VSX vector load */
{ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */
/* VSX vector store */
{ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */
/* VSX scalar load */
{ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */
/* VSX scalar store */
{ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */
/* VSX scalar as integer load */
{ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */
/* VSX scalar store as integer */
{ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */
/* VSX move from VSR */
{AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */
/* VSX move to VSR */
{AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */
/* VSX logical */
{AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */
{AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */
/* VSX select */
{AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */
/* VSX merge */
{AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */
/* VSX splat */
{AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */
/* VSX permute */
{AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */
/* VSX shift */
{AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */
/* VSX scalar FP-FP conversion */
{AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */
/* VSX vector FP-FP conversion */
{AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */
/* VSX scalar FP-integer conversion */
{AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */
/* VSX scalar integer-FP conversion */
{AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */
/* VSX vector FP-integer conversion */
{AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */
/* VSX vector integer-FP conversion */
{AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */
/* 64-bit special registers */
{AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0},
{AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0},
{AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0},
{AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0},
{AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0},
{AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0},
{AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0},
{AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0},
/* 32-bit special registers (gloss over sign-extension or not?) */
{AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0},
{AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0},
{AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0},
{AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0},
{AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0},
{AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0},
{AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0},
{AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0},
{AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0},
{AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0},
{AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0},
{AMOVFL, C_REG, C_NONE, C_LCON, C_CREG, 69, 4, 0},
{AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0},
{AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0},
{AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0},
{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0},
{ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0},
{ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0},
{ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0},
{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0},
{ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0},
{ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0},
{ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0},
{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0},
{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0},
{ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0},
{ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0},
{ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0},
{ADCBF, C_ZOREG, C_REG, C_NONE, C_NONE, 43, 4, 0},
{AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0},
{AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0},
{AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
{AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
{AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0},
{ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0},
{ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0},
{ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0},
{ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0},
{ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
{ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0},
{ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
{ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0},
{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0},
{obj.AUSEFIELD, C_ADDR, C_NONE, C_NONE, C_NONE, 0, 0, 0},
{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0},
{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0},
{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0},
{obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL
{obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL
{obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0},
}
var oprange [ALAST & obj.AMask][]Optab
var xcmp [C_NCLASS][C_NCLASS]bool
func span9(ctxt *obj.Link, cursym *obj.LSym) {
p := cursym.Text
if p == nil || p.Link == nil { // handle external functions and ELF section symbols
return
}
ctxt.Cursym = cursym
ctxt.Autosize = int32(p.To.Offset)
if oprange[AANDN&obj.AMask] == nil {
buildop(ctxt)
}
c := int64(0)
p.Pc = c
var m int
var o *Optab
for p = p.Link; p != nil; p = p.Link {
ctxt.Curp = p
p.Pc = c
o = oplook(ctxt, p)
m = int(o.size)
if m == 0 {
if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA && p.As != obj.AUSEFIELD {
ctxt.Diag("zero-width instruction\n%v", p)
}
continue
}
c += int64(m)
}
cursym.Size = c
/*
* if any procedure is large enough to
* generate a large SBRA branch, then
* generate extra passes putting branches
* around jmps to fix. this is rare.
*/
bflag := 1
var otxt int64
var q *obj.Prog
for bflag != 0 {
if ctxt.Debugvlog != 0 {
ctxt.Logf("%5.2f span1\n", obj.Cputime())
}
bflag = 0
c = 0
for p = cursym.Text.Link; p != nil; p = p.Link {
p.Pc = c
o = oplook(ctxt, p)
// very large conditional branches
if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil {
otxt = p.Pcond.Pc - c
if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 {
q = ctxt.NewProg()
q.Link = p.Link
p.Link = q
q.As = ABR
q.To.Type = obj.TYPE_BRANCH
q.Pcond = p.Pcond
p.Pcond = q
q = ctxt.NewProg()
q.Link = p.Link
p.Link = q
q.As = ABR
q.To.Type = obj.TYPE_BRANCH
q.Pcond = q.Link.Link
//addnop(p->link);
//addnop(p);
bflag = 1
}
}
m = int(o.size)
if m == 0 {
if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA && p.As != obj.AUSEFIELD {
ctxt.Diag("zero-width instruction\n%v", p)
}
continue
}
c += int64(m)
}
cursym.Size = c
}
c += -c & (funcAlign - 1)
cursym.Size = c
/*
* lay out the code, emitting code and data relocations.
*/
cursym.Grow(cursym.Size)
bp := cursym.P
var i int32
var out [6]uint32
for p := cursym.Text.Link; p != nil; p = p.Link {
ctxt.Pc = p.Pc
ctxt.Curp = p
o = oplook(ctxt, p)
if int(o.size) > 4*len(out) {
log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p)
}
asmout(ctxt, p, o, out[:])
for i = 0; i < int32(o.size/4); i++ {
ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
bp = bp[4:]
}
}
}
func isint32(v int64) bool {
return int64(int32(v)) == v
}
func isuint32(v uint64) bool {
return uint64(uint32(v)) == v
}
func aclass(ctxt *obj.Link, a *obj.Addr) int {
switch a.Type {
case obj.TYPE_NONE:
return C_NONE
case obj.TYPE_REG:
if REG_R0 <= a.Reg && a.Reg <= REG_R31 {
return C_REG
}
if REG_F0 <= a.Reg && a.Reg <= REG_F31 {
return C_FREG
}
if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
return C_VREG
}
if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 {
return C_VSREG
}
if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR {
return C_CREG
}
if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 {
switch a.Reg {
case REG_LR:
return C_LR
case REG_XER:
return C_XER
case REG_CTR:
return C_CTR
}
return C_SPR
}
if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 {
return C_SPR
}
if a.Reg == REG_FPSCR {
return C_FPSCR
}
if a.Reg == REG_MSR {
return C_MSR
}
return C_GOK
case obj.TYPE_MEM:
switch a.Name {
case obj.NAME_EXTERN,
obj.NAME_STATIC:
if a.Sym == nil {
break
}
ctxt.Instoffset = a.Offset
if a.Sym != nil { // use relocation
if a.Sym.Type == obj.STLSBSS {
if ctxt.Flag_shared {
return C_TLS_IE
} else {
return C_TLS_LE
}
}
return C_ADDR
}
return C_LEXT
case obj.NAME_GOTREF:
return C_GOTADDR
case obj.NAME_AUTO:
ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset
if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
return C_SAUTO
}
return C_LAUTO
case obj.NAME_PARAM:
ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize()
if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
return C_SAUTO
}
return C_LAUTO
case obj.NAME_NONE:
ctxt.Instoffset = a.Offset
if ctxt.Instoffset == 0 {
return C_ZOREG
}
if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
return C_SOREG
}
return C_LOREG
}
return C_GOK
case obj.TYPE_TEXTSIZE:
return C_TEXTSIZE
case obj.TYPE_CONST,
obj.TYPE_ADDR:
switch a.Name {
case obj.NAME_NONE:
ctxt.Instoffset = a.Offset
if a.Reg != 0 {
if -BIG <= ctxt.Instoffset && ctxt.Instoffset <= BIG {
return C_SACON
}
if isint32(ctxt.Instoffset) {
return C_LACON
}
return C_DACON
}
goto consize
case obj.NAME_EXTERN,
obj.NAME_STATIC:
s := a.Sym
if s == nil {
break
}
if s.Type == obj.SCONST {
ctxt.Instoffset = a.Offset
goto consize
}
ctxt.Instoffset = a.Offset
/* not sure why this barfs */
return C_LCON
case obj.NAME_AUTO:
ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset
if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
return C_SACON
}
return C_LACON
case obj.NAME_PARAM:
ctxt.Instoffset = int64(ctxt.Autosize) + a.Offset + ctxt.FixedFrameSize()
if ctxt.Instoffset >= -BIG && ctxt.Instoffset < BIG {
return C_SACON
}
return C_LACON
}
return C_GOK
consize:
if ctxt.Instoffset >= 0 {
if ctxt.Instoffset == 0 {
return C_ZCON
}
if ctxt.Instoffset <= 0x7fff {
return C_SCON
}
if ctxt.Instoffset <= 0xffff {
return C_ANDCON
}
if ctxt.Instoffset&0xffff == 0 && isuint32(uint64(ctxt.Instoffset)) { /* && (instoffset & (1<<31)) == 0) */
return C_UCON
}
if isint32(ctxt.Instoffset) || isuint32(uint64(ctxt.Instoffset)) {
return C_LCON
}
return C_DCON
}
if ctxt.Instoffset >= -0x8000 {
return C_ADDCON
}
if ctxt.Instoffset&0xffff == 0 && isint32(ctxt.Instoffset) {
return C_UCON
}
if isint32(ctxt.Instoffset) {
return C_LCON
}
return C_DCON
case obj.TYPE_BRANCH:
if a.Sym != nil && ctxt.Flag_dynlink {
return C_LBRAPIC
}
return C_SBRA
}
return C_GOK
}
func prasm(p *obj.Prog) {
fmt.Printf("%v\n", p)
}
func oplook(ctxt *obj.Link, p *obj.Prog) *Optab {
a1 := int(p.Optab)
if a1 != 0 {
return &optab[a1-1]
}
a1 = int(p.From.Class)
if a1 == 0 {
a1 = aclass(ctxt, &p.From) + 1
p.From.Class = int8(a1)
}
a1--
a3 := C_NONE + 1
if p.From3 != nil {
a3 = int(p.From3.Class)
if a3 == 0 {
a3 = aclass(ctxt, p.From3) + 1
p.From3.Class = int8(a3)
}
}
a3--
a4 := int(p.To.Class)
if a4 == 0 {
a4 = aclass(ctxt, &p.To) + 1
p.To.Class = int8(a4)
}
a4--
a2 := C_NONE
if p.Reg != 0 {
if REG_R0 <= p.Reg && p.Reg <= REG_R31 {
a2 = C_REG
} else if REG_V0 <= p.Reg && p.Reg <= REG_V31 {
a2 = C_VREG
} else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 {
a2 = C_VSREG
} else if REG_F0 <= p.Reg && p.Reg <= REG_F31 {
a2 = C_FREG
}
}
//print("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4);
ops := oprange[p.As&obj.AMask]
c1 := &xcmp[a1]
c3 := &xcmp[a3]
c4 := &xcmp[a4]
for i := range ops {
op := &ops[i]
if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] {
p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
return op
}
}
ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4))
prasm(p)
if ops == nil {
ops = optab
}
return &ops[0]
}
func cmp(a int, b int) bool {
if a == b {
return true
}
switch a {
case C_LCON:
if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
return true
}
case C_ADDCON:
if b == C_ZCON || b == C_SCON {
return true
}
case C_ANDCON:
if b == C_ZCON || b == C_SCON {
return true
}
case C_SPR:
if b == C_LR || b == C_XER || b == C_CTR {
return true
}
case C_UCON:
if b == C_ZCON {
return true
}
case C_SCON:
if b == C_ZCON {
return true
}
case C_LACON:
if b == C_SACON {
return true
}
case C_LBRA:
if b == C_SBRA {
return true
}
case C_LEXT:
if b == C_SEXT {
return true
}
case C_LAUTO:
if b == C_SAUTO {
return true
}
case C_REG:
if b == C_ZCON {
return r0iszero != 0 /*TypeKind(100016)*/
}
case C_LOREG:
if b == C_ZOREG || b == C_SOREG {
return true
}
case C_SOREG:
if b == C_ZOREG {
return true
}
case C_ANY:
return true
}