This section details the steps for adding support for new instructions in the native python plugins of RISCV-ISAC.
Note
An alternative is to add support for the new instructions using the riscv/riscv-opcodes repository. Refer rvopcodes for further information.
The first step is to update the parser-module to be able to deduce the relevant fields of the new instruction and create the required ~riscv_isac.parsers.instructionObject.
As part of this phase, the contributor will first have to add a function(s) which will decode the instruction hexadecimal encoding and extract the parameters of the ~riscv_isac.parsers.instructionObject. Make sure to follow the same code structure as used by other functions in module.
Currently the top level function that get's called by the coverage module is the ~riscv_isac.parsers.parseInstruction function. This function based on the instruction length encoding scheme defined by the RISC-V ISA spec identifies the length of the instruction. If the instruction is compressed then the ~riscv_isac.parsers.parseCompressedInstruction function is called, else the ~riscv_isac.parsers.parseInstruction function is called.
If the new instruction(s) being added belong to the non-compressed opcodes, then the particular entry in ~riscv_isac.parsers.OPCODES needs to be updated to point to the new function(s) defined earlier. If there are instructions falling into the compressed op-code space then the functions ~riscv_isac.parsers.quad0, ~riscv_isac.parsers.quad1 or ~riscv_isac.parsers.quad2 will need to be updated accordingly.
The coverage module maintains its own architectural state : integer register file, program counter, floating point register file, etc. If the new instruction(s) requires an additional architectural state, then that needs to be added in ~riscv_isac.coverage.archStats and the usage needs to be updated in ~riscv_isac.coverage.compute_per_line.