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Move the RISC-V local interrupt controller to drivers/irqchip
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@palmer-dabbelt
palmer-dabbelt committed Jun 1, 2017
1 parent 939e4f1 commit 549c7f5
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Showing 4 changed files with 254 additions and 224 deletions.
1 change: 1 addition & 0 deletions arch/riscv/Kconfig
View file
Expand Up @@ -34,6 +34,7 @@ config RISCV
select HAVE_ARCH_TRACEHOOK
select MODULES_USE_ELF_RELA if MODULES
select THREAD_INFO_IN_TASK
select RISCV_IRQ_INTC

config MMU
def_bool y
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224 changes: 0 additions & 224 deletions arch/riscv/kernel/irq.c
View file
Expand Up @@ -12,231 +12,7 @@
* GNU General Public License for more details.
*/

#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/ftrace.h>
#include <linux/of.h>
#include <linux/seq_file.h>

#include <asm/ptrace.h>
#include <asm/sbi.h>
#include <asm/smp.h>

struct riscv_irq_data {
struct irq_chip chip;
struct irq_domain *domain;
int hart;
char name[20];
};
DEFINE_PER_CPU(struct riscv_irq_data, riscv_irq_data);
DEFINE_PER_CPU(atomic_long_t, riscv_early_sie);

static void riscv_software_interrupt(void)
{
#ifdef CONFIG_SMP
irqreturn_t ret;

ret = handle_ipi();
if (ret != IRQ_NONE)
return;
#endif

BUG();
}

asmlinkage void __irq_entry do_IRQ(unsigned int cause, struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
struct irq_domain *domain;

irq_enter();

/* There are three classes of interrupt: timer, software, and
* external devices. We dispatch between them here. External
* device interrupts use the generic IRQ mechanisms.
*/
switch (cause) {
case INTERRUPT_CAUSE_TIMER:
riscv_timer_interrupt();
break;
case INTERRUPT_CAUSE_SOFTWARE:
riscv_software_interrupt();
break;
default:
domain = per_cpu(riscv_irq_data, smp_processor_id()).domain;
generic_handle_irq(irq_find_mapping(domain, cause));
break;
}

irq_exit();
set_irq_regs(old_regs);
}

static int riscv_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
struct riscv_irq_data *data = d->host_data;

irq_set_chip_and_handler(irq, &data->chip, handle_simple_irq);
irq_set_chip_data(irq, data);
irq_set_noprobe(irq);

return 0;
}

static const struct irq_domain_ops riscv_irqdomain_ops = {
.map = riscv_irqdomain_map,
.xlate = irq_domain_xlate_onecell,
};

static void riscv_irq_mask(struct irq_data *d)
{
struct riscv_irq_data *data = irq_data_get_irq_chip_data(d);

BUG_ON(smp_processor_id() != data->hart);
csr_clear(sie, 1 << (long)d->hwirq);
}

static void riscv_irq_unmask(struct irq_data *d)
{
struct riscv_irq_data *data = irq_data_get_irq_chip_data(d);

BUG_ON(smp_processor_id() != data->hart);
csr_set(sie, 1 << (long)d->hwirq);
}

static void riscv_irq_enable_helper(void *d)
{
riscv_irq_unmask(d);
}

static void riscv_irq_enable(struct irq_data *d)
{
struct riscv_irq_data *data = irq_data_get_irq_chip_data(d);

/* There are two phases to setting up an interrupt: first we set a bit
* in this bookkeeping structure, which is used by trap_init to
* initialize SIE for each hart as it comes up.
*/
atomic_long_or((1 << (long)d->hwirq),
&per_cpu(riscv_early_sie, data->hart));

/* The CPU is usually online, so here we just attempt to enable the
* interrupt by writing SIE directly. We need to write SIE on the
* correct hart, which might be another hart.
*/
if (data->hart == smp_processor_id())
riscv_irq_unmask(d);
else if (cpu_online(data->hart))
smp_call_function_single(data->hart,
riscv_irq_enable_helper,
d,
true);
}

static void riscv_irq_disable_helper(void *d)
{
riscv_irq_mask(d);
}

static void riscv_irq_disable(struct irq_data *d)
{
struct riscv_irq_data *data = irq_data_get_irq_chip_data(d);

/* This is the mirror of riscv_irq_enable. */
atomic_long_and(~(1 << (long)d->hwirq),
&per_cpu(riscv_early_sie, data->hart));
if (data->hart == smp_processor_id())
riscv_irq_mask(d);
else if (cpu_online(data->hart))
smp_call_function_single(data->hart,
riscv_irq_disable_helper,
d,
true);
}

static void riscv_irq_mask_noop(struct irq_data *d) { }

static void riscv_irq_unmask_noop(struct irq_data *d) { }

static void riscv_irq_enable_noop(struct irq_data *d)
{
struct device_node *data = irq_data_get_irq_chip_data(d);
u32 hart;

if (!of_property_read_u32(data, "reg", &hart))
printk(
KERN_WARNING "enabled interrupt %d for missing hart %d (this interrupt has no handler)\n",
(int)d->hwirq, hart);
}

static struct irq_chip riscv_noop_chip = {
.name = "riscv,cpu-intc,noop",
.irq_mask = riscv_irq_mask_noop,
.irq_unmask = riscv_irq_unmask_noop,
.irq_enable = riscv_irq_enable_noop,
};

static int riscv_irqdomain_map_noop(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
struct device_node *data = d->host_data;

irq_set_chip_and_handler(irq, &riscv_noop_chip, handle_simple_irq);
irq_set_chip_data(irq, data);
return 0;
}

static const struct irq_domain_ops riscv_irqdomain_ops_noop = {
.map = riscv_irqdomain_map_noop,
.xlate = irq_domain_xlate_onecell,
};

static int riscv_intc_init(struct device_node *node, struct device_node *parent)
{
int hart;
struct riscv_irq_data *data;

if (parent)
return 0;

hart = riscv_of_processor_hart(node->parent);
if (hart < 0) {
/* If a hart is disabled, create a no-op irq domain. Devices
* may still have interrupts connected to those harts. This is
* not wrong... unless they actually load a driver that needs
* it!
*/
irq_domain_add_linear(
node,
8*sizeof(uintptr_t),
&riscv_irqdomain_ops_noop,
node->parent);
return 0;
}

data = &per_cpu(riscv_irq_data, hart);
snprintf(data->name, sizeof(data->name), "riscv,cpu_intc,%d", hart);
data->hart = hart;
data->chip.name = data->name;
data->chip.irq_mask = riscv_irq_mask;
data->chip.irq_unmask = riscv_irq_unmask;
data->chip.irq_enable = riscv_irq_enable;
data->chip.irq_disable = riscv_irq_disable;
data->domain = irq_domain_add_linear(
node,
8*sizeof(uintptr_t),
&riscv_irqdomain_ops,
data);
WARN_ON(!data->domain);
printk(KERN_INFO "%s: %d local interrupts mapped\n",
data->name, 8*(int)sizeof(uintptr_t));
return 0;
}

IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);

void __init init_IRQ(void)
{
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14 changes: 14 additions & 0 deletions drivers/irqchip/Kconfig
View file
Expand Up @@ -313,3 +313,17 @@ config RISCV_PLIC
interrupt sources (MSI, GPIO, etc) are subordinate to the PLIC.

If you don't know what to do here, say Y.

config RISCV_INTC
def_bool y if RISCV
#bool "RISC-V Interrupt Controller"
depends on RISCV
default y
help
This enables support for the local interrupt controller found in
standard RISC-V systems. The local interrupt controller handles
timer interrupts, software interrupts, and hardware interrupts.
Without a local interrupt controller the system will be unable to
handle any interrupts, including those passed via the PLIC.

If you don't know what to do here, say Y.

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