fix crash when we try to read vector register on a running target

Change-Id: I0e140d69faa67f8817310cf18a4db3c581013de2 Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com>
riscv-collab · Aug 17, 2023 · 0ae47ae · 0ae47ae
1 parent f061623
commit 0ae47ae
Showing 1 changed file with 6 additions and 6 deletions.
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
@@ -2369,16 +2369,16 @@ static int riscv013_get_register_buf(struct target *target,
 	if (dm013_select_target(target) != ERROR_OK)
 		return ERROR_FAIL;
 
-	if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
-		return ERROR_FAIL;
-
 	riscv_reg_t mstatus, vtype, vl;
 	unsigned int debug_vl, debug_vsew;
 
 	if (prep_for_vector_access(target, &mstatus, &vtype, &vl,
 				&debug_vl, &debug_vsew) != ERROR_OK)
 		return ERROR_FAIL;
 
+	if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
+		return ERROR_FAIL;
+
 	unsigned int vnum = regno - GDB_REGNO_V0;
 
 	int result = ERROR_OK;
@@ -2424,16 +2424,16 @@ static int riscv013_set_register_buf(struct target *target,
 	if (dm013_select_target(target) != ERROR_OK)
 		return ERROR_FAIL;
 
-	if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
-		return ERROR_FAIL;
-
 	riscv_reg_t mstatus, vtype, vl;
 	unsigned int debug_vl, debug_vsew;
 
 	if (prep_for_vector_access(target, &mstatus, &vtype, &vl,
 				&debug_vl, &debug_vsew) != ERROR_OK)
 		return ERROR_FAIL;
 
+	if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
+		return ERROR_FAIL;
+
 	unsigned int vnum = regno - GDB_REGNO_V0;
 
 	struct riscv_program program;