c_sext_b.adoc

c.sext.b

Synopsis

Sign extend byte, 16-bit encoding

Mnemonic

c.sext.b rd'/rs1'

Encoding (RV32, RV64)

{reg:[
    { bits:  2, name: 0x1, attr: ['C1'] },
    { bits:  3, name: 0x1, attr: ['C.SEXT.B'] },
    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
    { bits:  3, name: 0x7 },
    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
],config:{bits:16}}

Description

This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand to XLEN bits by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits.

Note	rd'/rs1' is from the standard 8-register set x8-x15.

Prerequisites

Zbb is also required.

32-bit equivalent

[insns-sext_b] from Zbb

Note	The SAIL module variable for rd'/rs1' is called rsdc.

Operation

X(rsdc) = EXTS(X(rsdc)[7..0]);

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