c_zext_w.adoc

c.zext.w

Synopsis

Zero extend word, 16-bit encoding

Mnemonic

c.zext.w rd'/rs1'

Encoding (RV64)

{reg:[
    { bits:  2, name: 0x1, attr: ['C1'] },
    { bits:  3, name: 0x4, attr: ['C.ZEXT.W'] },
    { bits:  2, name: 0x3, attr: ['FUNCT2'] },
    { bits:  3, name: 'rd\'/rs1\'', attr: ['SRCDST'] },
    { bits:  3, name: 0x7 },
    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
],config:{bits:16}}

Description

This instruction takes a single source/destination operand. It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31.

Note	rd'/rs1' is from the standard 8-register set x8-x15.

Prerequisites

Zba is also required.

32-bit equivalent

add.uw rd'/rs1', rd'/rs1', zero

Note	The SAIL module variable for rd'/rs1' is called rsdc.

Operation

X(rsdc) = EXTZ(X(rsdc)[31..0]);

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