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1. Zc* v1.0.0-RC5.3

1.1. Change history since v0.70.1 (tagged release)

Table 1. Change history
Version change

v1.0.0-RC5.3

Add dependency on Zicsr for Zcmt

v1.0.0-RC5.2

Adjust the split so we have 240 cm.jalt and 16 cm.jt

v1.0.0-RC5.1

Make cm.jt/cm.jalt only valid if JVT.mode=0, and allow different behaviour in the future if JVT.mode>0

v1.0.0-RC5

Revert to cm.jt and cm.jalt encodings, to avoid toolchain and trace problems

v1.0.0-RC4.1

Resolve typographical issues with the document only, no actual changes

v1.0.0-RC4

Release candidate

Remove Zcmb as benefit is low. Remove cm.jalt, read LSB of jump table entry to determine whether to link

v0.70.5

Resolve #163 - jvt.base is WARL and fewer bits than the max can be implemented

v0.70.4

Clarified #159 - Need Zbb and Zba for RV64 and M/ZMmul to get all of Zcb

Resolved #161

Resolved #160 - Allocated Smstateen bit 2 and added the relevant text

v0.70.3

Added rule that Zcf and Zcmt imply Zca (this text was missing, this is not a spec change: #151)

Added that Zcf is illegal for RV64, as it contains no instructions (clarification: #149)

Added push/pop examples in the push/pop section

v0.70.2

Stylistic changes only, removing redundant text.

Corrected field names on JVT CSR diagram, and fixed synopsis for cm.mvsa01

1.2. Zc* Overview

This document is in the Frozen state. Change is extremely unlikely. A high threshold will be used, and a change will only occur because of some truly critical issue being identified during the public review cycle. Any other desired or needed changes can be the subject of a follow-on new extension. See https://riscv.org/spec-state

Zc* is a group of extensions which define subsets of the existing C extension (Zca, Zcd, Zcf) and new extensions which only contain 16-bit encodings.

Zcm* all reuse the encodings for c.fld, c.fsd, c.fldsp, c.fsdsp.

Table 2. Zc* extension overview
Instruction Zca Zcf Zcd Zcb Zcmp Zcmpe Zcmt

The Zca extension is added as way to refer to instructions in the C extension that do not include the floating-point loads and stores

C excl. c.f*

yes

The Zcf extension is added as a way to refer to compressed single-precision floating-point load/stores

c.flw

yes

c.flwsp

yes

c.fsw

yes

c.fswsp

yes

The Zcd extension is added as a way to refer to compressed double-precision floating-point load/stores

c.fld

yes

c.fldsp

yes

c.fsd

yes

c.fsdsp

yes

Simple operations for use on all architectures

c.lbu

yes

c.lh

yes

c.lhu

yes

c.sb

yes

c.sh

yes

c.zext.b

yes

c.sext.b

yes

c.zext.h

yes

c.sext.h

yes

c.zext.w

yes

c.mul

yes

c.not

yes

PUSH/POP and double move which overlap with c.fsdsp

cm.push

yes

yes

cm.pop

yes

yes

cm.popret

yes

yes

cm.popretz

yes

yes

cm.mva01s

yes

cm.mvsa01

yes

Reserved for EABI versions of PUSH/POP and double move which overlap with c.fsdsp

cm.push.e

yes

cm.pop.e

yes

cm.popret.e

yes

cm.popretz.e

yes

cm.mva01s.e

yes

cm.mvsa01.e

yes

Table jump

cm.jt

yes

cm.jalt

yes

1.3. Zca

The Zca extension is added as way to refer to instructions in the C extension that do not include the floating-point loads and stores.

Therefore it excluded all 16-bit floating point loads and stores: c.flw, c.flwsp, c.fsw, c.fswsp, c.fld, c.fldsp, c.fsd, c.fsdsp.

Note
 the the C extension only includes F/D instructions when D and F are also specified

1.4. Zcf (RV32 only)

Zcf is the existing set of compressed single precision floating point loads and stores: c.flw, c.flwsp, c.fsw, c.fswsp.

Zcf is only relevant to RV32, it cannot be specified for RV64.

Zcf requires the Zca extension.

1.5. Zcd

Zcd is the existing set of compressed double precision floating point loads and stores: c.fld, c.fldsp, c.fsd, c.fsdsp.

Zcd requires the Zca extension.

1.6. Zcb

All proposed encodings are currently reserved for all architectures, and have no conflicts with any existing extensions.

Zcb requires the Zca extension.

As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented. For example, c.mul is only implemented if M or Zmmul is implemented, and c.sext.b is only implemented if Zbb is implemented.

The c.mul encoding uses the CR register format along with other instructions such as c.sub, c.xor etc.

Note
 c.sext.w is a pseudo-instruction for c.addiw rd, 0 (RV64)
RV32 RV64 Mnemonic Instruction

yes

yes

c.lbu rd', uimm(rs1')

[insns-c_lbu]

yes

yes

c.lhu rd', uimm(rs1')

[insns-c_lhu]

yes

yes

c.lh rd', uimm(rs1')

[insns-c_lh]

yes

yes

c.sb rs2', uimm(rs1')

[insns-c_sb]

yes

yes

c.sh rs2', uimm(rs1')

[insns-c_sh]

yes

yes

c.zext.b rsd'

[insns-c_zext_b]

yes

yes

c.sext.b rsd'

[insns-c_sext_b]

yes

yes

c.zext.h rsd'

[insns-c_zext_h]

yes

yes

c.sext.h rsd'

[insns-c_sext_h]

yes

c.zext.w rsd'

[insns-c_zext_w]

yes

yes

c.not rsd'

[insns-c_not]

yes

yes

c.mul rsd', rs2'

[insns-c_mul]

1.7. Zcmp

The Zcmp extension is a set of instuctions which may be executed as a series of existing 32-bit RISC-V instructions.

This extension reuses some encodings from c.fsdsp. Therefore it is incompatible with Zcd, which is included when C and D extensions are both present.

Zcmp requires the Zca extension.

The PUSH/POP assembly syntax uses several variables, the meaning of which are:

  • reg_list is a list containing 1 to 13 registers (ra and 0 to 12 s registers)

    • valid values: {ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2}, …​, {ra, s0-s8}, {ra, s0-s9}, {ra, s0-s11}

    • note that {ra, s0-s10} is not valid, giving 12 lists not 13 for better encoding

  • stack_adj is the total size of the stack frame.

    • valid values vary with register list length and the specific encoding, see the instruction pages for details.

RV32 RV64 Mnemonic Instruction

yes

yes

cm.push {reg_list}, -stack_adj

[insns-cm_push]

yes

yes

cm.pop {reg_list}, stack_adj

[insns-cm_pop]

yes

yes

cm.popret {reg_list}, stack_adj

[insns-cm_popret]

yes

yes

cm.popretz {reg_list}, stack_adj

[insns-cm_popretz]

yes

yes

cm.mva01s sreg1, sreg2

[insns-cm_mva01s]

yes

yes

cm.mvsa01 sreg1, sreg2

[insns-cm_mvsa01]

1.8. Zcmpe

The Zcmpe extension offers EABI support for register mappings from Zcmp where the x register mapping is different to the UABI.

This extension reuses some encodings from c.fsdsp. Therefore it is incompatible with Zcd, which is included when C and D extensions are both present.

Zcmpe requires the Zca extension.

Note
 The EABI specification is not frozen so these instructions cannot yet be accurately specified.

1.9. Zcmt

Zcmt adds a table jump instuction and also adds the JVT CSR. The JVT CSR requires a state enable if Smstateen is implemented. See [csrs-jvt] for details.

This extension reuses some encodings from c.fsdsp. Therefore it is incompatible with Zcd, which is included when C and D extensions are both present.

Zcmt requires the Zca and Zicsr extensions.

RV32 RV64 Mnemonic Instruction

yes

yes

cm.jt index

[insns-cm_jt]

yes

yes

cm.jalt index

[insns-cm_jalt]