c_lhu.adoc

c.lhu

Synopsis

Load unsigned halfword, 16-bit encoding

Mnemonic

c.lhu rd', uimm(rs1')

Encoding (RV32, RV64)

{reg:[
    { bits:  2, name: 0x0, attr: ['C0'] },
    { bits:  3, name: 'rd\'' },
    { bits:  1, name: 'uimm[1]' },
    { bits:  1, name: 0x0 },
    { bits:  3, name: 'rs1\'' },
    { bits:  3, name: 0x1 },
    { bits:  3, name: 0x4, attr: ['FUNCT3'] },
],config:{bits:16}}

c_lhsh_imm_offset.adoc

Description

This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended to XLEN bits and is written to rd'.

Note	rd' and rs1' are from the standard 8-register set x8-x15.

Prerequisites

None

32-bit equivalent

[insns-lhu]

Operation

//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.

X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);

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