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analysis_arm_cs.c
2434 lines (2365 loc) · 61.1 KB
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analysis_arm_cs.c
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// SPDX-FileCopyrightText: 2013-2021 pancake <pancake@nopcode.org>
// SPDX-License-Identifier: LGPL-3.0-only
#include <rz_analysis.h>
#include <rz_lib.h>
#include <ht_uu.h>
#include <capstone/capstone.h>
#include <capstone/arm.h>
#include <rz_util/rz_assert.h>
#include "./analysis_arm_hacks.inc"
#include "../arch/arm/arm_cs.h"
#include "../arch/arm/arm_accessors32.h"
#include "../arch/arm/arm_accessors64.h"
#include "../../asm/arch/arm/arm_it.h"
typedef struct arm_cs_context_t {
RzArmITContext it;
csh handle;
int omode;
int obits;
} ArmCSContext;
static const char *shift_type_name(arm_shifter type) {
switch (type) {
case ARM_SFT_ASR:
return "asr";
case ARM_SFT_LSL:
return "lsl";
case ARM_SFT_LSR:
return "lsr";
case ARM_SFT_ROR:
return "ror";
case ARM_SFT_RRX:
return "rrx";
case ARM_SFT_ASR_REG:
return "asr_reg";
case ARM_SFT_LSL_REG:
return "lsl_reg";
case ARM_SFT_LSR_REG:
return "lsr_reg";
case ARM_SFT_ROR_REG:
return "ror_reg";
case ARM_SFT_RRX_REG:
return "rrx_reg";
default:
return "";
}
}
static const char *vector_data_type_name(arm_vectordata_type type) {
switch (type) {
case ARM_VECTORDATA_I8:
return "i8";
case ARM_VECTORDATA_I16:
return "i16";
case ARM_VECTORDATA_I32:
return "i32";
case ARM_VECTORDATA_I64:
return "i64";
case ARM_VECTORDATA_S8:
return "s8";
case ARM_VECTORDATA_S16:
return "s16";
case ARM_VECTORDATA_S32:
return "s32";
case ARM_VECTORDATA_S64:
return "s64";
case ARM_VECTORDATA_U8:
return "u8";
case ARM_VECTORDATA_U16:
return "u16";
case ARM_VECTORDATA_U32:
return "u32";
case ARM_VECTORDATA_U64:
return "u64";
case ARM_VECTORDATA_P8:
return "p8";
case ARM_VECTORDATA_F32:
return "f32";
case ARM_VECTORDATA_F64:
return "f64";
case ARM_VECTORDATA_F16F64:
return "f16.f64";
case ARM_VECTORDATA_F64F16:
return "f64.f16";
case ARM_VECTORDATA_F32F16:
return "f32.f16";
case ARM_VECTORDATA_F16F32:
return "f16.f32";
case ARM_VECTORDATA_F64F32:
return "f64.f32";
case ARM_VECTORDATA_F32F64:
return "f32.f64";
case ARM_VECTORDATA_S32F32:
return "s32.f32";
case ARM_VECTORDATA_U32F32:
return "u32.f32";
case ARM_VECTORDATA_F32S32:
return "f32.s32";
case ARM_VECTORDATA_F32U32:
return "f32.u32";
case ARM_VECTORDATA_F64S16:
return "f64.s16";
case ARM_VECTORDATA_F32S16:
return "f32.s16";
case ARM_VECTORDATA_F64S32:
return "f64.s32";
case ARM_VECTORDATA_S16F64:
return "s16.f64";
case ARM_VECTORDATA_S16F32:
return "s16.f64";
case ARM_VECTORDATA_S32F64:
return "s32.f64";
case ARM_VECTORDATA_U16F64:
return "u16.f64";
case ARM_VECTORDATA_U16F32:
return "u16.f32";
case ARM_VECTORDATA_U32F64:
return "u32.f64";
case ARM_VECTORDATA_F64U16:
return "f64.u16";
case ARM_VECTORDATA_F32U16:
return "f32.u16";
case ARM_VECTORDATA_F64U32:
return "f64.u32";
default:
return "";
}
}
static const char *cc_name(arm_cc cc) {
switch (cc) {
case ARM_CC_EQ: // Equal Equal
return "eq";
case ARM_CC_NE: // Not equal Not equal, or unordered
return "ne";
case ARM_CC_HS: // Carry set >, ==, or unordered
return "hs";
case ARM_CC_LO: // Carry clear Less than
return "lo";
case ARM_CC_MI: // Minus, negative Less than
return "mi";
case ARM_CC_PL: // Plus, positive or zero >, ==, or unordered
return "pl";
case ARM_CC_VS: // Overflow Unordered
return "vs";
case ARM_CC_VC: // No overflow Not unordered
return "vc";
case ARM_CC_HI: // Unsigned higher Greater than, or unordered
return "hi";
case ARM_CC_LS: // Unsigned lower or same Less than or equal
return "ls";
case ARM_CC_GE: // Greater than or equal Greater than or equal
return "ge";
case ARM_CC_LT: // Less than Less than, or unordered
return "lt";
case ARM_CC_GT: // Greater than Greater than
return "gt";
case ARM_CC_LE: // Less than or equal <, ==, or unordered
return "le";
default:
return "";
}
}
static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) {
int i;
PJ *pj = pj_new();
if (!pj) {
return;
}
pj_o(pj);
pj_ka(pj, "operands");
cs_arm *x = &insn->detail->arm;
for (i = 0; i < x->op_count; i++) {
cs_arm_op *op = x->operands + i;
pj_o(pj);
switch (op->type) {
case ARM_OP_REG:
pj_ks(pj, "type", "reg");
pj_ks(pj, "value", cs_reg_name(handle, op->reg));
break;
case ARM_OP_IMM:
pj_ks(pj, "type", "imm");
pj_ki(pj, "value", op->imm);
break;
case ARM_OP_MEM:
pj_ks(pj, "type", "mem");
if (op->mem.base != ARM_REG_INVALID) {
pj_ks(pj, "base", cs_reg_name(handle, op->mem.base));
}
if (op->mem.index != ARM_REG_INVALID) {
pj_ks(pj, "index", cs_reg_name(handle, op->mem.index));
}
pj_ki(pj, "scale", op->mem.scale);
pj_ki(pj, "disp", op->mem.disp);
break;
case ARM_OP_FP:
pj_ks(pj, "type", "fp");
pj_kd(pj, "value", op->fp);
break;
case ARM_OP_CIMM:
pj_ks(pj, "type", "cimm");
pj_ki(pj, "value", op->imm);
break;
case ARM_OP_PIMM:
pj_ks(pj, "type", "pimm");
pj_ki(pj, "value", op->imm);
break;
case ARM_OP_SETEND:
pj_ks(pj, "type", "setend");
switch (op->setend) {
case ARM_SETEND_BE:
pj_ks(pj, "value", "be");
break;
case ARM_SETEND_LE:
pj_ks(pj, "value", "le");
break;
default:
pj_ks(pj, "value", "invalid");
break;
}
break;
case ARM_OP_SYSREG: {
pj_ks(pj, "type", "sysreg");
const char *reg = cs_reg_name(handle, op->reg);
if (reg) {
pj_ks(pj, "value", reg);
}
break;
}
default:
pj_ks(pj, "type", "invalid");
break;
}
if (op->shift.type != ARM_SFT_INVALID) {
pj_ko(pj, "shift");
switch (op->shift.type) {
case ARM_SFT_ASR:
case ARM_SFT_LSL:
case ARM_SFT_LSR:
case ARM_SFT_ROR:
case ARM_SFT_RRX:
pj_ks(pj, "type", shift_type_name(op->shift.type));
pj_kn(pj, "value", (ut64)op->shift.value);
break;
case ARM_SFT_ASR_REG:
case ARM_SFT_LSL_REG:
case ARM_SFT_LSR_REG:
case ARM_SFT_ROR_REG:
case ARM_SFT_RRX_REG:
pj_ks(pj, "type", shift_type_name(op->shift.type));
pj_ks(pj, "value", cs_reg_name(handle, op->shift.value));
break;
default:
break;
}
pj_end(pj); /* o shift */
}
if (op->vector_index != -1) {
pj_ki(pj, "vector_index", op->vector_index);
}
if (op->subtracted) {
pj_kb(pj, "subtracted", true);
}
pj_end(pj); /* o operand */
}
pj_end(pj); /* a operands */
if (x->usermode) {
pj_kb(pj, "usermode", true);
}
if (x->update_flags) {
pj_kb(pj, "update_flags", true);
}
if (x->writeback) {
pj_kb(pj, "writeback", true);
}
if (x->vector_size) {
pj_ki(pj, "vector_size", x->vector_size);
}
if (x->vector_data != ARM_VECTORDATA_INVALID) {
pj_ks(pj, "vector_data", vector_data_type_name(x->vector_data));
}
if (x->cps_mode != ARM_CPSMODE_INVALID) {
pj_ki(pj, "cps_mode", x->cps_mode);
}
if (x->cps_flag != ARM_CPSFLAG_INVALID) {
pj_ki(pj, "cps_flag", x->cps_flag);
}
if (x->cc != ARM_CC_INVALID && x->cc != ARM_CC_AL) {
pj_ks(pj, "cc", cc_name(x->cc));
}
if (x->mem_barrier != ARM_MB_INVALID) {
pj_ki(pj, "mem_barrier", x->mem_barrier - 1);
}
pj_end(pj);
rz_strbuf_init(buf);
rz_strbuf_append(buf, pj_string(pj));
pj_free(pj);
}
static const char *cc_name64(arm64_cc cc) {
switch (cc) {
case ARM64_CC_EQ: // Equal
return "eq";
case ARM64_CC_NE: // Not equal: Not equal, or unordered
return "ne";
case ARM64_CC_HS: // Unsigned higher or same: >, ==, or unordered
return "hs";
case ARM64_CC_LO: // Unsigned lower or same: Less than
return "lo";
case ARM64_CC_MI: // Minus, negative: Less than
return "mi";
case ARM64_CC_PL: // Plus, positive or zero: >, ==, or unordered
return "pl";
case ARM64_CC_VS: // Overflow: Unordered
return "vs";
case ARM64_CC_VC: // No overflow: Ordered
return "vc";
case ARM64_CC_HI: // Unsigned higher: Greater than, or unordered
return "hi";
case ARM64_CC_LS: // Unsigned lower or same: Less than or equal
return "ls";
case ARM64_CC_GE: // Greater than or equal: Greater than or equal
return "ge";
case ARM64_CC_LT: // Less than: Less than, or unordered
return "lt";
case ARM64_CC_GT: // Signed greater than: Greater than
return "gt";
case ARM64_CC_LE: // Signed less than or equal: <, ==, or unordered
return "le";
default:
return "";
}
}
static const char *extender_name(arm64_extender extender) {
switch (extender) {
case ARM64_EXT_UXTB:
return "uxtb";
case ARM64_EXT_UXTH:
return "uxth";
case ARM64_EXT_UXTW:
return "uxtw";
case ARM64_EXT_UXTX:
return "uxtx";
case ARM64_EXT_SXTB:
return "sxtb";
case ARM64_EXT_SXTH:
return "sxth";
case ARM64_EXT_SXTW:
return "sxtw";
case ARM64_EXT_SXTX:
return "sxtx";
default:
return "";
}
}
static const char *vas_name(arm64_vas vas) {
switch (vas) {
case ARM64_VAS_8B:
return "8b";
case ARM64_VAS_16B:
return "16b";
case ARM64_VAS_4H:
return "4h";
case ARM64_VAS_8H:
return "8h";
case ARM64_VAS_2S:
return "2s";
case ARM64_VAS_4S:
return "4s";
case ARM64_VAS_2D:
return "2d";
case ARM64_VAS_1D:
return "1d";
case ARM64_VAS_1Q:
return "1q";
#if CS_API_MAJOR > 4
case ARM64_VAS_1B:
return "8b";
case ARM64_VAS_4B:
return "8b";
case ARM64_VAS_2H:
return "2h";
case ARM64_VAS_1H:
return "1h";
case ARM64_VAS_1S:
return "1s";
#endif
default:
return "";
}
}
#if CS_API_MAJOR == 4
static const char *vess_name(arm64_vess vess) {
switch (vess) {
case ARM64_VESS_B:
return "b";
case ARM64_VESS_H:
return "h";
case ARM64_VESS_S:
return "s";
case ARM64_VESS_D:
return "d";
default:
return "";
}
}
#endif
static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) {
int i;
PJ *pj = pj_new();
if (!pj) {
return;
}
pj_o(pj);
pj_ka(pj, "operands");
cs_arm64 *x = &insn->detail->arm64;
for (i = 0; i < x->op_count; i++) {
cs_arm64_op *op = x->operands + i;
pj_o(pj);
switch (op->type) {
case ARM64_OP_REG:
pj_ks(pj, "type", "reg");
pj_ks(pj, "value", cs_reg_name(handle, op->reg));
break;
case ARM64_OP_REG_MRS:
pj_ks(pj, "type", "reg_mrs");
// TODO value
break;
case ARM64_OP_REG_MSR:
pj_ks(pj, "type", "reg_msr");
// TODO value
break;
case ARM64_OP_IMM:
pj_ks(pj, "type", "imm");
pj_kN(pj, "value", op->imm);
break;
case ARM64_OP_MEM:
pj_ks(pj, "type", "mem");
if (op->mem.base != ARM64_REG_INVALID) {
pj_ks(pj, "base", cs_reg_name(handle, op->mem.base));
}
if (op->mem.index != ARM64_REG_INVALID) {
pj_ks(pj, "index", cs_reg_name(handle, op->mem.index));
}
pj_ki(pj, "disp", op->mem.disp);
break;
case ARM64_OP_FP:
pj_ks(pj, "type", "fp");
pj_kd(pj, "value", op->fp);
break;
case ARM64_OP_CIMM:
pj_ks(pj, "type", "cimm");
pj_kN(pj, "value", op->imm);
break;
case ARM64_OP_PSTATE:
pj_ks(pj, "type", "pstate");
switch (op->pstate) {
case ARM64_PSTATE_SPSEL:
pj_ks(pj, "value", "spsel");
break;
case ARM64_PSTATE_DAIFSET:
pj_ks(pj, "value", "daifset");
break;
case ARM64_PSTATE_DAIFCLR:
pj_ks(pj, "value", "daifclr");
break;
default:
pj_ki(pj, "value", op->pstate);
}
break;
case ARM64_OP_SYS:
pj_ks(pj, "type", "sys");
pj_kn(pj, "value", (ut64)op->sys);
break;
case ARM64_OP_PREFETCH:
pj_ks(pj, "type", "prefetch");
pj_ki(pj, "value", op->prefetch - 1);
break;
case ARM64_OP_BARRIER:
pj_ks(pj, "type", "prefetch");
pj_ki(pj, "value", op->barrier - 1);
break;
default:
pj_ks(pj, "type", "invalid");
break;
}
if (op->shift.type != ARM64_SFT_INVALID) {
pj_ko(pj, "shift");
switch (op->shift.type) {
case ARM64_SFT_LSL:
pj_ks(pj, "type", "lsl");
break;
case ARM64_SFT_MSL:
pj_ks(pj, "type", "msl");
break;
case ARM64_SFT_LSR:
pj_ks(pj, "type", "lsr");
break;
case ARM64_SFT_ASR:
pj_ks(pj, "type", "asr");
break;
case ARM64_SFT_ROR:
pj_ks(pj, "type", "ror");
break;
default:
break;
}
pj_kn(pj, "value", (ut64)op->shift.value);
pj_end(pj);
}
if (op->ext != ARM64_EXT_INVALID) {
pj_ks(pj, "ext", extender_name(op->ext));
}
if (op->vector_index != -1) {
pj_ki(pj, "vector_index", op->vector_index);
}
if (op->vas != ARM64_VAS_INVALID) {
pj_ks(pj, "vas", vas_name(op->vas));
}
#if CS_API_MAJOR == 4
if (op->vess != ARM64_VESS_INVALID) {
pj_ks(pj, "vess", vess_name(op->vess));
}
#endif
pj_end(pj);
}
pj_end(pj);
if (x->update_flags) {
pj_kb(pj, "update_flags", true);
}
if (x->writeback) {
pj_kb(pj, "writeback", true);
}
if (x->cc != ARM64_CC_INVALID && x->cc != ARM64_CC_AL && x->cc != ARM64_CC_NV) {
pj_ks(pj, "cc", cc_name64(x->cc));
}
pj_end(pj);
rz_strbuf_init(buf);
rz_strbuf_append(buf, pj_string(pj));
pj_free(pj);
}
static int cond_cs2r2(int cc) {
if (cc == ARM_CC_AL || cc < 0) {
cc = RZ_TYPE_COND_AL;
} else {
switch (cc) {
case ARM_CC_EQ: cc = RZ_TYPE_COND_EQ; break;
case ARM_CC_NE: cc = RZ_TYPE_COND_NE; break;
case ARM_CC_HS: cc = RZ_TYPE_COND_HS; break;
case ARM_CC_LO: cc = RZ_TYPE_COND_LO; break;
case ARM_CC_MI: cc = RZ_TYPE_COND_MI; break;
case ARM_CC_PL: cc = RZ_TYPE_COND_PL; break;
case ARM_CC_VS: cc = RZ_TYPE_COND_VS; break;
case ARM_CC_VC: cc = RZ_TYPE_COND_VC; break;
case ARM_CC_HI: cc = RZ_TYPE_COND_HI; break;
case ARM_CC_LS: cc = RZ_TYPE_COND_LS; break;
case ARM_CC_GE: cc = RZ_TYPE_COND_GE; break;
case ARM_CC_LT: cc = RZ_TYPE_COND_LT; break;
case ARM_CC_GT: cc = RZ_TYPE_COND_GT; break;
case ARM_CC_LE: cc = RZ_TYPE_COND_LE; break;
}
}
return cc;
}
static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) {
csh handle = ctx->handle;
ut64 addr = op->addr;
/* grab family */
if (cs_insn_group(handle, insn, ARM64_GRP_CRYPTO)) {
op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO;
} else if (cs_insn_group(handle, insn, ARM64_GRP_CRC)) {
op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO;
#if CS_API_MAJOR >= 4
} else if (cs_insn_group(handle, insn, ARM64_GRP_PRIVILEGE)) {
op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
#endif
} else if (cs_insn_group(handle, insn, ARM64_GRP_NEON)) {
op->family = RZ_ANALYSIS_OP_FAMILY_MMX;
} else if (cs_insn_group(handle, insn, ARM64_GRP_FPARMV8)) {
op->family = RZ_ANALYSIS_OP_FAMILY_FPU;
} else {
op->family = RZ_ANALYSIS_OP_FAMILY_CPU;
}
op->cond = cond_cs2r2(insn->detail->arm64.cc);
if (op->cond == RZ_TYPE_COND_NV) {
op->type = RZ_ANALYSIS_OP_TYPE_NOP;
return;
}
switch (insn->detail->arm64.cc) {
case ARM64_CC_GE:
case ARM64_CC_GT:
case ARM64_CC_LE:
case ARM64_CC_LT:
op->sign = true;
break;
default:
break;
}
switch (insn->id) {
#if CS_API_MAJOR > 4
case ARM64_INS_PACDA:
case ARM64_INS_PACDB:
case ARM64_INS_PACDZA:
case ARM64_INS_PACDZB:
case ARM64_INS_PACGA:
case ARM64_INS_PACIA:
case ARM64_INS_PACIA1716:
case ARM64_INS_PACIASP:
case ARM64_INS_PACIAZ:
case ARM64_INS_PACIB:
case ARM64_INS_PACIB1716:
case ARM64_INS_PACIBSP:
case ARM64_INS_PACIBZ:
case ARM64_INS_PACIZA:
case ARM64_INS_PACIZB:
case ARM64_INS_AUTDA:
case ARM64_INS_AUTDB:
case ARM64_INS_AUTDZA:
case ARM64_INS_AUTDZB:
case ARM64_INS_AUTIA:
case ARM64_INS_AUTIA1716:
case ARM64_INS_AUTIASP:
case ARM64_INS_AUTIAZ:
case ARM64_INS_AUTIB:
case ARM64_INS_AUTIB1716:
case ARM64_INS_AUTIBSP:
case ARM64_INS_AUTIBZ:
case ARM64_INS_AUTIZA:
case ARM64_INS_AUTIZB:
case ARM64_INS_XPACD:
case ARM64_INS_XPACI:
case ARM64_INS_XPACLRI:
op->type = RZ_ANALYSIS_OP_TYPE_CMP;
op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
break;
#endif
case ARM64_INS_SVC:
op->type = RZ_ANALYSIS_OP_TYPE_SWI;
op->val = IMM64(0);
break;
case ARM64_INS_ADRP:
case ARM64_INS_ADR:
op->type = RZ_ANALYSIS_OP_TYPE_LEA;
op->ptr = IMM64(1);
break;
case ARM64_INS_NOP:
op->type = RZ_ANALYSIS_OP_TYPE_NOP;
op->cycles = 1;
break;
case ARM64_INS_SUB:
if (ISREG64(0) && REGID64(0) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_INC;
if (ISIMM64(1)) {
// sub sp, 0x54
op->stackptr = IMM(1);
} else if (ISIMM64(2) && ISREG64(1) && REGID64(1) == ARM64_REG_SP) {
// sub sp, sp, 0x10
op->stackptr = IMM64(2);
}
op->val = op->stackptr;
} else {
op->stackop = RZ_ANALYSIS_STACK_RESET;
op->stackptr = 0;
}
op->cycles = 1;
/* fallthru */
case ARM64_INS_MSUB:
op->type = RZ_ANALYSIS_OP_TYPE_SUB;
break;
case ARM64_INS_FDIV:
case ARM64_INS_SDIV:
case ARM64_INS_UDIV:
op->cycles = 4;
op->type = RZ_ANALYSIS_OP_TYPE_DIV;
break;
case ARM64_INS_MUL:
case ARM64_INS_SMULL:
case ARM64_INS_FMUL:
case ARM64_INS_UMULL:
/* TODO: if next instruction is also a MUL, cycles are /=2 */
/* also known as Register Indexing Addressing */
op->cycles = 4;
op->type = RZ_ANALYSIS_OP_TYPE_MUL;
break;
case ARM64_INS_ADD:
if (ISREG64(0) && REGID64(0) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_INC;
if (ISIMM64(1)) {
// add sp, 0x54
op->stackptr = -IMM(1);
} else if (ISIMM64(2) && ISREG64(1) && REGID64(1) == ARM64_REG_SP) {
// add sp, sp, 0x10
op->stackptr = -IMM64(2);
}
op->val = op->stackptr;
} else {
op->stackop = RZ_ANALYSIS_STACK_RESET;
op->stackptr = 0;
if (ISIMM64(2)) {
op->val = IMM64(2);
}
}
op->cycles = 1;
/* fallthru */
case ARM64_INS_ADC:
// case ARM64_INS_ADCS:
case ARM64_INS_UMADDL:
case ARM64_INS_SMADDL:
case ARM64_INS_FMADD:
case ARM64_INS_MADD:
op->type = RZ_ANALYSIS_OP_TYPE_ADD;
break;
case ARM64_INS_CSEL:
case ARM64_INS_FCSEL:
case ARM64_INS_CSET:
case ARM64_INS_CINC:
op->type = RZ_ANALYSIS_OP_TYPE_CMOV;
break;
case ARM64_INS_MOV:
if (REGID64(0) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_RESET;
op->stackptr = 0;
}
if (ISIMM64(1)) {
op->val = IMM64(1);
}
op->cycles = 1;
/* fallthru */
case ARM64_INS_MOVI:
case ARM64_INS_MOVK:
case ARM64_INS_MOVN:
case ARM64_INS_SMOV:
case ARM64_INS_UMOV:
case ARM64_INS_FMOV:
case ARM64_INS_SBFX:
case ARM64_INS_UBFX:
case ARM64_INS_UBFM:
case ARM64_INS_SBFIZ:
case ARM64_INS_UBFIZ:
case ARM64_INS_BIC:
case ARM64_INS_BFI:
case ARM64_INS_BFXIL:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
break;
case ARM64_INS_MRS:
case ARM64_INS_MSR:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
break;
case ARM64_INS_MOVZ:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
op->ptr = 0LL;
op->ptrsize = 8;
op->val = IMM64(1);
break;
case ARM64_INS_UXTB:
case ARM64_INS_SXTB:
op->type = RZ_ANALYSIS_OP_TYPE_CAST;
op->ptr = 0LL;
op->ptrsize = 1;
break;
case ARM64_INS_UXTH:
case ARM64_INS_SXTH:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
op->ptr = 0LL;
op->ptrsize = 2;
break;
case ARM64_INS_UXTW:
case ARM64_INS_SXTW:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
op->ptr = 0LL;
op->ptrsize = 4;
break;
case ARM64_INS_BRK:
case ARM64_INS_HLT:
op->type = RZ_ANALYSIS_OP_TYPE_TRAP;
// hlt stops the process, not skips some cycles like in x86
break;
case ARM64_INS_DMB:
case ARM64_INS_DSB:
case ARM64_INS_ISB:
op->family = RZ_ANALYSIS_OP_FAMILY_THREAD;
// intentional fallthrough
case ARM64_INS_IC: // instruction cache invalidate
case ARM64_INS_DC: // data cache invalidate
op->type = RZ_ANALYSIS_OP_TYPE_SYNC; // or cache
break;
// XXX unimplemented instructions
case ARM64_INS_DUP:
case ARM64_INS_XTN:
case ARM64_INS_XTN2:
case ARM64_INS_REV64:
case ARM64_INS_EXT:
case ARM64_INS_INS:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
break;
case ARM64_INS_LSL:
op->cycles = 1;
/* fallthru */
case ARM64_INS_SHL:
case ARM64_INS_USHLL:
op->type = RZ_ANALYSIS_OP_TYPE_SHL;
break;
case ARM64_INS_LSR:
op->cycles = 1;
op->type = RZ_ANALYSIS_OP_TYPE_SHR;
break;
case ARM64_INS_ASR:
op->cycles = 1;
op->type = RZ_ANALYSIS_OP_TYPE_SAR;
break;
case ARM64_INS_NEG:
#if CS_API_MAJOR > 3
case ARM64_INS_NEGS:
#endif
op->type = RZ_ANALYSIS_OP_TYPE_NOT;
break;
case ARM64_INS_FCMP:
case ARM64_INS_CCMP:
case ARM64_INS_CCMN:
case ARM64_INS_CMP:
case ARM64_INS_CMN:
case ARM64_INS_TST:
op->type = RZ_ANALYSIS_OP_TYPE_CMP;
break;
case ARM64_INS_ROR:
op->cycles = 1;
op->type = RZ_ANALYSIS_OP_TYPE_ROR;
break;
case ARM64_INS_AND:
op->type = RZ_ANALYSIS_OP_TYPE_AND;
break;
case ARM64_INS_ORR:
case ARM64_INS_ORN:
op->type = RZ_ANALYSIS_OP_TYPE_OR;
if (ISIMM64(2)) {
op->val = IMM64(2);
}
break;
case ARM64_INS_EOR:
case ARM64_INS_EON:
op->type = RZ_ANALYSIS_OP_TYPE_XOR;
break;
case ARM64_INS_STRB:
case ARM64_INS_STURB:
case ARM64_INS_STUR:
case ARM64_INS_STR:
case ARM64_INS_STP:
case ARM64_INS_STNP:
case ARM64_INS_STXR:
case ARM64_INS_STXRH:
case ARM64_INS_STLXR:
case ARM64_INS_STLXRH:
case ARM64_INS_STXRB:
op->type = RZ_ANALYSIS_OP_TYPE_STORE;
if (ISPREINDEX64() && REGBASE64(2) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_INC;
op->stackptr = -MEMDISP64(2);
} else if (ISPOSTINDEX64() && REGID64(2) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_INC;
op->stackptr = -IMM64(3);
} else if (ISPREINDEX64() && REGBASE64(1) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_INC;
op->stackptr = -MEMDISP64(1);
} else if (ISPOSTINDEX64() && REGID64(1) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_INC;
op->stackptr = -IMM64(2);
}
break;
case ARM64_INS_LDUR:
case ARM64_INS_LDURB:
case ARM64_INS_LDRSW:
case ARM64_INS_LDRSB:
case ARM64_INS_LDRSH:
case ARM64_INS_LDR:
case ARM64_INS_LDURSW:
case ARM64_INS_LDP:
case ARM64_INS_LDNP:
case ARM64_INS_LDPSW:
case ARM64_INS_LDRH:
case ARM64_INS_LDRB:
if (ISPREINDEX64() && REGBASE64(2) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_INC;
op->stackptr = -MEMDISP64(2);
} else if (ISPOSTINDEX64() && REGID64(2) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_INC;
op->stackptr = -IMM64(3);
} else if (ISPREINDEX64() && REGBASE64(1) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_INC;
op->stackptr = -MEMDISP64(1);
} else if (ISPOSTINDEX64() && REGID64(1) == ARM64_REG_SP) {
op->stackop = RZ_ANALYSIS_STACK_INC;
op->stackptr = -IMM64(2);
}
if (REGID(0) == ARM_REG_PC) {
op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
if (insn->detail->arm.cc != ARM_CC_AL) {
// op->type = RZ_ANALYSIS_OP_TYPE_MCJMP;
op->type = RZ_ANALYSIS_OP_TYPE_UCJMP;
}
} else {
op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
}
switch (insn->id) {
case ARM64_INS_LDPSW:
case ARM64_INS_LDRSW:
case ARM64_INS_LDRSH:
case ARM64_INS_LDRSB:
op->sign = true;
break;
}
if (REGBASE64(1) == ARM64_REG_X29) {
op->stackop = RZ_ANALYSIS_STACK_GET;
op->stackptr = 0;
op->ptr = MEMDISP64(1);
} else {
if (ISIMM64(1)) {
op->type = RZ_ANALYSIS_OP_TYPE_LEA;
op->ptr = IMM64(1);
op->refptr = 8;
} else {
int d = (int)MEMDISP64(1);
op->ptr = (d < 0) ? -d : d;
op->refptr = 4;
}
}
break;
#if CS_API_MAJOR > 4
case ARM64_INS_BLRAA:
case ARM64_INS_BLRAAZ:
case ARM64_INS_BLRAB:
case ARM64_INS_BLRABZ:
op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
op->type = RZ_ANALYSIS_OP_TYPE_RCALL;
break;
case ARM64_INS_BRAA:
case ARM64_INS_BRAAZ:
case ARM64_INS_BRAB:
case ARM64_INS_BRABZ:
op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
op->type = RZ_ANALYSIS_OP_TYPE_RJMP;
break;
case ARM64_INS_LDRAA:
case ARM64_INS_LDRAB:
op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
break;
case ARM64_INS_RETAA:
case ARM64_INS_RETAB:
case ARM64_INS_ERETAA:
case ARM64_INS_ERETAB:
op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
op->type = RZ_ANALYSIS_OP_TYPE_RET;
break;
#endif
case ARM64_INS_ERET:
op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
op->type = RZ_ANALYSIS_OP_TYPE_RET;
break;
case ARM64_INS_RET:
op->type = RZ_ANALYSIS_OP_TYPE_RET;
break;
case ARM64_INS_BL: // bl 0x89480
op->type = RZ_ANALYSIS_OP_TYPE_CALL;
op->jump = IMM64(0);
op->fail = addr + 4;
break;
case ARM64_INS_BLR: // blr x0
op->type = RZ_ANALYSIS_OP_TYPE_RCALL;
op->reg = cs_reg_name(handle, REGID64(0));
op->fail = addr + 4;
// op->jump = IMM64(0);
break;
case ARM64_INS_CBZ:
case ARM64_INS_CBNZ:
op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
op->jump = IMM64(1);
op->fail = addr + op->size;
break;
case ARM64_INS_TBZ:
case ARM64_INS_TBNZ:
op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
op->jump = IMM64(2);
op->fail = addr + op->size;
break;