forked from illumos/illumos-gate
/
nxge_rxdma.c
5007 lines (4311 loc) · 131 KB
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nxge_rxdma.c
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/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://www.opensolaris.org/os/licensing.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include <sys/nxge/nxge_impl.h>
#include <sys/nxge/nxge_rxdma.h>
#include <sys/nxge/nxge_hio.h>
#if !defined(_BIG_ENDIAN)
#include <npi_rx_rd32.h>
#endif
#include <npi_rx_rd64.h>
#include <npi_rx_wr64.h>
#define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \
(rdcgrp + nxgep->pt_config.hw_config.def_mac_rxdma_grpid)
#define NXGE_ACTUAL_RDC(nxgep, rdc) \
(rdc + nxgep->pt_config.hw_config.start_rdc)
/*
* Globals: tunable parameters (/etc/system or adb)
*
*/
extern uint32_t nxge_rbr_size;
extern uint32_t nxge_rcr_size;
extern uint32_t nxge_rbr_spare_size;
extern uint16_t nxge_rdc_buf_offset;
extern uint32_t nxge_mblks_pending;
/*
* Tunable to reduce the amount of time spent in the
* ISR doing Rx Processing.
*/
extern uint32_t nxge_max_rx_pkts;
/*
* Tunables to manage the receive buffer blocks.
*
* nxge_rx_threshold_hi: copy all buffers.
* nxge_rx_bcopy_size_type: receive buffer block size type.
* nxge_rx_threshold_lo: copy only up to tunable block size type.
*/
extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi;
extern nxge_rxbuf_type_t nxge_rx_buf_size_type;
extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo;
extern uint32_t nxge_cksum_offload;
static nxge_status_t nxge_map_rxdma(p_nxge_t, int);
static void nxge_unmap_rxdma(p_nxge_t, int);
static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t);
static nxge_status_t nxge_rxdma_hw_start(p_nxge_t, int);
static void nxge_rxdma_hw_stop(p_nxge_t, int);
static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t,
p_nxge_dma_common_t *, p_rx_rbr_ring_t *,
uint32_t,
p_nxge_dma_common_t *, p_rx_rcr_ring_t *,
p_rx_mbox_t *);
static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t,
p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t);
static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t,
uint16_t,
p_nxge_dma_common_t *, p_rx_rbr_ring_t *,
p_rx_rcr_ring_t *, p_rx_mbox_t *);
static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t,
p_rx_rcr_ring_t, p_rx_mbox_t);
static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t,
uint16_t,
p_nxge_dma_common_t *,
p_rx_rbr_ring_t *, uint32_t);
static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t,
p_rx_rbr_ring_t);
static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t,
p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t);
static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t);
static mblk_t *
nxge_rx_pkts(p_nxge_t, p_rx_rcr_ring_t, rx_dma_ctl_stat_t, int);
static void nxge_receive_packet(p_nxge_t,
p_rx_rcr_ring_t,
p_rcr_entry_t,
boolean_t *,
mblk_t **, mblk_t **);
nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t);
static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t);
static void nxge_freeb(p_rx_msg_t);
static nxge_status_t nxge_rx_err_evnts(p_nxge_t, int, rx_dma_ctl_stat_t);
static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t,
uint32_t, uint32_t);
static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t,
p_rx_rbr_ring_t);
static nxge_status_t
nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t);
nxge_status_t
nxge_rx_port_fatal_err_recover(p_nxge_t);
static void nxge_rxdma_databuf_free(p_rx_rbr_ring_t);
nxge_status_t
nxge_init_rxdma_channels(p_nxge_t nxgep)
{
nxge_grp_set_t *set = &nxgep->rx_set;
int i, count, channel;
nxge_grp_t *group;
dc_map_t map;
int dev_gindex;
NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels"));
if (!isLDOMguest(nxgep)) {
if (nxge_rxdma_hw_start_common(nxgep) != NXGE_OK) {
cmn_err(CE_NOTE, "hw_start_common");
return (NXGE_ERROR);
}
}
/*
* NXGE_LOGICAL_GROUP_MAX > NXGE_MAX_RDC_GROUPS (8)
* We only have 8 hardware RDC tables, but we may have
* up to 16 logical (software-defined) groups of RDCS,
* if we make use of layer 3 & 4 hardware classification.
*/
for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) {
if ((1 << i) & set->lg.map) {
group = set->group[i];
dev_gindex =
nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i;
map = nxgep->pt_config.rdc_grps[dev_gindex].map;
for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
if ((1 << channel) & map) {
if ((nxge_grp_dc_add(nxgep,
group, VP_BOUND_RX, channel)))
goto init_rxdma_channels_exit;
}
}
}
if (++count == set->lg.count)
break;
}
NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels"));
return (NXGE_OK);
init_rxdma_channels_exit:
for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) {
if ((1 << i) & set->lg.map) {
group = set->group[i];
dev_gindex =
nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i;
map = nxgep->pt_config.rdc_grps[dev_gindex].map;
for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
if ((1 << channel) & map) {
nxge_grp_dc_remove(nxgep,
VP_BOUND_RX, channel);
}
}
}
if (++count == set->lg.count)
break;
}
NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels"));
return (NXGE_ERROR);
}
nxge_status_t
nxge_init_rxdma_channel(p_nxge_t nxge, int channel)
{
nxge_status_t status;
NXGE_DEBUG_MSG((nxge, MEM2_CTL, "==> nxge_init_rxdma_channel"));
status = nxge_map_rxdma(nxge, channel);
if (status != NXGE_OK) {
NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL,
"<== nxge_init_rxdma: status 0x%x", status));
return (status);
}
#if defined(sun4v)
if (isLDOMguest(nxge)) {
/* set rcr_ring */
p_rx_rcr_ring_t ring = nxge->rx_rcr_rings->rcr_rings[channel];
status = nxge_hio_rxdma_bind_intr(nxge, ring, channel);
if (status != NXGE_OK) {
nxge_unmap_rxdma(nxge, channel);
return (status);
}
}
#endif
status = nxge_rxdma_hw_start(nxge, channel);
if (status != NXGE_OK) {
nxge_unmap_rxdma(nxge, channel);
}
if (!nxge->statsp->rdc_ksp[channel])
nxge_setup_rdc_kstats(nxge, channel);
NXGE_DEBUG_MSG((nxge, MEM2_CTL,
"<== nxge_init_rxdma_channel: status 0x%x", status));
return (status);
}
void
nxge_uninit_rxdma_channels(p_nxge_t nxgep)
{
nxge_grp_set_t *set = &nxgep->rx_set;
int rdc;
NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels"));
if (set->owned.map == 0) {
NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
"nxge_uninit_rxdma_channels: no channels"));
return;
}
for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
if ((1 << rdc) & set->owned.map) {
nxge_grp_dc_remove(nxgep, VP_BOUND_RX, rdc);
}
}
NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uninit_rxdma_channels"));
}
void
nxge_uninit_rxdma_channel(p_nxge_t nxgep, int channel)
{
NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channel"));
if (nxgep->statsp->rdc_ksp[channel]) {
kstat_delete(nxgep->statsp->rdc_ksp[channel]);
nxgep->statsp->rdc_ksp[channel] = 0;
}
nxge_rxdma_hw_stop(nxgep, channel);
nxge_unmap_rxdma(nxgep, channel);
NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uinit_rxdma_channel"));
}
nxge_status_t
nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel)
{
npi_handle_t handle;
npi_status_t rs = NPI_SUCCESS;
nxge_status_t status = NXGE_OK;
NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_reset_rxdma_channel"));
handle = NXGE_DEV_NPI_HANDLE(nxgep);
rs = npi_rxdma_cfg_rdc_reset(handle, channel);
if (rs != NPI_SUCCESS) {
status = NXGE_ERROR | rs;
}
NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel"));
return (status);
}
void
nxge_rxdma_regs_dump_channels(p_nxge_t nxgep)
{
nxge_grp_set_t *set = &nxgep->rx_set;
int rdc;
NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels"));
if (!isLDOMguest(nxgep)) {
npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep);
(void) npi_rxdma_dump_fzc_regs(handle);
}
if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) {
NXGE_DEBUG_MSG((nxgep, TX_CTL,
"nxge_rxdma_regs_dump_channels: "
"NULL ring pointer(s)"));
return;
}
if (set->owned.map == 0) {
NXGE_DEBUG_MSG((nxgep, RX_CTL,
"nxge_rxdma_regs_dump_channels: no channels"));
return;
}
for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
if ((1 << rdc) & set->owned.map) {
rx_rbr_ring_t *ring =
nxgep->rx_rbr_rings->rbr_rings[rdc];
if (ring) {
(void) nxge_dump_rxdma_channel(nxgep, rdc);
}
}
}
NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump"));
}
nxge_status_t
nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel)
{
npi_handle_t handle;
npi_status_t rs = NPI_SUCCESS;
nxge_status_t status = NXGE_OK;
NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel"));
handle = NXGE_DEV_NPI_HANDLE(nxgep);
rs = npi_rxdma_dump_rdc_regs(handle, channel);
if (rs != NPI_SUCCESS) {
status = NXGE_ERROR | rs;
}
NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel"));
return (status);
}
nxge_status_t
nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel,
p_rx_dma_ent_msk_t mask_p)
{
npi_handle_t handle;
npi_status_t rs = NPI_SUCCESS;
nxge_status_t status = NXGE_OK;
NXGE_DEBUG_MSG((nxgep, DMA_CTL,
"<== nxge_init_rxdma_channel_event_mask"));
handle = NXGE_DEV_NPI_HANDLE(nxgep);
rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p);
if (rs != NPI_SUCCESS) {
status = NXGE_ERROR | rs;
}
return (status);
}
nxge_status_t
nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel,
p_rx_dma_ctl_stat_t cs_p)
{
npi_handle_t handle;
npi_status_t rs = NPI_SUCCESS;
nxge_status_t status = NXGE_OK;
NXGE_DEBUG_MSG((nxgep, DMA_CTL,
"<== nxge_init_rxdma_channel_cntl_stat"));
handle = NXGE_DEV_NPI_HANDLE(nxgep);
rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p);
if (rs != NPI_SUCCESS) {
status = NXGE_ERROR | rs;
}
return (status);
}
/*
* nxge_rxdma_cfg_rdcgrp_default_rdc
*
* Set the default RDC for an RDC Group (Table)
*
* Arguments:
* nxgep
* rdcgrp The group to modify
* rdc The new default RDC.
*
* Notes:
*
* NPI/NXGE function calls:
* npi_rxdma_cfg_rdc_table_default_rdc()
*
* Registers accessed:
* RDC_TBL_REG: FZC_ZCP + 0x10000
*
* Context:
* Service domain
*/
nxge_status_t
nxge_rxdma_cfg_rdcgrp_default_rdc(
p_nxge_t nxgep,
uint8_t rdcgrp,
uint8_t rdc)
{
npi_handle_t handle;
npi_status_t rs = NPI_SUCCESS;
p_nxge_dma_pt_cfg_t p_dma_cfgp;
p_nxge_rdc_grp_t rdc_grp_p;
uint8_t actual_rdcgrp, actual_rdc;
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
" ==> nxge_rxdma_cfg_rdcgrp_default_rdc"));
p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
handle = NXGE_DEV_NPI_HANDLE(nxgep);
/*
* This has to be rewritten. Do we even allow this anymore?
*/
rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp];
RDC_MAP_IN(rdc_grp_p->map, rdc);
rdc_grp_p->def_rdc = rdc;
actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp);
actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc);
rs = npi_rxdma_cfg_rdc_table_default_rdc(
handle, actual_rdcgrp, actual_rdc);
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
" <== nxge_rxdma_cfg_rdcgrp_default_rdc"));
return (NXGE_OK);
}
nxge_status_t
nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc)
{
npi_handle_t handle;
uint8_t actual_rdc;
npi_status_t rs = NPI_SUCCESS;
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
" ==> nxge_rxdma_cfg_port_default_rdc"));
handle = NXGE_DEV_NPI_HANDLE(nxgep);
actual_rdc = rdc; /* XXX Hack! */
rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc);
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
" <== nxge_rxdma_cfg_port_default_rdc"));
return (NXGE_OK);
}
nxge_status_t
nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel,
uint16_t pkts)
{
npi_status_t rs = NPI_SUCCESS;
npi_handle_t handle;
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
" ==> nxge_rxdma_cfg_rcr_threshold"));
handle = NXGE_DEV_NPI_HANDLE(nxgep);
rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts);
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold"));
return (NXGE_OK);
}
nxge_status_t
nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel,
uint16_t tout, uint8_t enable)
{
npi_status_t rs = NPI_SUCCESS;
npi_handle_t handle;
NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout"));
handle = NXGE_DEV_NPI_HANDLE(nxgep);
if (enable == 0) {
rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel);
} else {
rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel,
tout);
}
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout"));
return (NXGE_OK);
}
nxge_status_t
nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel,
p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p)
{
npi_handle_t handle;
rdc_desc_cfg_t rdc_desc;
p_rcrcfig_b_t cfgb_p;
npi_status_t rs = NPI_SUCCESS;
NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel"));
handle = NXGE_DEV_NPI_HANDLE(nxgep);
/*
* Use configuration data composed at init time.
* Write to hardware the receive ring configurations.
*/
rdc_desc.mbox_enable = 1;
rdc_desc.mbox_addr = mbox_p->mbox_addr;
NXGE_DEBUG_MSG((nxgep, RX_CTL,
"==> nxge_enable_rxdma_channel: mboxp $%p($%p)",
mbox_p->mbox_addr, rdc_desc.mbox_addr));
rdc_desc.rbr_len = rbr_p->rbb_max;
rdc_desc.rbr_addr = rbr_p->rbr_addr;
switch (nxgep->rx_bksize_code) {
case RBR_BKSIZE_4K:
rdc_desc.page_size = SIZE_4KB;
break;
case RBR_BKSIZE_8K:
rdc_desc.page_size = SIZE_8KB;
break;
case RBR_BKSIZE_16K:
rdc_desc.page_size = SIZE_16KB;
break;
case RBR_BKSIZE_32K:
rdc_desc.page_size = SIZE_32KB;
break;
}
rdc_desc.size0 = rbr_p->npi_pkt_buf_size0;
rdc_desc.valid0 = 1;
rdc_desc.size1 = rbr_p->npi_pkt_buf_size1;
rdc_desc.valid1 = 1;
rdc_desc.size2 = rbr_p->npi_pkt_buf_size2;
rdc_desc.valid2 = 1;
rdc_desc.full_hdr = rcr_p->full_hdr_flag;
rdc_desc.offset = rcr_p->sw_priv_hdr_len;
rdc_desc.rcr_len = rcr_p->comp_size;
rdc_desc.rcr_addr = rcr_p->rcr_addr;
cfgb_p = &(rcr_p->rcr_cfgb);
rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres;
/* For now, disable this timeout in a guest domain. */
if (isLDOMguest(nxgep)) {
rdc_desc.rcr_timeout = 0;
rdc_desc.rcr_timeout_enable = 0;
} else {
rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout;
rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout;
}
NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: "
"rbr_len qlen %d pagesize code %d rcr_len %d",
rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len));
NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: "
"size 0 %d size 1 %d size 2 %d",
rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1,
rbr_p->npi_pkt_buf_size2));
if (nxgep->niu_hw_type == NIU_HW_TYPE_RF)
rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc,
&rdc_desc, B_TRUE);
else
rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc,
&rdc_desc, B_FALSE);
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
/*
* Enable the timeout and threshold.
*/
rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel,
rdc_desc.rcr_threshold);
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel,
rdc_desc.rcr_timeout);
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
if (!isLDOMguest(nxgep)) {
/* Enable the DMA */
rs = npi_rxdma_cfg_rdc_enable(handle, channel);
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
}
/* Kick the DMA engine. */
npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max);
if (!isLDOMguest(nxgep)) {
/* Clear the rbr empty bit */
(void) npi_rxdma_channel_rbr_empty_clear(handle, channel);
}
NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel"));
return (NXGE_OK);
}
nxge_status_t
nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel)
{
npi_handle_t handle;
npi_status_t rs = NPI_SUCCESS;
NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel"));
handle = NXGE_DEV_NPI_HANDLE(nxgep);
/* disable the DMA */
rs = npi_rxdma_cfg_rdc_disable(handle, channel);
if (rs != NPI_SUCCESS) {
NXGE_DEBUG_MSG((nxgep, RX_CTL,
"<== nxge_disable_rxdma_channel:failed (0x%x)",
rs));
return (NXGE_ERROR | rs);
}
NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel"));
return (NXGE_OK);
}
nxge_status_t
nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel)
{
npi_handle_t handle;
nxge_status_t status = NXGE_OK;
NXGE_DEBUG_MSG((nxgep, DMA_CTL,
"<== nxge_init_rxdma_channel_rcrflush"));
handle = NXGE_DEV_NPI_HANDLE(nxgep);
npi_rxdma_rdc_rcr_flush(handle, channel);
NXGE_DEBUG_MSG((nxgep, DMA_CTL,
"<== nxge_init_rxdma_channel_rcrflsh"));
return (status);
}
#define MID_INDEX(l, r) ((r + l + 1) >> 1)
#define TO_LEFT -1
#define TO_RIGHT 1
#define BOTH_RIGHT (TO_RIGHT + TO_RIGHT)
#define BOTH_LEFT (TO_LEFT + TO_LEFT)
#define IN_MIDDLE (TO_RIGHT + TO_LEFT)
#define NO_HINT 0xffffffff
/*ARGSUSED*/
nxge_status_t
nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p,
uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp,
uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index)
{
int bufsize;
uint64_t pktbuf_pp;
uint64_t dvma_addr;
rxring_info_t *ring_info;
int base_side, end_side;
int r_index, l_index, anchor_index;
int found, search_done;
uint32_t offset, chunk_size, block_size, page_size_mask;
uint32_t chunk_index, block_index, total_index;
int max_iterations, iteration;
rxbuf_index_info_t *bufinfo;
NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp"));
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d",
pkt_buf_addr_pp,
pktbufsz_type));
#if defined(__i386)
pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp;
#else
pktbuf_pp = (uint64_t)pkt_buf_addr_pp;
#endif
switch (pktbufsz_type) {
case 0:
bufsize = rbr_p->pkt_buf_size0;
break;
case 1:
bufsize = rbr_p->pkt_buf_size1;
break;
case 2:
bufsize = rbr_p->pkt_buf_size2;
break;
case RCR_SINGLE_BLOCK:
bufsize = 0;
anchor_index = 0;
break;
default:
return (NXGE_ERROR);
}
if (rbr_p->num_blocks == 1) {
anchor_index = 0;
ring_info = rbr_p->ring_info;
bufinfo = (rxbuf_index_info_t *)ring_info->buffer;
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: (found, 1 block) "
"buf_pp $%p btype %d anchor_index %d "
"bufinfo $%p",
pkt_buf_addr_pp,
pktbufsz_type,
anchor_index,
bufinfo));
goto found_index;
}
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: "
"buf_pp $%p btype %d anchor_index %d",
pkt_buf_addr_pp,
pktbufsz_type,
anchor_index));
ring_info = rbr_p->ring_info;
found = B_FALSE;
bufinfo = (rxbuf_index_info_t *)ring_info->buffer;
iteration = 0;
max_iterations = ring_info->max_iterations;
/*
* First check if this block has been seen
* recently. This is indicated by a hint which
* is initialized when the first buffer of the block
* is seen. The hint is reset when the last buffer of
* the block has been processed.
* As three block sizes are supported, three hints
* are kept. The idea behind the hints is that once
* the hardware uses a block for a buffer of that
* size, it will use it exclusively for that size
* and will use it until it is exhausted. It is assumed
* that there would a single block being used for the same
* buffer sizes at any given time.
*/
if (ring_info->hint[pktbufsz_type] != NO_HINT) {
anchor_index = ring_info->hint[pktbufsz_type];
dvma_addr = bufinfo[anchor_index].dvma_addr;
chunk_size = bufinfo[anchor_index].buf_size;
if ((pktbuf_pp >= dvma_addr) &&
(pktbuf_pp < (dvma_addr + chunk_size))) {
found = B_TRUE;
/*
* check if this is the last buffer in the block
* If so, then reset the hint for the size;
*/
if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size))
ring_info->hint[pktbufsz_type] = NO_HINT;
}
}
if (found == B_FALSE) {
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: (!found)"
"buf_pp $%p btype %d anchor_index %d",
pkt_buf_addr_pp,
pktbufsz_type,
anchor_index));
/*
* This is the first buffer of the block of this
* size. Need to search the whole information
* array.
* the search algorithm uses a binary tree search
* algorithm. It assumes that the information is
* already sorted with increasing order
* info[0] < info[1] < info[2] .... < info[n-1]
* where n is the size of the information array
*/
r_index = rbr_p->num_blocks - 1;
l_index = 0;
search_done = B_FALSE;
anchor_index = MID_INDEX(r_index, l_index);
while (search_done == B_FALSE) {
if ((r_index == l_index) ||
(iteration >= max_iterations))
search_done = B_TRUE;
end_side = TO_RIGHT; /* to the right */
base_side = TO_LEFT; /* to the left */
/* read the DVMA address information and sort it */
dvma_addr = bufinfo[anchor_index].dvma_addr;
chunk_size = bufinfo[anchor_index].buf_size;
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: (searching)"
"buf_pp $%p btype %d "
"anchor_index %d chunk_size %d dvmaaddr $%p",
pkt_buf_addr_pp,
pktbufsz_type,
anchor_index,
chunk_size,
dvma_addr));
if (pktbuf_pp >= dvma_addr)
base_side = TO_RIGHT; /* to the right */
if (pktbuf_pp < (dvma_addr + chunk_size))
end_side = TO_LEFT; /* to the left */
switch (base_side + end_side) {
case IN_MIDDLE:
/* found */
found = B_TRUE;
search_done = B_TRUE;
if ((pktbuf_pp + bufsize) <
(dvma_addr + chunk_size))
ring_info->hint[pktbufsz_type] =
bufinfo[anchor_index].buf_index;
break;
case BOTH_RIGHT:
/* not found: go to the right */
l_index = anchor_index + 1;
anchor_index = MID_INDEX(r_index, l_index);
break;
case BOTH_LEFT:
/* not found: go to the left */
r_index = anchor_index - 1;
anchor_index = MID_INDEX(r_index, l_index);
break;
default: /* should not come here */
return (NXGE_ERROR);
}
iteration++;
}
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: (search done)"
"buf_pp $%p btype %d anchor_index %d",
pkt_buf_addr_pp,
pktbufsz_type,
anchor_index));
}
if (found == B_FALSE) {
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: (search failed)"
"buf_pp $%p btype %d anchor_index %d",
pkt_buf_addr_pp,
pktbufsz_type,
anchor_index));
return (NXGE_ERROR);
}
found_index:
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: (FOUND1)"
"buf_pp $%p btype %d bufsize %d anchor_index %d",
pkt_buf_addr_pp,
pktbufsz_type,
bufsize,
anchor_index));
/* index of the first block in this chunk */
chunk_index = bufinfo[anchor_index].start_index;
dvma_addr = bufinfo[anchor_index].dvma_addr;
page_size_mask = ring_info->block_size_mask;
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)"
"buf_pp $%p btype %d bufsize %d "
"anchor_index %d chunk_index %d dvma $%p",
pkt_buf_addr_pp,
pktbufsz_type,
bufsize,
anchor_index,
chunk_index,
dvma_addr));
offset = pktbuf_pp - dvma_addr; /* offset within the chunk */
block_size = rbr_p->block_size; /* System block(page) size */
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)"
"buf_pp $%p btype %d bufsize %d "
"anchor_index %d chunk_index %d dvma $%p "
"offset %d block_size %d",
pkt_buf_addr_pp,
pktbufsz_type,
bufsize,
anchor_index,
chunk_index,
dvma_addr,
offset,
block_size));
NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index"));
block_index = (offset / block_size); /* index within chunk */
total_index = chunk_index + block_index;
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: "
"total_index %d dvma_addr $%p "
"offset %d block_size %d "
"block_index %d ",
total_index, dvma_addr,
offset, block_size,
block_index));
#if defined(__i386)
*pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr +
(uint32_t)offset);
#else
*pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr +
(uint64_t)offset);
#endif
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: "
"total_index %d dvma_addr $%p "
"offset %d block_size %d "
"block_index %d "
"*pkt_buf_addr_p $%p",
total_index, dvma_addr,
offset, block_size,
block_index,
*pkt_buf_addr_p));
*msg_index = total_index;
*bufoffset = (offset & page_size_mask);
NXGE_DEBUG_MSG((nxgep, RX2_CTL,
"==> nxge_rxbuf_pp_to_vp: get msg index: "
"msg_index %d bufoffset_index %d",
*msg_index,
*bufoffset));
NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp"));
return (NXGE_OK);
}
/*
* used by quick sort (qsort) function
* to perform comparison
*/
static int
nxge_sort_compare(const void *p1, const void *p2)
{
rxbuf_index_info_t *a, *b;
a = (rxbuf_index_info_t *)p1;
b = (rxbuf_index_info_t *)p2;
if (a->dvma_addr > b->dvma_addr)
return (1);
if (a->dvma_addr < b->dvma_addr)