-
Notifications
You must be signed in to change notification settings - Fork 64
/
pci-bus.yaml
232 lines (196 loc) · 6.9 KB
/
pci-bus.yaml
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
# SPDX-License-Identifier: (GPL2.0-only OR BSD-2-Clause)
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/pci-bus.yaml#
$schema: http://devicetree.org/meta-schemas/base.yaml#
title: PCI Bus Nodes
description: |
Common properties for PCI host bridge nodes and PCI bus structure.
PCI bus bridges have standardized Device Tree bindings:
PCI Bus Binding to: IEEE Std 1275-1994
http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
And for the interrupt mapping part:
Open Firmware Recommended Practice: Interrupt Mapping
http://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
maintainers:
- Rob Herring <robh@kernel.org>
properties:
$nodename:
pattern: "^pcie?@"
ranges:
oneOf:
- $ref: /schemas/types.yaml#/definitions/flag
- minItems: 1
maxItems: 32 # Should be enough
items:
minItems: 5
maxItems: 7
additionalItems: true
items:
- enum:
- 0x01000000
- 0x02000000
- 0x03000000
- 0x42000000
- 0x43000000
- 0x81000000
- 0x82000000
- 0x83000000
- 0xc2000000
- 0xc3000000
reg:
description: |
On PCI-PCI bridge nodes, as defined in the IEEE Std 1275-1994
document, it is a five-cell address encoded as (phys.hi phys.mid
phys.lo size.hi size.lo). phys.hi should contain the device's BDF as
0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.
The bus number is defined by firmware, through the standard bridge
configuration mechanism. If this port is a switch port, then firmware
allocates the bus number and writes it into the Secondary Bus Number
register of the bridge directly above this port. Otherwise, the bus
number of a root port is the first number in the bus-range property,
defaulting to zero.
If firmware leaves the ARI Forwarding Enable bit set in the bridge
above this port, then phys.hi contains the 8-bit function number as
0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification
recommends that firmware only leaves ARI enabled when it knows that the
OS is ARI-aware.
dma-ranges:
oneOf:
- type: boolean
- minItems: 1
maxItems: 32 # Should be enough
items:
minItems: 5
maxItems: 7
additionalItems: true
items:
- enum:
- 0x02000000
- 0x03000000
- 0x42000000
- 0x43000000
"#address-cells":
const: 3
"#size-cells":
const: 2
device_type:
const: pci
bus-range:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 2
items:
maximum: 255
external-facing:
description:
When present, the port is externally facing. All bridges and endpoints
downstream of this port are external to the machine. The OS can, for
example, use this information to identify devices that cannot be
trusted with relaxed DMA protection, as users could easily attach
malicious devices to this port.
type: boolean
"#interrupt-cells":
const: 1
interrupt-map: true
# minItems: 1
# maxItems: 88 # 22 IDSEL x 4 IRQs
# items:
# minItems: 6 # 3 addr cells, 1 PCI IRQ cell, 1 phandle, 1+ parent addr and IRQ cells
# maxItems: 16
interrupt-map-mask:
items:
- description: PCI high address cell
minimum: 0
maximum: 0xf800
- description: PCI mid address cell
const: 0
- description: PCI low address cell
const: 0
- description: PCI IRQ cell
minimum: 0
maximum: 7
linux,pci-domain:
description:
If present this property assigns a fixed PCI domain number to a host bridge,
otherwise an unstable (across boots) unique number will be assigned.
It is required to either not set this property at all or set it for all
host bridges in the system, otherwise potentially conflicting domain numbers
may be assigned to root buses behind different host bridges. The domain
number for each host bridge in the system must be unique.
$ref: /schemas/types.yaml#/definitions/uint32
max-link-speed:
description:
If present this property specifies PCI generation number for link
capability. Host drivers could add this as a strategy to avoid
unnecessary operation for unsupported link speed, for instance, trying to
do training for unsupported link speed, etc.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 1, 2, 3, 4 ]
msi-map:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
minItems: 3
items:
- description: The RID base matched by the entry
- description: phandle to msi-controller node
- description: (optional) The msi-specifier produced for the first RID matched
by the entry. Currently, msi-specifier is 0 or 1 cells.
- description: The length of consecutive RIDs following the RID base
msi-map-mask:
description: A mask to be applied to each Requester ID prior to being
mapped to an msi-specifier per the msi-map property.
$ref: /schemas/types.yaml#/definitions/uint32
num-lanes:
description: The number of PCIe lanes
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 1, 2, 4, 8, 16, 32 ]
reset-gpios:
description: GPIO controlled connection to PERST# signal
maxItems: 1
slot-power-limit-milliwatt:
description:
If present, specifies slot power limit in milliwatts.
This property is invalid in host bridge nodes.
maxItems: 1
supports-clkreq:
description:
If present this property specifies that CLKREQ signal routing exists from
root port to downstream device and host bridge drivers can do programming
which depends on CLKREQ signal existence. For example, programming root port
not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
type: boolean
aspm-no-l0s:
description: Disables ASPM L0s capability
type: boolean
vendor-id:
description: The PCI vendor ID
$ref: /schemas/types.yaml#/definitions/uint32
device-id:
description: The PCI device ID
$ref: /schemas/types.yaml#/definitions/uint32
patternProperties:
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@1?[0-9a-f](,[0-7])?$":
type: object
properties:
compatible:
contains:
pattern: "^(pci[0-9a-f]{3,4},[0-9a-f]{1,4}|pciclass,[0-9a-f]{4,6})$"
reg:
items:
minItems: 5
maxItems: 5
minItems: 1
maxItems: 6 # Up to 6 BARs
required:
- reg
required:
- device_type
- ranges
- reg
- "#address-cells"
- "#size-cells"
dependentRequired:
msi-map-mask: [ msi-map ]
additionalProperties: true