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rk_hdmirx.c
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rk_hdmirx.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
*
* Author: Dingxian Wen <shawn.wen@rock-chips.com>
*/
#include <dt-bindings/soc/rockchip-system-status.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/fs.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/math64.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_reserved_mem.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/rk_hdmirx_config.h>
#include <linux/rockchip/rockchip_sip.h>
#include <linux/seq_file.h>
#include <linux/v4l2-dv-timings.h>
#include <linux/workqueue.h>
#include <media/cec.h>
#include <media/cec-notifier.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-dv-timings.h>
#include <media/v4l2-event.h>
#include <media/v4l2-fh.h>
#include <media/v4l2-ioctl.h>
#include <media/videobuf2-dma-contig.h>
#include <media/videobuf2-v4l2.h>
#include <soc/rockchip/rockchip-system-status.h>
#include <sound/hdmi-codec.h>
#include "rk_hdmirx.h"
#include "rk_hdmirx_cec.h"
#include "rk_hdmirx_hdcp.h"
static struct class *hdmirx_class;
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "debug level (0-3)");
#define RK_HDMIRX_DRVNAME "rk_hdmirx"
#define EDID_NUM_BLOCKS_MAX 2
#define EDID_BLOCK_SIZE 128
#define HDMIRX_DEFAULT_TIMING V4L2_DV_BT_CEA_640X480P59_94
#define HDMIRX_VDEV_NAME "stream_hdmirx"
#define HDMIRX_REQ_BUFS_MIN 2
#define HDMIRX_STORED_BIT_WIDTH 8
#define IREF_CLK_FREQ_HZ 428571429
#define MEMORY_ALIGN_ROUND_UP_BYTES 64
#define HDMIRX_PLANE_Y 0
#define HDMIRX_PLANE_CBCR 1
#define INIT_FIFO_STATE 64
#define RK_IRQ_HDMIRX_HDMI 210
#define FILTER_FRAME_CNT 6
#define CPU_LIMIT_FREQ_KHZ 1200000
#define WAIT_PHY_REG_TIME 50
#define WAIT_TIMER_LOCK_TIME 50
#define WAIT_SIGNAL_LOCK_TIME 600 /* if 5V present: 7ms each time */
#define WAIT_AVI_PKT_TIME 300
#define is_validfs(x) (x == 32000 || \
x == 44100 || \
x == 48000 || \
x == 88200 || \
x == 96000 || \
x == 176400 || \
x == 192000 || \
x == 768000)
struct hdmirx_audiostate {
struct platform_device *pdev;
u32 hdmirx_aud_clkrate;
u32 fs_audio;
u32 ch_audio;
u32 ctsn_flag;
u32 fifo_flag;
int init_state;
int pre_state;
bool fifo_int;
bool audio_enabled;
};
enum hdmirx_pix_fmt {
HDMIRX_RGB888 = 0,
HDMIRX_YUV422 = 1,
HDMIRX_YUV444 = 2,
HDMIRX_YUV420 = 3,
};
static const char * const pix_fmt_str[] = {
"RGB888",
"YUV422",
"YUV444",
"YUV420",
};
enum ddr_store_fmt {
STORE_RGB888 = 0,
STORE_RGBA_ARGB,
STORE_YUV420_8BIT,
STORE_YUV420_10BIT,
STORE_YUV422_8BIT,
STORE_YUV422_10BIT,
STORE_YUV444_8BIT,
STORE_YUV420_16BIT = 8,
STORE_YUV422_16BIT = 9,
};
enum hdmirx_reg_attr {
HDMIRX_ATTR_RW = 0,
HDMIRX_ATTR_RO = 1,
HDMIRX_ATTR_WO = 2,
HDMIRX_ATTR_RE = 3,
};
enum hdmirx_edid_version {
HDMIRX_EDID_USER = 0,
HDMIRX_EDID_340M = 1,
HDMIRX_EDID_600M = 2,
};
struct hdmirx_reg_table {
int reg_base;
int reg_end;
enum hdmirx_reg_attr attr;
};
struct hdmirx_buffer {
struct vb2_v4l2_buffer vb;
struct list_head queue;
union {
u32 buff_addr[VIDEO_MAX_PLANES];
void *vaddr[VIDEO_MAX_PLANES];
};
};
struct hdmirx_output_fmt {
u32 fourcc;
u8 cplanes;
u8 mplanes;
u8 bpp[VIDEO_MAX_PLANES];
};
struct hdmirx_stream {
struct rk_hdmirx_dev *hdmirx_dev;
struct video_device vdev;
struct vb2_queue buf_queue;
struct list_head buf_head;
struct hdmirx_buffer *curr_buf;
struct hdmirx_buffer *next_buf;
struct v4l2_pix_format_mplane pixm;
const struct hdmirx_output_fmt *out_fmt;
struct mutex vlock;
spinlock_t vbq_lock;
bool stopping;
wait_queue_head_t wq_stopped;
u32 frame_idx;
u32 line_flag_int_cnt;
u32 irq_stat;
};
struct rk_hdmirx_dev {
struct cec_notifier *cec_notifier;
struct cpufreq_policy *policy;
struct device *dev;
struct device *classdev;
struct device *codec_dev;
struct device_node *of_node;
struct hdmirx_stream stream;
struct v4l2_device v4l2_dev;
struct v4l2_ctrl_handler hdl;
struct v4l2_ctrl *detect_tx_5v_ctrl;
struct v4l2_dv_timings timings;
struct gpio_desc *hdmirx_det_gpio;
struct work_struct work_wdt_config;
struct delayed_work delayed_work_hotplug;
struct delayed_work delayed_work_res_change;
struct delayed_work delayed_work_audio;
struct delayed_work delayed_work_heartbeat;
struct dentry *debugfs_dir;
struct freq_qos_request min_sta_freq_req;
struct hdmirx_audiostate audio_state;
struct hdmirx_cec *cec;
struct mutex stream_lock;
struct mutex work_lock;
struct pm_qos_request pm_qos;
struct reset_control *rst_a;
struct reset_control *rst_p;
struct reset_control *rst_ref;
struct reset_control *rst_biu;
struct clk_bulk_data *clks;
struct regmap *grf;
struct regmap *vo1_grf;
struct rk_hdmirx_hdcp *hdcp;
void __iomem *regs;
int edid_version;
int audio_present;
int hdmi_irq;
int dma_irq;
int det_irq;
enum hdmirx_pix_fmt pix_fmt;
bool avi_pkt_rcv;
bool cr_write_done;
bool cr_read_done;
bool timer_base_lock;
bool tmds_clk_ratio;
bool is_dvi_mode;
bool power_on;
bool initialized;
bool freq_qos_add;
bool get_timing;
bool cec_enable;
bool hpd_on;
bool force_off;
u8 hdcp_enable;
u32 num_clks;
u32 edid_blocks_written;
u32 hpd_trigger_level;
u32 cur_vic;
u32 cur_fmt_fourcc;
u32 cur_color_range;
u32 cur_color_space;
u32 color_depth;
u32 cpu_freq_khz;
u32 bound_cpu;
u32 fps;
u32 wdt_cfg_bound_cpu;
u8 edid[EDID_BLOCK_SIZE * 2];
hdmi_codec_plugged_cb plugged_cb;
spinlock_t rst_lock;
};
static bool tx_5v_power_present(struct rk_hdmirx_dev *hdmirx_dev);
static void hdmirx_set_fmt(struct hdmirx_stream *stream,
struct v4l2_pix_format_mplane *pixm, bool try);
static void hdmirx_audio_set_state(struct rk_hdmirx_dev *hdmirx_dev, enum audio_stat stat);
static void hdmirx_audio_setup(struct rk_hdmirx_dev *hdmirx_dev);
static u32 hdmirx_audio_fs(struct rk_hdmirx_dev *hdmirx_dev);
static u32 hdmirx_audio_ch(struct rk_hdmirx_dev *hdmirx_dev);
static void hdmirx_audio_fifo_init(struct rk_hdmirx_dev *hdmirx_dev);
static void hdmirx_audio_handle_plugged_change(struct rk_hdmirx_dev *hdmirx_dev, bool plugged);
static void hdmirx_audio_interrupts_setup(struct rk_hdmirx_dev *hdmirx_dev, bool en);
static int hdmirx_set_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev);
static void hdmirx_cancel_cpu_limit_freq(struct rk_hdmirx_dev *hdmirx_dev);
static void hdmirx_plugout(struct rk_hdmirx_dev *hdmirx_dev);
static u8 edid_init_data_340M[] = {
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00,
0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78,
0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23,
0x09, 0x48, 0x4C, 0x21, 0x08, 0x00, 0x61, 0x40,
0x01, 0x01, 0x81, 0x00, 0x95, 0x00, 0xA9, 0xC0,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E,
0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
0x6E, 0x28, 0x55, 0x00, 0x20, 0xC2, 0x31, 0x00,
0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52,
0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0xA7,
0x02, 0x03, 0x2E, 0xF1, 0x51, 0x07, 0x16, 0x14,
0x05, 0x01, 0x03, 0x12, 0x13, 0x84, 0x22, 0x1F,
0x90, 0x5D, 0x5E, 0x5F, 0x60, 0x61, 0x23, 0x09,
0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03,
0x0C, 0x00, 0x30, 0x00, 0x00, 0x44, 0xE3, 0x05,
0x03, 0x01, 0xE3, 0x0E, 0x60, 0x61, 0x02, 0x3A,
0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
0x45, 0x00, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD2,
};
static u8 edid_init_data_600M[] = {
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
0x49, 0x70, 0x88, 0x35, 0x01, 0x00, 0x00, 0x00,
0x2D, 0x1F, 0x01, 0x03, 0x80, 0x78, 0x44, 0x78,
0x0A, 0xCF, 0x74, 0xA3, 0x57, 0x4C, 0xB0, 0x23,
0x09, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x08, 0xE8,
0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80, 0xB0, 0x58,
0x8A, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
0x08, 0xE8, 0x00, 0x30, 0xF2, 0x70, 0x5A, 0x80,
0xB0, 0x58, 0x8A, 0x00, 0x20, 0xC2, 0x31, 0x00,
0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x52,
0x4B, 0x2D, 0x55, 0x48, 0x44, 0x0A, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
0x00, 0x3B, 0x46, 0x1F, 0x8C, 0x3C, 0x00, 0x0A,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x39,
0x02, 0x03, 0x22, 0xF2, 0x41, 0x61, 0x23, 0x09,
0x07, 0x07, 0x83, 0x01, 0x00, 0x00, 0x67, 0x03,
0x0C, 0x00, 0x30, 0x00, 0x00, 0x78, 0x67, 0xD8,
0x5D, 0xC4, 0x01, 0x78, 0xC0, 0x00, 0xE3, 0x05,
0x03, 0x01, 0x08, 0xE8, 0x00, 0x30, 0xF2, 0x70,
0x5A, 0x80, 0xB0, 0x58, 0x8A, 0x00, 0xC4, 0x8E,
0x21, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x65,
};
static char *hdmirx_color_space[8] = {
"xvYCC601", "xvYCC709", "sYCC601", "Adobe_YCC601",
"Adobe_RGB", "BT2020_YcCbcCrc", "BT2020_RGB"
};
static const struct v4l2_dv_timings_cap hdmirx_timings_cap = {
.type = V4L2_DV_BT_656_1120,
.reserved = { 0 },
V4L2_INIT_BT_TIMINGS(640, 4096, /* min/max width */
480, 2160, /* min/max height */
20000000, 600000000, /* min/max pixelclock */
/* standards */
V4L2_DV_BT_STD_CEA861,
/* capabilities */
V4L2_DV_BT_CAP_PROGRESSIVE |
V4L2_DV_BT_CAP_INTERLACED)
};
static const struct hdmirx_output_fmt g_out_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_BGR24,
.cplanes = 1,
.mplanes = 1,
.bpp = { 24 },
}, {
.fourcc = V4L2_PIX_FMT_NV24,
.cplanes = 2,
.mplanes = 1,
.bpp = { 8, 16 },
}, {
.fourcc = V4L2_PIX_FMT_NV16,
.cplanes = 2,
.mplanes = 1,
.bpp = { 8, 16 },
}, {
.fourcc = V4L2_PIX_FMT_NV12,
.cplanes = 2,
.mplanes = 1,
.bpp = { 8, 16 },
}
};
static inline struct hdmirx_buffer *to_hdmirx_buffer(struct vb2_v4l2_buffer *vb)
{
return container_of(vb, struct hdmirx_buffer, vb);
}
static void hdmirx_writel(struct rk_hdmirx_dev *hdmirx_dev, int reg, u32 val)
{
unsigned long lock_flags = 0;
spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
writel(val, hdmirx_dev->regs + reg);
spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
}
static u32 hdmirx_readl(struct rk_hdmirx_dev *hdmirx_dev, int reg)
{
unsigned long lock_flags = 0;
u32 val;
spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
val = readl(hdmirx_dev->regs + reg);
spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
return val;
}
static void hdmirx_reset_dma(struct rk_hdmirx_dev *hdmirx_dev)
{
unsigned long lock_flags = 0;
spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
reset_control_assert(hdmirx_dev->rst_a);
reset_control_deassert(hdmirx_dev->rst_a);
spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
}
static void hdmirx_reset_all(struct rk_hdmirx_dev *hdmirx_dev)
{
unsigned long lock_flags = 0;
spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
reset_control_assert(hdmirx_dev->rst_a);
reset_control_assert(hdmirx_dev->rst_p);
reset_control_assert(hdmirx_dev->rst_ref);
reset_control_assert(hdmirx_dev->rst_biu);
reset_control_deassert(hdmirx_dev->rst_a);
reset_control_deassert(hdmirx_dev->rst_p);
reset_control_deassert(hdmirx_dev->rst_ref);
reset_control_deassert(hdmirx_dev->rst_biu);
spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
}
static void hdmirx_update_bits(struct rk_hdmirx_dev *hdmirx_dev, int reg, u32 mask,
u32 data)
{
unsigned long lock_flags = 0;
u32 val;
spin_lock_irqsave(&hdmirx_dev->rst_lock, lock_flags);
val = readl(hdmirx_dev->regs + reg) & ~mask;
val |= (data & mask);
writel(val, hdmirx_dev->regs + reg);
spin_unlock_irqrestore(&hdmirx_dev->rst_lock, lock_flags);
}
static int hdmirx_subscribe_event(struct v4l2_fh *fh,
const struct v4l2_event_subscription *sub)
{
switch (sub->type) {
case V4L2_EVENT_SOURCE_CHANGE:
if (fh->vdev->vfl_dir == VFL_DIR_RX)
return v4l2_src_change_event_subscribe(fh, sub);
break;
case V4L2_EVENT_CTRL:
return v4l2_ctrl_subscribe_event(fh, sub);
case RK_HDMIRX_V4L2_EVENT_SIGNAL_LOST:
return v4l2_event_subscribe(fh, sub, 0, NULL);
default:
return v4l2_ctrl_subscribe_event(fh, sub);
}
return -EINVAL;
}
static bool port_no_link(struct rk_hdmirx_dev *hdmirx_dev)
{
return !tx_5v_power_present(hdmirx_dev);
}
static bool signal_not_lock(struct rk_hdmirx_dev *hdmirx_dev)
{
u32 mu_status, dma_st10, cmu_st;
mu_status = hdmirx_readl(hdmirx_dev, MAINUNIT_STATUS);
dma_st10 = hdmirx_readl(hdmirx_dev, DMA_STATUS10);
cmu_st = hdmirx_readl(hdmirx_dev, CMU_STATUS);
if ((mu_status & TMDSVALID_STABLE_ST) &&
(dma_st10 & HDMIRX_LOCK) &&
(cmu_st & TMDSQPCLK_LOCKED_ST))
return false;
return true;
}
static bool tx_5v_power_present(struct rk_hdmirx_dev *hdmirx_dev)
{
bool ret;
int val, i, cnt;
cnt = 0;
for (i = 0; i < 10; i++) {
usleep_range(1000, 1100);
val = gpiod_get_value(hdmirx_dev->hdmirx_det_gpio);
if (val > 0)
cnt++;
if (cnt >= 7)
break;
}
ret = (cnt >= 7) ? true : false;
v4l2_dbg(3, debug, &hdmirx_dev->v4l2_dev, "%s: %d\n", __func__, ret);
return ret;
}
static int hdmirx_g_dv_timings(struct file *file, void *_fh,
struct v4l2_dv_timings *timings)
{
struct hdmirx_stream *stream = video_drvdata(file);
struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
u32 dma_cfg1;
*timings = hdmirx_dev->timings;
dma_cfg1 = hdmirx_readl(hdmirx_dev, DMA_CONFIG1);
v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s, DMA_CONFIG1:%#x\n",
__func__, pix_fmt_str[hdmirx_dev->pix_fmt], dma_cfg1);
return 0;
}
static int hdmirx_s_dv_timings(struct file *file, void *_fh,
struct v4l2_dv_timings *timings)
{
struct hdmirx_stream *stream = video_drvdata(file);
struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
if (!timings)
return -EINVAL;
if (debug)
v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name,
"hdmirx_s_dv_timings: ", timings, false);
if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) {
v4l2_dbg(1, debug, v4l2_dev,
"%s: timings out of range\n", __func__);
return -ERANGE;
}
/* Check if the timings are part of the CEA-861 timings. */
if (!v4l2_find_dv_timings_cap(timings, &hdmirx_timings_cap,
0, NULL, NULL))
return -EINVAL;
if (v4l2_match_dv_timings(&hdmirx_dev->timings, timings, 0, false)) {
v4l2_dbg(1, debug, v4l2_dev, "%s: no change\n", __func__);
return 0;
}
/*
* Changing the timings implies a format change, which is not allowed
* while buffers for use with streaming have already been allocated.
*/
if (vb2_is_busy(&stream->buf_queue))
return -EBUSY;
hdmirx_dev->timings = *timings;
/* Update the internal format */
hdmirx_set_fmt(stream, &stream->pixm, false);
return 0;
}
static void hdmirx_get_colordepth(struct rk_hdmirx_dev *hdmirx_dev)
{
u32 val, color_depth_reg;
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
color_depth_reg = (val & HDMIRX_COLOR_DEPTH_MASK) >> 3;
switch (color_depth_reg) {
case 0x4:
hdmirx_dev->color_depth = 24;
break;
case 0x5:
hdmirx_dev->color_depth = 30;
break;
case 0x6:
hdmirx_dev->color_depth = 36;
break;
case 0x7:
hdmirx_dev->color_depth = 48;
break;
default:
hdmirx_dev->color_depth = 24;
break;
}
v4l2_dbg(1, debug, v4l2_dev, "%s: color_depth: %d, reg_val:%d\n",
__func__, hdmirx_dev->color_depth, color_depth_reg);
}
static void hdmirx_get_pix_fmt(struct rk_hdmirx_dev *hdmirx_dev)
{
u32 val;
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
hdmirx_dev->pix_fmt = val & HDMIRX_FORMAT_MASK;
switch (hdmirx_dev->pix_fmt) {
case HDMIRX_RGB888:
hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
break;
case HDMIRX_YUV422:
hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV16;
break;
case HDMIRX_YUV444:
hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV24;
break;
case HDMIRX_YUV420:
hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_NV12;
break;
default:
v4l2_err(v4l2_dev,
"%s: err pix_fmt: %d, set RGB888 as default\n",
__func__, hdmirx_dev->pix_fmt);
hdmirx_dev->pix_fmt = HDMIRX_RGB888;
hdmirx_dev->cur_fmt_fourcc = V4L2_PIX_FMT_BGR24;
break;
}
/*
* set avmute value to black
* RGB: R:bit[47:40], G:bit[31:24], B:bit[15:8]
* YUV444: Y:bit[47:40], U:bit[31:24], V:bit[15:8]
* YUV422: Y:bit[47:40], UV:bit[15:8]
* YUV420: Y:bit[47:40], Y:bit[31:24], UV:bit[15:8]
*/
if (hdmirx_dev->pix_fmt == HDMIRX_RGB888) {
hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_H, 0x0);
hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_L, 0x0);
} else if (hdmirx_dev->pix_fmt == HDMIRX_YUV444) {
hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_H, 0x0);
hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_L, 0x80008000);
} else {
hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_H, 0x0);
hdmirx_writel(hdmirx_dev, VIDEO_MUTE_VALUE_L, 0x00008000);
}
v4l2_dbg(1, debug, v4l2_dev, "%s: pix_fmt: %s\n", __func__,
pix_fmt_str[hdmirx_dev->pix_fmt]);
}
static void hdmirx_get_color_space(struct rk_hdmirx_dev *hdmirx_dev)
{
u32 val;
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
/*
* Note: PKTDEC_ACR_PB3_0 contents only updated after
* reading pktdec_aviif_ph2_1 unless snapshot feature
* is disabled using pktdec_snapshot_bypass
*/
hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1);
val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB3_0);
hdmirx_dev->cur_color_space = (val & EXTEND_COLORIMETRY) >> 28;
v4l2_dbg(2, debug, v4l2_dev, "%s: video standard: %s\n", __func__,
hdmirx_color_space[hdmirx_dev->cur_color_space]);
}
static void hdmirx_get_color_range(struct rk_hdmirx_dev *hdmirx_dev)
{
u32 val;
int color_range;
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
/*
* Note: PKTDEC_ACR_PB3_0 contents only updated after
* reading pktdec_aviif_ph2_1 unless snapshot feature
* is disabled using pktdec_snapshot_bypass
*/
hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1);
val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB3_0);
color_range = (val & RGB_QUANTIZATION_RANGE) >> 26;
if (hdmirx_dev->pix_fmt != HDMIRX_RGB888) {
hdmirx_dev->cur_color_range = color_range;
} else {
if (color_range != HDMIRX_DEFAULT_RANGE) {
hdmirx_dev->cur_color_range = color_range;
} else {
(hdmirx_dev->cur_vic) ?
(hdmirx_dev->cur_color_range = HDMIRX_LIMIT_RANGE) :
(hdmirx_dev->cur_color_range = HDMIRX_FULL_RANGE);
}
}
v4l2_dbg(2, debug, v4l2_dev, "%s: color_range: %s\n", __func__,
(hdmirx_dev->cur_color_range == HDMIRX_DEFAULT_RANGE) ? "default" :
(hdmirx_dev->cur_color_range == HDMIRX_FULL_RANGE ? "full" : "limit"));
}
static void hdmirx_get_timings(struct rk_hdmirx_dev *hdmirx_dev,
struct v4l2_bt_timings *bt, bool from_dma)
{
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
u32 hact, vact, htotal, vtotal, fps;
u32 hfp, hs, hbp, vfp, vs, vbp;
u32 val;
if (from_dma) {
hfp = 0;
val = hdmirx_readl(hdmirx_dev, DMA_STATUS2);
hact = (val >> 16) & 0xffff;
vact = val & 0xffff;
val = hdmirx_readl(hdmirx_dev, DMA_STATUS3);
htotal = (val >> 16) & 0xffff;
vtotal = val & 0xffff;
val = hdmirx_readl(hdmirx_dev, DMA_STATUS4);
hs = (val >> 16) & 0xffff;
vs = val & 0xffff;
val = hdmirx_readl(hdmirx_dev, DMA_STATUS5);
hbp = (val >> 16) & 0xffff;
vbp = val & 0xffff;
} else {
val = hdmirx_readl(hdmirx_dev, VMON_STATUS1);
hs = (val >> 16) & 0xffff;
hfp = val & 0xffff;
val = hdmirx_readl(hdmirx_dev, VMON_STATUS2);
hbp = val & 0xffff;
val = hdmirx_readl(hdmirx_dev, VMON_STATUS3);
htotal = (val >> 16) & 0xffff;
hact = val & 0xffff;
val = hdmirx_readl(hdmirx_dev, VMON_STATUS4);
vs = (val >> 16) & 0xffff;
vfp = val & 0xffff;
val = hdmirx_readl(hdmirx_dev, VMON_STATUS5);
vbp = val & 0xffff;
val = hdmirx_readl(hdmirx_dev, VMON_STATUS6);
vtotal = (val >> 16) & 0xffff;
vact = val & 0xffff;
}
if (hdmirx_dev->pix_fmt == HDMIRX_YUV420) {
htotal *= 2;
hfp *= 2;
hbp *= 2;
hs *= 2;
if (!from_dma)
hact *= 2;
}
if (from_dma) {
hfp = htotal - hact - hs - hbp;
vfp = vtotal - vact - vs - vbp;
}
fps = (bt->pixelclock + (htotal * vtotal) / 2) / (htotal * vtotal);
if (hdmirx_dev->pix_fmt == HDMIRX_YUV420)
fps *= 2;
bt->width = hact;
bt->height = vact;
bt->hfrontporch = hfp;
bt->hsync = hs;
bt->hbackporch = hbp;
bt->vfrontporch = vfp;
bt->vsync = vs;
bt->vbackporch = vbp;
hdmirx_dev->fps = fps;
v4l2_dbg(1, debug, v4l2_dev, "get timings from %s\n", from_dma ? "dma" : "ctrl");
v4l2_dbg(1, debug, v4l2_dev,
"act:%ux%u, total:%ux%u, fps:%u, pixclk:%llu\n",
bt->width, bt->height, htotal, vtotal, fps, bt->pixelclock);
v4l2_dbg(2, debug, v4l2_dev,
"hfp:%u, hs:%u, hbp:%u, vfp:%u, vs:%u, vbp:%u\n",
bt->hfrontporch, bt->hsync, bt->hbackporch,
bt->vfrontporch, bt->vsync, bt->vbackporch);
}
static bool hdmirx_check_timing_valid(struct v4l2_bt_timings *bt)
{
if (bt->width < 100 || bt->width > 5000 ||
bt->height < 100 || bt->height > 5000)
return false;
if (bt->hsync == 0 || bt->hsync > 500 ||
bt->vsync == 0 || bt->vsync > 100)
return false;
if (bt->hbackporch == 0 || bt->hbackporch > 3000 ||
bt->vbackporch == 0 || bt->vbackporch > 3000)
return false;
if (bt->hfrontporch == 0 || bt->hfrontporch > 3000 ||
bt->vfrontporch == 0 || bt->vfrontporch > 3000)
return false;
return true;
}
static int hdmirx_get_detected_timings(struct rk_hdmirx_dev *hdmirx_dev,
struct v4l2_dv_timings *timings, bool from_dma)
{
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
struct v4l2_bt_timings *bt = &timings->bt;
u32 field_type, color_depth, deframer_st;
u32 val, tmdsqpclk_freq, pix_clk;
u64 tmp_data, tmds_clk;
memset(timings, 0, sizeof(struct v4l2_dv_timings));
timings->type = V4L2_DV_BT_656_1120;
val = hdmirx_readl(hdmirx_dev, DMA_STATUS11);
field_type = (val & HDMIRX_TYPE_MASK) >> 7;
hdmirx_get_pix_fmt(hdmirx_dev);
hdmirx_get_color_range(hdmirx_dev);
hdmirx_get_color_space(hdmirx_dev);
bt->interlaced = field_type & BIT(0) ?
V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PH2_1);
val = hdmirx_readl(hdmirx_dev, PKTDEC_AVIIF_PB7_4);
hdmirx_dev->cur_vic = val & VIC_VAL_MASK;
hdmirx_get_colordepth(hdmirx_dev);
color_depth = hdmirx_dev->color_depth;
deframer_st = hdmirx_readl(hdmirx_dev, DEFRAMER_STATUS);
hdmirx_dev->is_dvi_mode = deframer_st & OPMODE_STS_MASK ? false : true;
tmdsqpclk_freq = hdmirx_readl(hdmirx_dev, CMU_TMDSQPCLK_FREQ);
tmds_clk = tmdsqpclk_freq * 4 * 1000U;
tmp_data = tmds_clk * 24;
do_div(tmp_data, color_depth);
pix_clk = tmp_data;
bt->pixelclock = tmds_clk;
hdmirx_get_timings(hdmirx_dev, bt, from_dma);
if (bt->interlaced == V4L2_DV_INTERLACED) {
bt->height *= 2;
bt->il_vsync = bt->vsync + 1;
}
v4l2_dbg(2, debug, v4l2_dev, "tmds_clk:%llu, pix_clk:%d\n", tmds_clk, pix_clk);
v4l2_dbg(1, debug, v4l2_dev, "interlace:%d, fmt:%d, vic:%d, color:%d, mode:%s\n",
bt->interlaced, hdmirx_dev->pix_fmt,
hdmirx_dev->cur_vic, hdmirx_dev->color_depth,
hdmirx_dev->is_dvi_mode ? "dvi" : "hdmi");
v4l2_dbg(2, debug, v4l2_dev, "deframer_st:%#x\n", deframer_st);
if (!hdmirx_check_timing_valid(bt))
return -EINVAL;
return 0;
}
static void hdmirx_set_negative_pol(struct rk_hdmirx_dev *hdmirx_dev, bool en)
{
if (en) {
hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6,
VSYNC_TOGGLE_EN|
HSYNC_TOGGLE_EN,
VSYNC_TOGGLE_EN|
HSYNC_TOGGLE_EN);
hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2,
VPROC_VSYNC_POL_OVR_VALUE|
VPROC_VSYNC_POL_OVR_EN|
VPROC_HSYNC_POL_OVR_VALUE|
VPROC_HSYNC_POL_OVR_EN,
VPROC_VSYNC_POL_OVR_EN|
VPROC_HSYNC_POL_OVR_EN);
return;
}
hdmirx_update_bits(hdmirx_dev, DMA_CONFIG6,
VSYNC_TOGGLE_EN|
HSYNC_TOGGLE_EN,
0);
hdmirx_update_bits(hdmirx_dev, VIDEO_CONFIG2,
VPROC_VSYNC_POL_OVR_VALUE|
VPROC_VSYNC_POL_OVR_EN|
VPROC_HSYNC_POL_OVR_VALUE|
VPROC_HSYNC_POL_OVR_EN,
0);
}
static int hdmirx_try_to_get_timings(struct rk_hdmirx_dev *hdmirx_dev,
struct v4l2_dv_timings *timings, int try_cnt)
{
int i, cnt = 0, fail_cnt = 0, ret = 0;
bool from_dma = false;
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
hdmirx_set_negative_pol(hdmirx_dev, false);
for (i = 0; i < try_cnt; i++) {
ret = hdmirx_get_detected_timings(hdmirx_dev, timings, from_dma);
if (ret) {
cnt = 0;
fail_cnt++;
if (fail_cnt > 3) {
hdmirx_set_negative_pol(hdmirx_dev, true);
from_dma = true;
}
} else {
cnt++;
}
if (cnt >= 5)
break;
usleep_range(10*1000, 10*1100);
}
if (try_cnt > 8 && cnt < 5)
v4l2_dbg(1, debug, v4l2_dev, "%s: res not stable!\n", __func__);
return ret;
}
static int hdmirx_query_dv_timings(struct file *file, void *_fh,
struct v4l2_dv_timings *timings)
{
int ret;
struct hdmirx_stream *stream = video_drvdata(file);
struct rk_hdmirx_dev *hdmirx_dev = stream->hdmirx_dev;
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
if (port_no_link(hdmirx_dev)) {
v4l2_err(v4l2_dev, "%s port has no link!\n", __func__);
return -ENOLINK;
}
if (signal_not_lock(hdmirx_dev)) {
v4l2_err(v4l2_dev, "%s signal is not locked!\n", __func__);
return -ENOLCK;
}
/*
* query dv timings is during preview, dma's timing is stable,
* so we can get from DMA. If the current resolution is negative,
* get timing from CTRL need to change polarity of sync,
* maybe cause DMA errors.
*/
ret = hdmirx_get_detected_timings(hdmirx_dev, timings, true);
if (ret)
return ret;
if (debug)
v4l2_print_dv_timings(hdmirx_dev->v4l2_dev.name,
"query_dv_timings: ", timings, false);
if (!v4l2_valid_dv_timings(timings, &hdmirx_timings_cap, NULL, NULL)) {
v4l2_dbg(1, debug, v4l2_dev, "%s: timings out of range\n", __func__);
return -ERANGE;
}
return 0;
}
static void hdmirx_cec_state_reconfiguration(struct rk_hdmirx_dev *hdmirx_dev, bool en)
{
unsigned int irqs;
if (en) {
hdmirx_update_bits(hdmirx_dev, GLOBAL_SWENABLE, CEC_ENABLE, CEC_ENABLE);
hdmirx_update_bits(hdmirx_dev, CEC_CONFIG, RX_AUTO_DRIVE_ACKNOWLEDGE,
RX_AUTO_DRIVE_ACKNOWLEDGE);
irqs = CECTX_LINE_ERR | CECTX_NACK | CECRX_EOM | CECTX_DONE;
hdmirx_writel(hdmirx_dev, CEC_INT_MASK_N, irqs);
}
cec_queue_pin_hpd_event(hdmirx_dev->cec->adap, en, ktime_get());
}
static void hdmirx_hpd_config(struct rk_hdmirx_dev *hdmirx_dev, bool en)
{
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
u32 level;
v4l2_dbg(1, debug, v4l2_dev, "%s: %sable, hpd_trigger_level:%d\n",
__func__, en ? "en" : "dis",
hdmirx_dev->hpd_trigger_level);
hdmirx_update_bits(hdmirx_dev, SCDC_CONFIG, HPDLOW, en ? 0 : HPDLOW);
level = hdmirx_dev->hpd_trigger_level ? en : !en;
hdmirx_writel(hdmirx_dev, CORE_CONFIG, level);
if (hdmirx_dev->cec && hdmirx_dev->cec->adap)
hdmirx_cec_state_reconfiguration(hdmirx_dev, en);
}
static void hdmirx_hpd_ctrl(struct rk_hdmirx_dev *hdmirx_dev, bool en)
{
struct v4l2_device *v4l2_dev = &hdmirx_dev->v4l2_dev;
if (hdmirx_dev->force_off && en)
return;
v4l2_dbg(1, debug, v4l2_dev, "%s: %sable, hpd_trigger_level:%d\n",
__func__, en ? "en" : "dis",
hdmirx_dev->hpd_trigger_level);
hdmirx_hpd_config(hdmirx_dev, en);
if (hdmirx_dev->hdcp && hdmirx_dev->hdcp->hdcp2_connect_ctrl) {
regmap_write(hdmirx_dev->vo1_grf, VO1_GRF_VO1_CON1,
HDCP1_P0_GPIO_IN_SEL | HDCP1_P0_GPIO_IN_SEL << 16);
hdmirx_dev->hdcp->hdcp2_connect_ctrl(hdmirx_dev->hdcp, en);
}
hdmirx_dev->hpd_on = en;
}
static int hdmirx_write_edid(struct rk_hdmirx_dev *hdmirx_dev,
struct v4l2_edid *edid, bool hpd_up)