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rv1106.dtsi
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rv1106.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/clock/rv1106-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include <dt-bindings/suspend/rockchip-rv1106.h>
#include <dt-bindings/thermal/thermal.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rockchip,rv1106";
interrupt-parent = <&gic>;
aliases {
csi2dphy0 = &csi2_dphy0;
csi2dphy1 = &csi2_dphy1;
csi2dphy2 = &csi2_dphy2;
ethernet0 = &gmac;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdio;
pwm0 = &pwm0;
pwm1 = &pwm1;
pwm2 = &pwm2;
pwm3 = &pwm3;
pwm4 = &pwm4;
pwm5 = &pwm5;
pwm6 = &pwm6;
pwm7 = &pwm7;
pwm8 = &pwm8;
pwm9 = &pwm9;
pwm10 = &pwm10;
pwm11 = &pwm11;
rkcif_mipi_lvds0 = &rkcif_mipi_lvds;
rkcif_mipi_lvds1 = &rkcif_mipi_lvds1;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &sfc;
};
clocks {
compatible = "simple-bus";
cpu_pvtpll: cpu-pvtpll {
compatible = "fixed-clock";
clock-frequency = <1300000000>;
clock-output-names = "cpu_pvtpll";
#clock-cells = <0>;
status = "disabled";
};
rkvenc_pvtpll: pvtpll-0 {
compatible = "fixed-clock";
clock-frequency = <410000000>;
clock-output-names = "clk_pvtpll_0";
#clock-cells = <0>;
};
npu_pvtpll: pvtpll-1 {
compatible = "fixed-clock";
clock-frequency = <420000000>;
clock-output-names = "clk_pvtpll_1";
#clock-cells = <0>;
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
cpu0_opp_table: cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpu_leakage>;
nvmem-cell-names = "leakage";
rockchip,pvtpll-avg-offset = <0x4001c>;
rockchip,pvtpll-min-rate = <1104000>;
rockchip,pvtpll-volt-step = <12500>;
rockchip,grf = <&grf>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <850000 850000 1000000>;
clock-latency-ns = <40000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <850000 850000 1000000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <850000 850000 1000000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <850000 850000 1000000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <850000 850000 1000000>;
clock-latency-ns = <40000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <875000 850000 1000000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <925000 850000 1000000>;
clock-latency-ns = <40000>;
};
opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <975000 850000 1000000>;
clock-latency-ns = <40000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1000000 850000 1000000>;
clock-latency-ns = <40000>;
};
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>;
};
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
nvmem-cell-names = "id", "cpu-version", "cpu-code";
};
/* dphy0 full mode */
csi2_dphy0: csi2-dphy0 {
compatible = "rockchip,rv1106-csi2-dphy";
rockchip,hw = <&csi2_dphy_hw>;
status = "disabled";
};
/* dphy1 split mode 01 */
csi2_dphy1: csi2-dphy1 {
compatible = "rockchip,rv1106-csi2-dphy";
rockchip,hw = <&csi2_dphy_hw>;
status = "disabled";
};
/* dphy2 split mode 23 */
csi2_dphy2: csi2-dphy2 {
compatible = "rockchip,rv1106-csi2-dphy";
rockchip,hw = <&csi2_dphy_hw>;
status = "disabled";
};
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
status = "disabled";
route {
route_rgb: route-rgb {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_rgb>;
};
};
};
fiq_debugger: fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;
rockchip,wake-irq = <0>;
rockchip,irq-mode-enable = <0>;
rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
firmware {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
status = "disabled";
};
};
mipi0_csi2: mipi0-csi2 {
compatible = "rockchip,rv1106-mipi-csi2";
rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>;
status = "disabled";
};
mipi1_csi2: mipi1-csi2 {
compatible = "rockchip,rv1106-mipi-csi2";
rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>;
status = "disabled";
};
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <2>;
status = "disabled";
};
mpp_vcodec: mpp-vcodec {
compatible = "rockchip,vcodec";
status = "disabled";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
rkcif_dvp: rkcif-dvp {
compatible = "rockchip,rkcif-dvp";
rockchip,hw = <&rkcif>;
status = "disabled";
};
rkcif_dvp_sditf: rkcif-dvp-sditf {
compatible = "rockchip,rkcif-sditf";
rockchip,cif = <&rkcif_dvp>;
status = "disabled";
};
rkcif_mipi_lvds: rkcif-mipi-lvds {
compatible = "rockchip,rkcif-mipi-lvds";
rockchip,hw = <&rkcif>;
status = "disabled";
};
rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
compatible = "rockchip,rkcif-sditf";
rockchip,cif = <&rkcif_mipi_lvds>;
status = "disabled";
};
rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
compatible = "rockchip,rkcif-mipi-lvds";
rockchip,hw = <&rkcif>;
status = "disabled";
};
rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
compatible = "rockchip,rkcif-sditf";
rockchip,cif = <&rkcif_mipi_lvds1>;
status = "disabled";
};
rkisp_vir0: rkisp-vir0 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
dvbm = <&rkdvbm>;
status = "disabled";
};
rkisp_vir1: rkisp-vir1 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
status = "disabled";
};
rkisp_vir2: rkisp-vir2 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
status = "disabled";
};
rkisp_vir3: rkisp-vir3 {
compatible = "rockchip,rkisp-vir";
rockchip,hw = <&rkisp>;
status = "disabled";
};
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-config";
status = "okay";
rockchip,sleep-io-config = <
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(0)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(1)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_DOWN
| RKPM_IO_CFG_ID(2)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_UP
| RKPM_IO_CFG_ID(3)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_UP
| RKPM_IO_CFG_ID(4)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_NONE
| RKPM_IO_CFG_ID(5)
)
(0
| RKPM_IO_CFG_IOMUX_GPIO
| RKPM_IO_CFG_GPIO_DIR_INPUT
| RKPM_IO_CFG_PULL_NONE
| RKPM_IO_CFG_ID(6)
)
>;
};
rockchip_system_monitor: rockchip-system-monitor {
compatible = "rockchip,system-monitor";
rockchip,thermal-zone = "soc-thermal";
};
thermal_zones: thermal-zones {
soc_thermal: soc-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
sustainable-power = <2100>; /* milliwatts */
thermal-sensors = <&tsadc 0>;
trips {
threshold: trip-point-0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point-1 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc_crit: soc-crit {
/* millicelsius */
temperature = <115000>;
/* millicelsius */
hysteresis = <2000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
grf: syscon@ff000000 {
compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd";
reg = <0xff000000 0x68000>;
grf_cru: grf-clock-controller {
compatible = "rockchip,rv1106-grf-cru";
#clock-cells = <1>;
};
reboot_mode: reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x20200>;
mode-bootloader = <BOOT_BL_DOWNLOAD>;
mode-charge = <BOOT_CHARGING>;
mode-fastboot = <BOOT_FASTBOOT>;
mode-loader = <BOOT_BL_DOWNLOAD>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-ums = <BOOT_UMS>;
mode-panic = <BOOT_PANIC>;
mode-watchdog = <BOOT_WATCHDOG>;
};
rgb: rgb {
compatible = "rockchip,rv1106-rgb";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
rgb_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_rgb>;
};
};
};
};
rknpor_powergood: rknpor-powergood {
compatible = "rockchip,rv1106-npor-powergood";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
};
rtc: rtc@ff1c0000 {
compatible = "rockchip,rv1106-rtc";
reg = <0xff1c0000 0x1000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_VI_RTC_PHY>, <&cru PCLK_VI_RTC_TEST>;
clock-names = "pclk_phy", "pclk_test";
assigned-clocks = <&cru PCLK_VI_RTC_PHY>;
assigned-clock-rates = <24000000>;
status = "disabled";
};
gic: interrupt-controller@ff1f0000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0xff1f1000 0x1000>,
<0xff1f2000 0x2000>,
<0xff1f4000 0x2000>,
<0xff1f6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
};
arm-debug@ff200000 {
compatible = "rockchip,debug";
reg = <0xff200000 0x1000>;
};
pvtm@ff240000 {
compatible = "rockchip,rv1106-core-pvtm";
reg = <0xff240000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
pvtm@0 {
reg = <0>;
clocks = <&cru CLK_PVTM_CORE>;
clock-names = "clk";
resets = <&cru SRST_PVTM_CORE>, <&cru SRST_P_PVTM_CORE>;
reset-names = "rst", "rst-p";
};
};
pmu: power-management@ff300000 {
compatible = "rockchip,rv1106-pmu", "syscon";
reg = <0xff300000 0x1000>;
};
i2c0: i2c@ff310000 {
compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
reg = <0xff310000 0x1000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c0m0_xfer>;
status = "disabled";
};
i2c1: i2c@ff320000 {
compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
reg = <0xff320000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c1m0_xfer>;
status = "disabled";
};
dsm: codec-digital@ff340000 {
compatible = "rockchip,rv1106-codec-digital", "rockchip,codec-digital-v1";
reg = <0xff340000 0x1000>;
clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>;
clock-names = "dac", "pclk";
resets = <&cru SRST_M_DSM>;
reset-names = "reset" ;
rockchip,grf = <&grf>;
rockchip,pwm-output-mode;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&dsmaudio_pins>;
status = "disabled";
};
pwm0: pwm@ff350000 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff350000 0x10>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm0m0_pins>;
clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm1: pwm@ff350010 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff350010 0x10>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm1m0_pins>;
clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm2: pwm@ff350020 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff350020 0x10>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm2m0_pins>;
clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm3: pwm@ff350030 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff350030 0x10>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm3m0_pins>;
clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm4: pwm@ff360000 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff360000 0x10>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm4m0_pins>;
clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm5: pwm@ff360010 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff360010 0x10>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm5m0_pins>;
clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm6: pwm@ff360020 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff360020 0x10>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm6m0_pins>;
clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm7: pwm@ff360030 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff360030 0x10>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm7m0_pins>;
clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pmu_mailbox: mailbox@ff378000 {
compatible = "rockchip,rv1106-mailbox",
"rockchip,rk3368-mailbox";
reg = <0xff378000 0x200>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_PMU_MAILBOX>;
clock-names = "pclk_mailbox";
#mbox-cells = <1>;
status = "disabled";
};
pmuioc: syscon@ff388000 {
compatible = "rockchip,rv1106-pmuioc", "syscon";
reg = <0xff388000 0x1000>;
};
pvtm@ff390000 {
compatible = "rockchip,rv1106-pmu-pvtm";
reg = <0xff390000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
pvtm@0 {
reg = <1>;
clocks = <&cru CLK_PVTM_PMU>, <&cru PCLK_PVTM_PMU>;
clock-names = "clk", "pclk";
resets = <&cru SRST_PVTM_PMU>, <&cru SRST_P_PVTM_PMU>;
reset-names = "rst", "rst-p";
};
};
cru: clock-controller@ff3a0000 {
compatible = "rockchip,rv1106-cru";
reg = <0xff3a0000 0x20000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ARMCLK>,
<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
<&cru HCLK_PMU_ROOT>;
assigned-clock-rates =
<1188000000>, <1000000000>,
<1104000000>,
<400000000>, <200000000>,
<100000000>, <300000000>,
<100000000>, <100000000>,
<200000000>;
};
saradc: saradc@ff3c0000 {
compatible = "rockchip,rv1106-saradc";
reg = <0xff3c0000 0x200>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_P_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};
tsadc: tsadc@ff3c8000 {
compatible = "rockchip,rv1106-tsadc";
reg = <0xff3c8000 0x1000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>;
clock-names = "tsadc", "apb_pclk", "tsen";
assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
assigned-clock-rates = <1000000>, <12000000>;
resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
reset-names = "tsadc", "tsadc-apb";
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <120000>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
status = "disabled";
};
otp: otp@ff3d0000 {
compatible = "rockchip,rv1106-otp";
reg = <0xff3d0000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
<&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>,
<&cru CLK_OTPC_ARB>, <&cru CLK_PMC_OTP>;
clock-names = "usr", "sbpi", "apb", "phy", "arb", "pmc";
resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>,
<&cru SRST_P_OTPC_NS>, <&cru SRST_P_OTP_MASK>,
<&cru SRST_OTPC_ARB>, <&cru SRST_PMC_OTP>;
reset-names = "usr", "sbpi", "apb", "phy", "arb", "pmc";
/* Data cells */
cpu_code: cpu-code@2 {
reg = <0x02 0x2>;
};
otp_cpu_version: cpu-version@8 {
reg = <0x08 0x1>;
bits = <3 3>;
};
otp_id: id@a {
reg = <0x0a 0x10>;
};
cpu_leakage: cpu-leakage@1a {
reg = <0x1a 0x1>;
};
log_leakage: log-leakage@1b {
reg = <0x1b 0x1>;
};
macphy_bgs: macphy-bgs@2d {
reg = <0x2d 0x1>;
};
macphy_txlevel: macphy-txlevel@2e {
reg = <0x2e 0x2>;
};
};
u2phy: usb2-phy@ff3e0000 {
compatible = "rockchip,rv1106-usb2phy";
reg = <0xff3e0000 0x8000>;
rockchip,usbgrf = <&grf>;
clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
clock-names = "phyclk", "pclk";
resets = <&cru SRST_USBPHY_POR>, <&cru SRST_P_USBPHY>;
reset-names = "u2phy", "u2phy-apb";
#clock-cells = <0>;
status = "disabled";
u2phy_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate", "disconnect";
status = "disabled";
};
};
csi2_dphy_hw: csi2-dphy-hw@ff3e8000 {
compatible = "rockchip,rv1106-csi2-dphy-hw";
reg = <0xff3e8000 0x8000>;
clocks = <&cru PCLK_MIPICSIPHY>;
clock-names = "pclk";
resets = <&cru SRST_P_MIPICSIPHY>;
reset-names = "srst_p_csiphy";
rockchip,grf = <&grf>;
status = "disabled";
};
dmac: dma-controller@ff420000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xff420000 0x4000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
arm,pl330-periph-burst;
};
crypto: crypto@ff440000 {
compatible = "rockchip,crypto-v3";
reg = <0xff440000 0x2000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
<&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
clock-names = "aclk", "hclk", "sclk", "pka";
assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
assigned-clock-rates = <200000000>, <200000000>;
resets = <&cru SRST_CORE_CRYPTO>;
reset-names = "crypto-rst";
status = "disabled";
};
rng: rng@ff448000 {
compatible = "rockchip,trngv1";
reg = <0xff448000 0x200>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_TRNG_NS>;
clock-names = "hclk_trng";
resets = <&cru SRST_H_TRNG_NS>;
reset-names = "reset";
status = "disabled";
};
i2c2: i2c@ff450000 {
compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
reg = <0xff450000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m0_xfer>;
status = "disabled";
};
i2c3: i2c@ff460000 {
compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
reg = <0xff460000 0x1000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c3m0_xfer>;
status = "disabled";
};
i2c4: i2c@ff470000 {
compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
reg = <0xff470000 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c4m0_xfer>;
status = "disabled";
};
acodec: acodec@ff480000 {
compatible = "rockchip,rv1106-codec";
reg = <0xff480000 0x1000>;
rockchip,grf = <&grf>;
clocks = <&cru PCLK_ACODEC>,
<&cru MCLK_ACODEC_TX>,
<&cru MCLK_I2S0_8CH_TX>;
clock-names = "pclk_acodec", "mclk_acodec", "mclk_cpu";
resets = <&cru SRST_P_ACODEC>;
reset-names = "acodec-reset";
acodec,micbias;
init-mic-gain = <0x22>; /* Left:20dB Right:20dB */
status = "disabled";
};
pwm8: pwm@ff490000 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff490000 0x10>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm8m0_pins>;
clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm9: pwm@ff490010 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff490010 0x10>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm9m0_pins>;
clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm10: pwm@ff490020 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff490020 0x10>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm10m0_pins>;
clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm11: pwm@ff490030 {
compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
reg = <0xff490030 0x10>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm11m0_pins>;
clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
clock-names = "pwm", "pclk";
status = "disabled";
};
uart0: serial@ff4a0000 {
compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
reg = <0xff4a0000 0x100>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac 7>, <&dmac 6>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
status = "disabled";
};
uart1: serial@ff4b0000 {
compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
reg = <0xff4b0000 0x100>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac 9>, <&dmac 8>;
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
status = "disabled";
};
uart2: serial@ff4c0000 {
compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
reg = <0xff4c0000 0x100>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;