/
rv1126.dtsi
2680 lines (2428 loc) · 68.9 KB
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rv1126.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/clock/rv1126-cru.h>
#include <dt-bindings/power/rv1126-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include <dt-bindings/suspend/rockchip-rv1126.h>
#include <dt-bindings/thermal/thermal.h>
#include "rv1126-dram-default-timing.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "rockchip,rv1126";
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
mmc0 = &emmc;
mmc1 = &sdmmc;
mmc2 = &sdio;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
spi0 = &spi0;
spi1 = &spi1;
dphy0 = &csi_dphy0;
dphy1 = &csi_dphy1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@f00 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
dynamic-power-coefficient = <60>;
#cooling-cells = <2>;
cpu-idle-states = <&CPU_SLEEP>;
};
cpu1: cpu@f01 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf01>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
dynamic-power-coefficient = <60>;
cpu-idle-states = <&CPU_SLEEP>;
};
cpu2: cpu@f02 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf02>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
dynamic-power-coefficient = <60>;
cpu-idle-states = <&CPU_SLEEP>;
};
cpu3: cpu@f03 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf03>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
dynamic-power-coefficient = <60>;
cpu-idle-states = <&CPU_SLEEP>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP: cpu-sleep {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <120>;
exit-latency-us = <250>;
min-residency-us = <900>;
};
};
};
cpu0_opp_table: cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
nvmem-cells = <&cpu_leakage>, <&cpu_performance>;
nvmem-cell-names = "leakage", "performance";
rockchip,reboot-freq = <816000>;
rockchip,temp-freq-table = <
100000 1296000
>;
clocks = <&cru PLL_APLL>;
rockchip,bin-scaling-sel = <
0 5
1 9
>;
rockchip,bin-voltage-sel = <
1 0
>;
rockchip,pvtm-voltage-sel = <
0 100500 1
100501 104500 2
104501 109500 3
109501 999999 4
>;
rockchip,pvtm-freq = <408000>;
rockchip,pvtm-volt = <800000>;
rockchip,pvtm-ch = <0 0>;
rockchip,pvtm-sample-time = <1000>;
rockchip,pvtm-number = <10>;
rockchip,pvtm-error = <1000>;
rockchip,pvtm-ref-temp = <37>;
rockchip,pvtm-temp-prop = <(-40) 13>;
rockchip,pvtm-thermal-zone = "cpu-thermal";
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <725000 725000 1000000>;
opp-microvolt-L0 = <725000 725000 1000000>;
clock-latency-ns = <40000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <725000 725000 1000000>;
opp-microvolt-L0 = <725000 725000 1000000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <725000 725000 1000000>;
opp-microvolt-L0 = <750000 750000 1000000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <775000 775000 1000000>;
opp-microvolt-L0 = <800000 800000 1000000>;
opp-microvolt-L1 = <775000 775000 1000000>;
opp-microvolt-L2 = <775000 775000 1000000>;
opp-microvolt-L3 = <750000 750000 1000000>;
opp-microvolt-L4 = <725000 725000 1000000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <850000 850000 1000000>;
opp-microvolt-L0 = <875000 875000 1000000>;
opp-microvolt-L1 = <850000 850000 1000000>;
opp-microvolt-L2 = <850000 850000 1000000>;
opp-microvolt-L3 = <825000 825000 1000000>;
opp-microvolt-L4 = <800000 800000 1000000>;
clock-latency-ns = <40000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <875000 875000 1000000>;
opp-microvolt-L0 = <925000 925000 1000000>;
opp-microvolt-L1 = <875000 875000 1000000>;
opp-microvolt-L2 = <875000 875000 1000000>;
opp-microvolt-L3 = <850000 850000 1000000>;
opp-microvolt-L4 = <825000 825000 1000000>;
clock-latency-ns = <40000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <925000 925000 1000000>;
opp-microvolt-L0 = <975000 975000 1000000>;
opp-microvolt-L1 = <925000 925000 1000000>;
opp-microvolt-L2 = <925000 925000 1000000>;
opp-microvolt-L3 = <900000 900000 1000000>;
opp-microvolt-L4 = <875000 875000 1000000>;
clock-latency-ns = <40000>;
};
opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <975000 975000 1000000>;
opp-microvolt-L1 = <975000 975000 1000000>;
opp-microvolt-L2 = <950000 950000 1000000>;
opp-microvolt-L3 = <925000 925000 1000000>;
opp-microvolt-L4 = <900000 900000 1000000>;
clock-latency-ns = <40000>;
};
};
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&otp_id>, <&otp_cpu_code>;
nvmem-cell-names = "id", "cpu-code";
};
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
bus_soc: bus-soc {
compatible = "rockchip,rv1126-bus";
rockchip,busfreq-policy = "smc";
soc-bus0 {
bus-id = <0>;
cfg-val = <0x00300020>;
enable-msk = <0x7144>;
status = "okay";
};
soc-bus1 {
bus-id = <1>;
cfg-val = <0x00300020>;
enable-msk = <0x70ff>;
status = "disabled";
};
soc-bus2 {
bus-id = <2>;
cfg-val = <0x00300020>;
enable-msk = <0x70ff>;
status = "disabled";
};
soc-bus3 {
bus-id = <3>;
cfg-val = <0x00300020>;
enable-msk = <0x70ff>;
status = "disabled";
};
soc-bus4 {
bus-id = <4>;
cfg-val = <0x00300020>;
enable-msk = <0x7011>;
status = "disabled";
};
soc-bus5 {
bus-id = <5>;
cfg-val = <0x00300020>;
enable-msk = <0x7011>;
status = "disabled";
};
soc-bus6 {
bus-id = <6>;
cfg-val = <0x00300020>;
enable-msk = <0x7011>;
status = "disabled";
};
soc-bus7 {
bus-id = <7>;
cfg-val = <0x00300020>;
enable-msk = <0x0>;
status = "disabled";
};
soc-bus8 {
bus-id = <8>;
cfg-val = <0x00300020>;
enable-msk = <0x0>;
status = "disabled";
};
soc-bus9 {
bus-id = <9>;
cfg-val = <0x00300020>;
enable-msk = <0x0>;
status = "disabled";
};
soc-bus10 {
bus-id = <10>;
cfg-val = <0x00300020>;
enable-msk = <0x0>;
status = "disabled";
};
soc-bus11 {
bus-id = <11>;
cfg-val = <0x00300020>;
enable-msk = <0x7000>;
status = "disabled";
};
};
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
status = "disabled";
logo-memory-region = <&drm_logo>;
route {
route_dsi: route-dsi {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_dsi>;
};
route_rgb: route-rgb {
status = "disabled";
logo,uboot = "logo.bmp";
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_rgb>;
};
};
};
fiq_debugger: fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;
rockchip,wake-irq = <0>;
rockchip,irq-mode-enable = <0>;
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
firmware {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
status = "disabled";
};
};
mipi_csi2: mipi-csi2 {
compatible = "rockchip,rv1126-mipi-csi2";
rockchip,hw = <&mipi_csi2_hw>;
status = "disabled";
};
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <4>;
rockchip,resetgroup-count = <4>;
status = "disabled";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
inactive;
reusable;
size = <0x800000>;
linux,cma-default;
};
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0>;
};
isp_reserved: isp {
compatible = "shared-dma-pool";
inactive;
reusable;
size = <0x10000000>;
};
ramoops: ramoops@8000000 {
compatible = "ramoops";
reg = <0x8000000 0x100000>;
record-size = <0x20000>;
console-size = <0x40000>;
ftrace-size = <0x00000>;
pmsg-size = <0x40000>;
status = "disabled";
};
};
rkcif_dvp: rkcif_dvp {
compatible = "rockchip,rkcif-dvp";
rockchip,hw = <&rkcif>;
// iommus = <&rkcif_mmu>;
memory-region = <&isp_reserved>;
status = "disabled";
};
rkcif_dvp_sditf: rkcif_dvp_sditf {
compatible = "rockchip,rkcif-sditf";
rockchip,cif = <&rkcif_dvp>;
status = "disabled";
};
rkcif_lite_mipi_lvds: rkcif_lite_mipi_lvds {
compatible = "rockchip,rkcif-mipi-lvds";
rockchip,hw = <&rkcif_lite>;
iommus = <&rkcif_lite_mmu>;
status = "disabled";
};
rkcif_lite_sditf: rkcif_lite_sditf {
compatible = "rockchip,rkcif-sditf";
rockchip,cif = <&rkcif_lite_mipi_lvds>;
status = "disabled";
};
rkcif_mipi_lvds: rkcif_mipi_lvds {
compatible = "rockchip,rkcif-mipi-lvds";
rockchip,hw = <&rkcif>;
// iommus = <&rkcif_mmu>;
memory-region = <&isp_reserved>;
status = "disabled";
};
rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf {
compatible = "rockchip,rkcif-sditf";
rockchip,cif = <&rkcif_mipi_lvds>;
status = "disabled";
};
rockchip_suspend: rockchip-suspend {
compatible = "rockchip,pm-rv1126";
status = "disabled";
rockchip,sleep-debug-en = <0>;
rockchip,sleep-mode-config = <
(0
| RKPM_SLP_ARMOFF
| RKPM_SLP_PMU_PMUALIVE_32K
| RKPM_SLP_PMU_DIS_OSC
| RKPM_SLP_PMIC_LP
)
>;
rockchip,wakeup-config = <
(0
| RKPM_GPIO_WKUP_EN
)
>;
};
rockchip_system_monitor: rockchip-system-monitor {
compatible = "rockchip,system-monitor";
};
thermal_zones: thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
sustainable-power = <875>; /* milliwatts */
k_pu = <75>;
k_po = <175>;
k_i = <0>;
thermal-sensors = <&cpu_tsadc 0>;
trips {
threshold: trip-point-0 {
/* millicelsius */
temperature = <75000>;
/* millicelsius */
hysteresis = <2000>;
type = "passive";
};
target: trip-point-1 {
/* millicelsius */
temperature = <85000>;
/* millicelsius */
hysteresis = <2000>;
type = "passive";
};
soc_crit: soc-crit {
/* millicelsius */
temperature = <115000>;
/* millicelsius */
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map1 {
trip = <&target>;
cooling-device =
<&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1024>;
};
map2 {
trip = <&target>;
cooling-device =
<&rkvenc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <1060>;
};
};
};
npu_thermal: npu-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
sustainable-power = <977>; /* milliwatts */
thermal-sensors = <&npu_tsadc 0>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clock-frequency = <24000000>;
};
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
dummy_cpll: dummy_cpll {
compatible = "fixed-clock";
clock-frequency = <0>;
clock-output-names = "dummy_cpll";
#clock-cells = <0>;
};
gmac_clkin_m0: external-gmac-clockm0 {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clk_gmac_rgmii_clkin_m0";
#clock-cells = <0>;
};
gmac_clkini_m1: external-gmac-clockm1 {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clk_gmac_rgmii_clkin_m1";
#clock-cells = <0>;
};
grf: syscon@fe000000 {
compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
reg = <0xfe000000 0x20000>;
rgb: rgb {
compatible = "rockchip,rv1126-rgb";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
rgb_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_rgb>;
};
};
};
};
};
pmugrf: syscon@fe020000 {
compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
reg = <0xfe020000 0x1000>;
pmu_io_domains: io-domains {
compatible = "rockchip,rv1126-pmu-io-voltage-domain";
};
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x200>;
mode-bootloader = <BOOT_BL_DOWNLOAD>;
mode-charge = <BOOT_CHARGING>;
mode-fastboot = <BOOT_FASTBOOT>;
mode-loader = <BOOT_BL_DOWNLOAD>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-ums = <BOOT_UMS>;
mode-panic = <BOOT_PANIC>;
mode-watchdog = <BOOT_WATCHDOG>;
};
};
qos_usb_host: qos@fe810000 {
compatible = "syscon";
reg = <0xfe810000 0x20>;
};
qos_usb_otg: qos@fe810080 {
compatible = "syscon";
reg = <0xfe810080 0x20>;
};
qos_npu: qos@fe850000 {
compatible = "syscon";
reg = <0xfe850000 0x20>;
};
qos_emmc: qos@fe860000 {
compatible = "syscon";
reg = <0xfe860000 0x20>;
};
qos_nandc: qos@fe860080 {
compatible = "syscon";
reg = <0xfe860080 0x20>;
};
qos_sfc: qos@fe860200 {
compatible = "syscon";
reg = <0xfe860200 0x20>;
};
qos_sdio: qos@fe86c000 {
compatible = "syscon";
reg = <0xfe86c000 0x20>;
};
qos_vepu_rd0: qos@fe870000 {
compatible = "syscon";
reg = <0xfe870000 0x20>;
};
qos_vepu_rd1: qos@fe870080 {
compatible = "syscon";
reg = <0xfe870080 0x20>;
};
qos_vepu_wr: qos@fe870100 {
compatible = "syscon";
reg = <0xfe870100 0x20>;
};
qos_ispp_m0: qos@fe880000 {
compatible = "syscon";
reg = <0xfe880000 0x20>;
};
qos_ispp_m1: qos@fe880080 {
compatible = "syscon";
reg = <0xfe880080 0x20>;
};
qos_isp: qos@fe890000 {
compatible = "syscon";
reg = <0xfe890000 0x20>;
};
qos_cif_lite: qos@fe890080 {
compatible = "syscon";
reg = <0xfe890080 0x20>;
};
qos_cif: qos@fe890100 {
compatible = "syscon";
reg = <0xfe890100 0x20>;
};
qos_iep: qos@fe8a0000 {
compatible = "syscon";
reg = <0xfe8a0000 0x20>;
};
qos_rga_rd: qos@fe8a0080 {
compatible = "syscon";
reg = <0xfe8a0080 0x20>;
};
qos_rga_wr: qos@fe8a0100 {
compatible = "syscon";
reg = <0xfe8a0100 0x20>;
};
qos_vop: qos@fe8a0180 {
compatible = "syscon";
reg = <0xfe8a0180 0x20>;
};
qos_vdpu: qos@fe8b0000 {
compatible = "syscon";
reg = <0xfe8b0000 0x20>;
};
qos_jpeg: qos@fe8c0000 {
compatible = "syscon";
reg = <0xfe8c0000 0x20>;
};
qos_crypto: qos@fe8d0000 {
compatible = "syscon";
reg = <0xfe8d0000 0x20>;
};
gic: interrupt-controller@feff0000 {
compatible = "arm,gic-400";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <0>;
reg = <0xfeff1000 0x1000>,
<0xfeff2000 0x2000>,
<0xfeff4000 0x2000>,
<0xfeff6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
arm-debug@ff010000 {
compatible = "rockchip,debug";
reg = <0xff010000 0x1000>,
<0xff012000 0x1000>,
<0xff014000 0x1000>,
<0xff016000 0x1000>;
};
pvtm@ff040000 {
compatible = "rockchip,rv1126-cpu-pvtm";
reg = <0xff040000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
pvtm@0 {
reg = <0>;
clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>;
clock-names = "clk", "pclk";
resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>;
reset-names = "rst", "rst-p";
};
};
pmu: power-management@ff3e0000 {
compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
reg = <0xff3e0000 0x1000>;
power: power-controller {
compatible = "rockchip,rv1126-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
/* These power domains are grouped by VD_NPU */
pd_npu@RV1126_PD_NPU {
reg = <RV1126_PD_NPU>;
clocks = <&cru ACLK_NPU>,
<&cru HCLK_NPU>,
<&cru PCLK_PDNPU>,
<&cru CLK_CORE_NPU>;
pm_qos = <&qos_npu>;
};
/* These power domains are grouped by VD_VEPU */
pd_vepu@RV1126_PD_VEPU {
reg = <RV1126_PD_VEPU>;
clocks = <&cru ACLK_VENC>,
<&cru HCLK_VENC>,
<&cru CLK_VENC_CORE>;
pm_qos = <&qos_vepu_rd0>,
<&qos_vepu_rd1>,
<&qos_vepu_wr>;
};
/* These power domains are grouped by VD_LOGIC */
pd_crypto@RV1126_PD_CRYPTO {
reg = <RV1126_PD_CRYPTO>;
clocks = <&cru ACLK_CRYPTO>,
<&cru HCLK_CRYPTO>,
<&cru CLK_CRYPTO_CORE>,
<&cru CLK_CRYPTO_PKA>;
pm_qos = <&qos_crypto>;
};
pd_vi@RV1126_PD_VI {
reg = <RV1126_PD_VI>;
clocks = <&cru ACLK_ISP>,
<&cru HCLK_ISP>,
<&cru CLK_ISP>,
<&cru ACLK_CIF>,
<&cru HCLK_CIF>,
<&cru DCLK_CIF>,
<&cru CLK_CIF_OUT>,
<&cru CLK_MIPICSI_OUT>,
<&cru PCLK_CSIHOST>,
<&cru ACLK_CIFLITE>,
<&cru HCLK_CIFLITE>,
<&cru DCLK_CIFLITE>;
pm_qos = <&qos_isp>,
<&qos_cif_lite>,
<&qos_cif>;
};
pd_vo@RV1126_PD_VO {
reg = <RV1126_PD_VO>;
clocks = <&cru ACLK_RGA>,
<&cru HCLK_RGA>,
<&cru CLK_RGA_CORE>,
<&cru ACLK_VOP>,
<&cru HCLK_VOP>,
<&cru DCLK_VOP>,
<&cru PCLK_DSIHOST>,
<&cru ACLK_IEP>,
<&cru HCLK_IEP>,
<&cru CLK_IEP_CORE>;
pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
<&qos_vop>, <&qos_iep>;
};
pd_ispp@RV1126_PD_ISPP {
reg = <RV1126_PD_ISPP>;
clocks = <&cru ACLK_ISPP>,
<&cru HCLK_ISPP>,
<&cru CLK_ISPP>;
pm_qos = <&qos_ispp_m0>,
<&qos_ispp_m1>;
};
pd_vdpu@RV1126_PD_VDPU {
reg = <RV1126_PD_VDPU>;
clocks = <&cru ACLK_VDEC>,
<&cru HCLK_VDEC>,
<&cru CLK_VDEC_CORE>,
<&cru CLK_VDEC_CA>,
<&cru CLK_VDEC_HEVC_CA>,
<&cru ACLK_JPEG>,
<&cru HCLK_JPEG>;
pm_qos = <&qos_vdpu>,
<&qos_jpeg>;
};
pd_nvm@RV1126_PD_NVM {
reg = <RV1126_PD_NVM>;
clocks = <&cru HCLK_EMMC>,
<&cru CLK_EMMC>,
<&cru HCLK_NANDC>,
<&cru CLK_NANDC>,
<&cru HCLK_SFC>,
<&cru HCLK_SFCXIP>,
<&cru SCLK_SFC>;
pm_qos = <&qos_emmc>,
<&qos_nandc>,
<&qos_sfc>;
};
pd_sdio@RV1126_PD_SDIO {
reg = <RV1126_PD_SDIO>;
clocks = <&cru HCLK_SDIO>,
<&cru CLK_SDIO>;
pm_qos = <&qos_sdio>;
};
pd_usb@RV1126_PD_USB {
reg = <RV1126_PD_USB>;
clocks = <&cru HCLK_USBHOST>,
<&cru HCLK_USBHOST_ARB>,
<&cru CLK_USBHOST_UTMI_OHCI>,
<&cru ACLK_USBOTG>,
<&cru CLK_USBOTG_REF>;
pm_qos = <&qos_usb_host>,
<&qos_usb_otg>;
};
};
};
i2c0: i2c@ff3f0000 {
compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
reg = <0xff3f0000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
status = "disabled";
};
i2c2: i2c@ff400000 {
compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
reg = <0xff400000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
rockchip,grf = <&pmugrf>;
clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
status = "disabled";
};
amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dmac: dma-controller@ff4e0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xff4e0000 0x4000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
arm,pl330-periph-burst;
};
};
uart1: serial@ff410000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff410000 0x100>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
dmas = <&dmac 7>, <&dmac 6>;
clock-frequency = <24000000>;
clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
status = "disabled";
};
pwm0: pwm@ff430000 {
compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
reg = <0xff430000 0x10>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm0m0_pins>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm1: pwm@ff430010 {
compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
reg = <0xff430010 0x10>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm1m0_pins>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm2: pwm@ff430020 {
compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
reg = <0xff430020 0x10>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm2m0_pins>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
status = "disabled";
};
pwm3: pwm@ff430030 {
compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
reg = <0xff430030 0x10>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
pinctrl-names = "active";
pinctrl-0 = <&pwm3m0_pins>;