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rockchip_drm_vop.c
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rockchip_drm_vop.c
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/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Author:Mark Yao <mark.yao@rock-chips.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <drm/drm.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_flip_work.h>
#include <drm/drm_plane_helper.h>
#include <dt-bindings/clock/rk_system_status.h>
#include <linux/debugfs.h>
#include <linux/fixp-arith.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/iopoll.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/component.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/reset.h>
#include <linux/delay.h>
#include <linux/sort.h>
#include <soc/rockchip/rockchip_dmc.h>
#include <soc/rockchip/rockchip-system-status.h>
#include <uapi/drm/rockchip_drm.h>
#include <uapi/linux/videodev2.h>
#include "rockchip_drm_drv.h"
#include "rockchip_drm_gem.h"
#include "rockchip_drm_fb.h"
#include "rockchip_drm_vop.h"
#include "rockchip_drm_backlight.h"
#define MAX_VOPS 2
#define VOP_REG_SUPPORT(vop, reg) \
(reg.mask && \
(!reg.major || \
(reg.major == VOP_MAJOR(vop->version) && \
reg.begin_minor <= VOP_MINOR(vop->version) && \
reg.end_minor >= VOP_MINOR(vop->version))))
#define VOP_WIN_SUPPORT(vop, win, name) \
VOP_REG_SUPPORT(vop, win->phy->name)
#define VOP_WIN_SCL_EXT_SUPPORT(vop, win, name) \
(win->phy->scl->ext && \
VOP_REG_SUPPORT(vop, win->phy->scl->ext->name))
#define VOP_CTRL_SUPPORT(vop, name) \
VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
#define VOP_INTR_SUPPORT(vop, name) \
VOP_REG_SUPPORT(vop, vop->data->intr->name)
#define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
#define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
do { \
if (VOP_REG_SUPPORT(vop, reg)) \
__REG_SET(vop, off + reg.offset, mask, reg.shift, \
v, reg.write_mask, relaxed); \
else \
dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
} while(0)
#define REG_SET(x, name, off, reg, v, relaxed) \
_REG_SET(x, name, off, reg, reg.mask, v, relaxed)
#define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
_REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
#define VOP_WIN_SET(x, win, name, v) \
REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
#define VOP_WIN_SET_EXT(x, win, ext, name, v) \
REG_SET(x, name, 0, win->ext->name, v, true)
#define VOP_SCL_SET(x, win, name, v) \
REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
#define VOP_SCL_SET_EXT(x, win, name, v) \
REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
#define VOP_CTRL_SET(x, name, v) \
REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
#define VOP_INTR_GET(vop, name) \
vop_read_reg(vop, 0, &vop->data->ctrl->name)
#define VOP_INTR_SET(vop, name, v) \
REG_SET(vop, name, 0, vop->data->intr->name, \
v, false)
#define VOP_INTR_SET_MASK(vop, name, mask, v) \
REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
mask, v, false)
#define VOP_INTR_SET_TYPE(vop, name, type, v) \
do { \
int i, reg = 0, mask = 0; \
for (i = 0; i < vop->data->intr->nintrs; i++) { \
if (vop->data->intr->intrs[i] & type) { \
reg |= (v) << i; \
mask |= 1 << i; \
} \
} \
VOP_INTR_SET_MASK(vop, name, mask, reg); \
} while (0)
#define VOP_INTR_GET_TYPE(vop, name, type) \
vop_get_intr_type(vop, &vop->data->intr->name, type)
#define VOP_CTRL_GET(x, name) \
vop_read_reg(x, 0, &vop->data->ctrl->name)
#define VOP_WIN_GET(x, win, name) \
vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
#define VOP_WIN_NAME(win, name) \
(vop_get_win_phy(win, &win->phy->name)->name)
#define VOP_WIN_GET_YRGBADDR(vop, win) \
vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
#define VOP_GRF_SET(vop, reg, v) \
do { \
if (vop->data->grf_ctrl) { \
vop_grf_writel(vop, vop->data->grf_ctrl->reg, v); \
} \
} while (0)
#define to_vop(x) container_of(x, struct vop, crtc)
#define to_vop_win(x) container_of(x, struct vop_win, base)
#define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
struct vop_zpos {
int win_id;
int zpos;
};
enum vop_pending {
VOP_PENDING_FB_UNREF,
};
struct vop_plane_state {
struct drm_plane_state base;
int format;
int zpos;
unsigned int logo_ymirror;
struct drm_rect src;
struct drm_rect dest;
dma_addr_t yrgb_mst;
dma_addr_t uv_mst;
void *yrgb_kvaddr;
const uint32_t *y2r_table;
const uint32_t *r2r_table;
const uint32_t *r2y_table;
int eotf;
bool y2r_en;
bool r2r_en;
bool r2y_en;
int color_space;
unsigned int csc_mode;
bool enable;
int global_alpha;
int blend_mode;
unsigned long offset;
int pdaf_data_type;
};
struct rockchip_mcu_timing {
int mcu_pix_total;
int mcu_cs_pst;
int mcu_cs_pend;
int mcu_rw_pst;
int mcu_rw_pend;
int mcu_hold_mode;
};
struct vop_win {
struct vop_win *parent;
struct drm_plane base;
int win_id;
int area_id;
uint32_t offset;
enum drm_plane_type type;
const struct vop_win_phy *phy;
const struct vop_csc *csc;
const uint32_t *data_formats;
uint32_t nformats;
u64 feature;
struct vop *vop;
struct drm_property *rotation_prop;
struct vop_plane_state state;
};
struct vop {
struct drm_crtc crtc;
struct device *dev;
struct drm_device *drm_dev;
struct dentry *debugfs;
struct drm_info_list *debugfs_files;
struct drm_property *plane_zpos_prop;
struct drm_property *plane_feature_prop;
struct drm_property *feature_prop;
bool is_iommu_enabled;
bool is_iommu_needed;
bool is_enabled;
bool mode_update;
u32 version;
struct drm_tv_connector_state active_tv_state;
bool pre_overlay;
/* mutex vsync_ work */
struct mutex vsync_mutex;
bool vsync_work_pending;
bool loader_protect;
struct completion dsp_hold_completion;
/* protected by dev->event_lock */
struct drm_pending_vblank_event *event;
struct drm_flip_work fb_unref_work;
unsigned long pending;
struct completion line_flag_completion;
const struct vop_data *data;
int num_wins;
uint32_t *regsbak;
void __iomem *regs;
struct regmap *grf;
/* physical map length of vop register */
uint32_t len;
void __iomem *lut_regs;
u32 *lut;
u32 lut_len;
bool lut_active;
void __iomem *cabc_lut_regs;
u32 cabc_lut_len;
/* one time only one process allowed to config the register */
spinlock_t reg_lock;
/* lock vop irq reg */
spinlock_t irq_lock;
/* mutex vop enable and disable */
struct mutex vop_lock;
unsigned int irq;
/* vop AHP clk */
struct clk *hclk;
/* vop dclk */
struct clk *dclk;
/* vop share memory frequency */
struct clk *aclk;
/* vop source handling, optional */
struct clk *dclk_source;
/* vop dclk reset */
struct reset_control *dclk_rst;
struct rockchip_dclk_pll *pll;
struct rockchip_mcu_timing mcu_timing;
struct vop_win win[];
};
static void vop_lock(struct vop *vop)
{
mutex_lock(&vop->vop_lock);
rockchip_dmcfreq_lock();
}
static void vop_unlock(struct vop *vop)
{
rockchip_dmcfreq_unlock();
mutex_unlock(&vop->vop_lock);
}
static inline void vop_grf_writel(struct vop *vop, struct vop_reg reg, u32 v)
{
u32 val = 0;
if (IS_ERR_OR_NULL(vop->grf))
return;
if (VOP_REG_SUPPORT(vop, reg)) {
val = (v << reg.shift) | (reg.mask << (reg.shift + 16));
regmap_write(vop->grf, reg.offset, val);
}
}
static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
{
writel(v, vop->regs + offset);
vop->regsbak[offset >> 2] = v;
}
static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
{
return readl(vop->regs + offset);
}
static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
const struct vop_reg *reg)
{
return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
}
static inline void vop_mask_write(struct vop *vop, uint32_t offset,
uint32_t mask, uint32_t shift, uint32_t v,
bool write_mask, bool relaxed)
{
if (!mask)
return;
if (write_mask) {
v = ((v & mask) << shift) | (mask << (shift + 16));
} else {
uint32_t cached_val = vop->regsbak[offset >> 2];
v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
vop->regsbak[offset >> 2] = v;
}
if (relaxed)
writel_relaxed(v, vop->regs + offset);
else
writel(v, vop->regs + offset);
}
static inline const struct vop_win_phy *
vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
{
if (!reg->mask && win->parent)
return win->parent->phy;
return win->phy;
}
static inline uint32_t vop_get_intr_type(struct vop *vop,
const struct vop_reg *reg, int type)
{
uint32_t i, ret = 0;
uint32_t regs = vop_read_reg(vop, 0, reg);
for (i = 0; i < vop->data->intr->nintrs; i++) {
if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
ret |= vop->data->intr->intrs[i];
}
return ret;
}
static void vop_load_hdr2sdr_table(struct vop *vop)
{
int i;
const struct vop_hdr_table *table = vop->data->hdr_table;
uint32_t hdr2sdr_eetf_oetf_yn[33];
for (i = 0; i < 33; i++)
hdr2sdr_eetf_oetf_yn[i] = table->hdr2sdr_eetf_yn[i] +
(table->hdr2sdr_bt1886oetf_yn[i] << 16);
vop_writel(vop, table->hdr2sdr_eetf_oetf_y0_offset,
hdr2sdr_eetf_oetf_yn[0]);
for (i = 1; i < 33; i++)
vop_writel(vop,
table->hdr2sdr_eetf_oetf_y1_offset + (i - 1) * 4,
hdr2sdr_eetf_oetf_yn[i]);
vop_writel(vop, table->hdr2sdr_sat_y0_offset,
table->hdr2sdr_sat_yn[0]);
for (i = 1; i < 9; i++)
vop_writel(vop, table->hdr2sdr_sat_y1_offset + (i - 1) * 4,
table->hdr2sdr_sat_yn[i]);
VOP_CTRL_SET(vop, hdr2sdr_src_min, table->hdr2sdr_src_range_min);
VOP_CTRL_SET(vop, hdr2sdr_src_max, table->hdr2sdr_src_range_max);
VOP_CTRL_SET(vop, hdr2sdr_normfaceetf, table->hdr2sdr_normfaceetf);
VOP_CTRL_SET(vop, hdr2sdr_dst_min, table->hdr2sdr_dst_range_min);
VOP_CTRL_SET(vop, hdr2sdr_dst_max, table->hdr2sdr_dst_range_max);
VOP_CTRL_SET(vop, hdr2sdr_normfacgamma, table->hdr2sdr_normfacgamma);
}
static void vop_load_sdr2hdr_table(struct vop *vop, uint32_t cmd)
{
int i;
const struct vop_hdr_table *table = vop->data->hdr_table;
uint32_t sdr2hdr_eotf_oetf_yn[65];
uint32_t sdr2hdr_oetf_dx_dxpow[64];
for (i = 0; i < 65; i++) {
if (cmd == SDR2HDR_FOR_BT2020)
sdr2hdr_eotf_oetf_yn[i] =
table->sdr2hdr_bt1886eotf_yn_for_bt2020[i] +
(table->sdr2hdr_st2084oetf_yn_for_bt2020[i] << 18);
else if (cmd == SDR2HDR_FOR_HDR)
sdr2hdr_eotf_oetf_yn[i] =
table->sdr2hdr_bt1886eotf_yn_for_hdr[i] +
(table->sdr2hdr_st2084oetf_yn_for_hdr[i] << 18);
else if (cmd == SDR2HDR_FOR_HLG_HDR)
sdr2hdr_eotf_oetf_yn[i] =
table->sdr2hdr_bt1886eotf_yn_for_hlg_hdr[i] +
(table->sdr2hdr_st2084oetf_yn_for_hlg_hdr[i] << 18);
}
vop_writel(vop, table->sdr2hdr_eotf_oetf_y0_offset,
sdr2hdr_eotf_oetf_yn[0]);
for (i = 1; i < 65; i++)
vop_writel(vop, table->sdr2hdr_eotf_oetf_y1_offset +
(i - 1) * 4, sdr2hdr_eotf_oetf_yn[i]);
for (i = 0; i < 64; i++) {
sdr2hdr_oetf_dx_dxpow[i] = table->sdr2hdr_st2084oetf_dxn[i] +
(table->sdr2hdr_st2084oetf_dxn_pow2[i] << 16);
vop_writel(vop, table->sdr2hdr_oetf_dx_dxpow1_offset + i * 4,
sdr2hdr_oetf_dx_dxpow[i]);
}
for (i = 0; i < 63; i++)
vop_writel(vop, table->sdr2hdr_oetf_xn1_offset + i * 4,
table->sdr2hdr_st2084oetf_xn[i]);
}
static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
{
int i;
/*
* so far the csc offset is not 0 and in the feature the csc offset
* impossible be 0, so when the offset is 0, should return here.
*/
if (!table || offset == 0)
return;
for (i = 0; i < 8; i++)
vop_writel(vop, offset + i * 4, table[i]);
}
static inline void vop_cfg_done(struct vop *vop)
{
VOP_CTRL_SET(vop, cfg_done, 1);
}
static bool vop_is_allwin_disabled(struct vop *vop)
{
int i;
for (i = 0; i < vop->num_wins; i++) {
struct vop_win *win = &vop->win[i];
if (VOP_WIN_GET(vop, win, enable) != 0)
return false;
}
return true;
}
static void vop_disable_allwin(struct vop *vop)
{
int i;
for (i = 0; i < vop->num_wins; i++) {
struct vop_win *win = &vop->win[i];
if (win->phy->scl && win->phy->scl->ext) {
VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
}
VOP_WIN_SET(vop, win, enable, 0);
VOP_WIN_SET(vop, win, gate, 0);
}
}
static bool vop_fs_irq_is_active(struct vop *vop)
{
if (VOP_MAJOR(vop->version) == 3 && VOP_MINOR(vop->version) >= 7)
return VOP_INTR_GET_TYPE(vop, status, FS_FIELD_INTR);
else
return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
}
static bool vop_line_flag_is_active(struct vop *vop)
{
return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
}
static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
{
writel(v, vop->lut_regs + offset);
}
static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
{
return readl(vop->lut_regs + offset);
}
static inline void vop_write_cabc_lut(struct vop *vop, uint32_t offset, uint32_t v)
{
writel(v, vop->cabc_lut_regs + offset);
}
static bool has_rb_swapped(uint32_t format)
{
switch (format) {
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
case DRM_FORMAT_BGR888:
case DRM_FORMAT_BGR565:
return true;
default:
return false;
}
}
static enum vop_data_format vop_convert_format(uint32_t format)
{
switch (format) {
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
return VOP_FMT_ARGB8888;
case DRM_FORMAT_RGB888:
case DRM_FORMAT_BGR888:
return VOP_FMT_RGB888;
case DRM_FORMAT_RGB565:
case DRM_FORMAT_BGR565:
return VOP_FMT_RGB565;
case DRM_FORMAT_NV12:
case DRM_FORMAT_NV12_10:
return VOP_FMT_YUV420SP;
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV16_10:
return VOP_FMT_YUV422SP;
case DRM_FORMAT_NV24:
case DRM_FORMAT_NV24_10:
return VOP_FMT_YUV444SP;
case DRM_FORMAT_RGB332:
case DRM_FORMAT_BGR233:
return VOP_RAW8;
default:
DRM_ERROR("unsupport format[%08x]\n", format);
return -EINVAL;
}
}
static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode)
{
/*
* FIXME:
*
* There is no media type for YUV444 output,
* so when out_mode is AAAA or P888, assume output is YUV444 on
* yuv format.
*
* From H/W testing, YUV444 mode need a rb swap.
*/
if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
(output_mode == ROCKCHIP_OUT_MODE_AAAA ||
output_mode == ROCKCHIP_OUT_MODE_P888))
return true;
else
return false;
}
static bool is_yuv_output(uint32_t bus_format)
{
switch (bus_format) {
case MEDIA_BUS_FMT_YUV8_1X24:
case MEDIA_BUS_FMT_YUV10_1X30:
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
return true;
default:
return false;
}
}
static bool is_yuv_support(uint32_t format)
{
switch (format) {
case DRM_FORMAT_NV12:
case DRM_FORMAT_NV12_10:
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV16_10:
case DRM_FORMAT_NV24:
case DRM_FORMAT_NV24_10:
return true;
default:
return false;
}
}
static bool is_yuv_10bit(uint32_t format)
{
switch (format) {
case DRM_FORMAT_NV12_10:
case DRM_FORMAT_NV16_10:
case DRM_FORMAT_NV24_10:
return true;
default:
return false;
}
}
static bool is_alpha_support(uint32_t format)
{
switch (format) {
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
return true;
default:
return false;
}
}
static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
uint32_t dst, bool is_horizontal,
int vsu_mode, int *vskiplines)
{
uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
if (is_horizontal) {
if (mode == SCALE_UP)
val = GET_SCL_FT_BIC(src, dst);
else if (mode == SCALE_DOWN)
val = GET_SCL_FT_BILI_DN(src, dst);
} else {
if (mode == SCALE_UP) {
if (vsu_mode == SCALE_UP_BIL)
val = GET_SCL_FT_BILI_UP(src, dst);
else
val = GET_SCL_FT_BIC(src, dst);
} else if (mode == SCALE_DOWN) {
if (vskiplines) {
*vskiplines = scl_get_vskiplines(src, dst);
val = scl_get_bili_dn_vskip(src, dst,
*vskiplines);
} else {
val = GET_SCL_FT_BILI_DN(src, dst);
}
}
}
return val;
}
static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
uint32_t src_w, uint32_t src_h, uint32_t dst_w,
uint32_t dst_h, uint32_t pixel_format)
{
uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
uint16_t cbcr_hor_scl_mode = SCALE_NONE;
uint16_t cbcr_ver_scl_mode = SCALE_NONE;
int hsub = drm_format_horz_chroma_subsampling(pixel_format);
int vsub = drm_format_vert_chroma_subsampling(pixel_format);
bool is_yuv = is_yuv_support(pixel_format);
uint16_t cbcr_src_w = src_w / hsub;
uint16_t cbcr_src_h = src_h / vsub;
uint16_t vsu_mode;
uint16_t lb_mode;
uint32_t val;
int vskiplines = 0;
const struct vop_data *vop_data = vop->data;
if (!win->phy->scl)
return;
if (!(vop_data->feature & VOP_FEATURE_ALPHA_SCALE)) {
if (is_alpha_support(pixel_format) &&
((src_w != dst_w) || (src_h != dst_h)))
DRM_ERROR("ERROR : unsupport ppixel alpha add scale\n");
}
if (!win->phy->scl->ext) {
VOP_SCL_SET(vop, win, scale_yrgb_x,
scl_cal_scale2(src_w, dst_w));
VOP_SCL_SET(vop, win, scale_yrgb_y,
scl_cal_scale2(src_h, dst_h));
if (is_yuv) {
VOP_SCL_SET(vop, win, scale_cbcr_x,
scl_cal_scale2(cbcr_src_w, dst_w));
VOP_SCL_SET(vop, win, scale_cbcr_y,
scl_cal_scale2(cbcr_src_h, dst_h));
}
return;
}
yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
if (is_yuv) {
cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
if (cbcr_hor_scl_mode == SCALE_DOWN)
lb_mode = scl_vop_cal_lb_mode(dst_w, true);
else
lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
} else {
if (yrgb_hor_scl_mode == SCALE_DOWN)
lb_mode = scl_vop_cal_lb_mode(dst_w, false);
else
lb_mode = scl_vop_cal_lb_mode(src_w, false);
}
VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
if (lb_mode == LB_RGB_3840X2) {
if (yrgb_ver_scl_mode != SCALE_NONE) {
DRM_ERROR("ERROR : not allow yrgb ver scale\n");
return;
}
if (cbcr_ver_scl_mode != SCALE_NONE) {
DRM_ERROR("ERROR : not allow cbcr ver scale\n");
return;
}
vsu_mode = SCALE_UP_BIL;
} else if (lb_mode == LB_RGB_2560X4) {
vsu_mode = SCALE_UP_BIL;
} else {
vsu_mode = SCALE_UP_BIC;
}
val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
true, 0, NULL);
VOP_SCL_SET(vop, win, scale_yrgb_x, val);
val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
false, vsu_mode, &vskiplines);
VOP_SCL_SET(vop, win, scale_yrgb_y, val);
VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
if (is_yuv) {
vskiplines = 0;
val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
dst_w, true, 0, NULL);
VOP_SCL_SET(vop, win, scale_cbcr_x, val);
val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
dst_h, false, vsu_mode, &vskiplines);
VOP_SCL_SET(vop, win, scale_cbcr_y, val);
VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
}
}
/*
* rk3328 HDR/CSC path
*
* HDR/SDR --> win0 --> HDR2SDR ----\
* \ MUX --\
* \ --> SDR2HDR/CSC--/ \
* \
* SDR --> win1 -->pre_overlay ->SDR2HDR/CSC --> post_ovrlay-->post CSC-->output
* SDR --> win2 -/
*
*/
static int vop_hdr_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
{
struct drm_atomic_state *state = crtc_state->state;
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
struct drm_plane_state *pstate;
struct drm_plane *plane;
struct vop *vop = to_vop(crtc);
int pre_sdr2hdr_state = 0, post_sdr2hdr_state = 0;
int pre_sdr2hdr_mode = 0, post_sdr2hdr_mode = 0, sdr2hdr_func = 0;
bool pre_overlay = false;
int hdr2sdr_en = 0, plane_id = 0;
if (!vop->data->hdr_table)
return 0;
/* hdr cover */
drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
struct vop_plane_state *vop_plane_state;
struct vop_win *win = to_vop_win(plane);
pstate = drm_atomic_get_plane_state(state, plane);
if (IS_ERR(pstate))
return PTR_ERR(pstate);
vop_plane_state = to_vop_plane_state(pstate);
if (!pstate->fb)
continue;
if (vop_plane_state->eotf > s->eotf)
if (win->feature & WIN_FEATURE_HDR2SDR)
hdr2sdr_en = 1;
if (vop_plane_state->eotf < s->eotf) {
if (win->feature & WIN_FEATURE_PRE_OVERLAY)
pre_sdr2hdr_state |= BIT(plane_id);
else
post_sdr2hdr_state |= BIT(plane_id);
}
plane_id++;
}
if (pre_sdr2hdr_state || post_sdr2hdr_state || hdr2sdr_en) {
pre_overlay = true;
pre_sdr2hdr_mode = BT709_TO_BT2020;
post_sdr2hdr_mode = BT709_TO_BT2020;
sdr2hdr_func = SDR2HDR_FOR_HDR;
goto exit_hdr_conver;
}
/* overlay mode */
plane_id = 0;
pre_overlay = false;
pre_sdr2hdr_mode = 0;
post_sdr2hdr_mode = 0;
pre_sdr2hdr_state = 0;
post_sdr2hdr_state = 0;
drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
struct vop_plane_state *vop_plane_state;
struct vop_win *win = to_vop_win(plane);
pstate = drm_atomic_get_plane_state(state, plane);
if (IS_ERR(pstate))
return PTR_ERR(pstate);
vop_plane_state = to_vop_plane_state(pstate);
if (!pstate->fb)
continue;
if (vop_plane_state->color_space == V4L2_COLORSPACE_BT2020 &&
vop_plane_state->color_space > s->color_space) {
if (win->feature & WIN_FEATURE_PRE_OVERLAY) {
pre_sdr2hdr_mode = BT2020_TO_BT709;
pre_sdr2hdr_state |= BIT(plane_id);
} else {
post_sdr2hdr_mode = BT2020_TO_BT709;
post_sdr2hdr_state |= BIT(plane_id);
}
}
if (s->color_space == V4L2_COLORSPACE_BT2020 &&
vop_plane_state->color_space < s->color_space) {
if (win->feature & WIN_FEATURE_PRE_OVERLAY) {
pre_sdr2hdr_mode = BT709_TO_BT2020;
pre_sdr2hdr_state |= BIT(plane_id);
} else {
post_sdr2hdr_mode = BT709_TO_BT2020;
post_sdr2hdr_state |= BIT(plane_id);
}
}
plane_id++;
}
if (pre_sdr2hdr_state || post_sdr2hdr_state) {
pre_overlay = true;
sdr2hdr_func = SDR2HDR_FOR_BT2020;
}
exit_hdr_conver:
s->hdr.pre_overlay = pre_overlay;
s->hdr.hdr2sdr_en = hdr2sdr_en;
if (s->hdr.pre_overlay)
s->yuv_overlay = 0;
s->hdr.sdr2hdr_state.bt1886eotf_pre_conv_en = !!pre_sdr2hdr_state;
s->hdr.sdr2hdr_state.rgb2rgb_pre_conv_en = !!pre_sdr2hdr_state;
s->hdr.sdr2hdr_state.rgb2rgb_pre_conv_mode = pre_sdr2hdr_mode;
s->hdr.sdr2hdr_state.st2084oetf_pre_conv_en = !!pre_sdr2hdr_state;
s->hdr.sdr2hdr_state.bt1886eotf_post_conv_en = !!post_sdr2hdr_state;
s->hdr.sdr2hdr_state.rgb2rgb_post_conv_en = !!post_sdr2hdr_state;
s->hdr.sdr2hdr_state.rgb2rgb_post_conv_mode = post_sdr2hdr_mode;
s->hdr.sdr2hdr_state.st2084oetf_post_conv_en = !!post_sdr2hdr_state;
s->hdr.sdr2hdr_state.sdr2hdr_func = sdr2hdr_func;
return 0;
}
static int to_vop_csc_mode(int csc_mode)
{
switch (csc_mode) {
case V4L2_COLORSPACE_SMPTE170M:
return CSC_BT601L;
case V4L2_COLORSPACE_REC709:
case V4L2_COLORSPACE_DEFAULT:
return CSC_BT709L;
case V4L2_COLORSPACE_JPEG:
return CSC_BT601F;
case V4L2_COLORSPACE_BT2020:
return CSC_BT2020;
default:
return CSC_BT709L;
}
}
static void vop_disable_all_planes(struct vop *vop)
{
bool active;
int ret;
vop_disable_allwin(vop);
vop_cfg_done(vop);
ret = readx_poll_timeout_atomic(vop_is_allwin_disabled,
vop, active, active,
0, 500 * 1000);
if (ret)
dev_err(vop->dev, "wait win close timeout\n");
}
/*
* rk3399 colorspace path:
* Input Win csc Output
* 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
* RGB --> R2Y __/
*
* 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
* RGB --> 709To2020->R2Y __/
*
* 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
* RGB --> R2Y __/
*
* 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
* RGB --> 709To2020->R2Y __/
*
* 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
* RGB --> R2Y __/
*
* 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
* RGB --> R2Y(601) __/
*
* 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
* RGB --> bypass __/
*
* 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
*
* 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
*
* 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
*
* 11. RGB --> bypass --> RGB_OUTPUT(709)
*/
static int vop_setup_csc_table(const struct vop_csc_table *csc_table,
bool is_input_yuv, bool is_output_yuv,
int input_csc, int output_csc,
const uint32_t **y2r_table,
const uint32_t **r2r_table,
const uint32_t **r2y_table)
{
*y2r_table = NULL;
*r2r_table = NULL;
*r2y_table = NULL;
if (!csc_table)
return 0;
if (is_output_yuv) {
if (output_csc == V4L2_COLORSPACE_BT2020) {
if (is_input_yuv) {
if (input_csc == V4L2_COLORSPACE_BT2020)
return 0;
*y2r_table = csc_table->y2r_bt709;
}
if (input_csc != V4L2_COLORSPACE_BT2020)
*r2r_table = csc_table->r2r_bt709_to_bt2020;
*r2y_table = csc_table->r2y_bt2020;
} else {
if (is_input_yuv && input_csc == V4L2_COLORSPACE_BT2020)
*y2r_table = csc_table->y2r_bt2020;
if (input_csc == V4L2_COLORSPACE_BT2020)
*r2r_table = csc_table->r2r_bt2020_to_bt709;