How to reduce the center frequency spike?

[JSzut]

Is there a way to reduce the center frequency spike using the library itself?

[nocarryr]

Is your question related to spectral analysis? There shouldn't necessarily be a "spike" at the center frequency for the raw IQ samples read from the device.

You may be seeing that in an FFT or PSD, depending on the methods used. Can you provide a code example?

[JSzut]

Sure thing, here's the code:

import pylab as plt
from rtlsdr import *

sdr = RtlSdr()
sdr.sample_rate = 2.4e6
sdr.center_freq = 101.1e6
sdr.gain = 7.7

samples = sdr.read_samples(256 * 1024)
plt.psd(samples, NFFT=1024, Fs=sdr.sample_rate / 1e6, Fc=sdr.center_freq / 1e6)

plt.show()

This is the graph with the spike (it is even on the real peak at 101.1 MHz):

[itdaniher]

You can see some excellent discussion here - the spur at 0Hz relative to your tune frequency is a fact of the mismatch between the in-phase and quadrature (I&Q) branches of the (rtl)sdr - besides modeling and subtracting the offset, there's not much you can do.

[nocarryr]

Great answer itdaniher I always thought that was an issue with the 0 Hz frequency bin of the Fourier transfer. Never knew it had to do with the LO down mix on the device itself, so thanks again for taking me to school, lol

[michelp]

Thanks @itdaniher ! great info

[nocarryr]

@itdaniher @michelp @roger-
This topic inspired me to put together a list for information like this on the wiki.

Take a look if you get the chance, I'd love to hear your feedback.

[JSzut]

Thank you for your involvment guys. Special thanks to @itdaniher for his answer.

[pinhodb]

While IQ imbalance is caused by mismatches in the two paths, RX DC offset is mainly caused by 3 factors:

• LO signal self mixing due to finite isolation between mixer ports
• LO signal (self or interfering) re-radiation from the antenna
• Interfering signal and circuit generated second-order nonlinearities

I suggest the following article which explains these fenomena in more detail http://venividiwiki.ee.virginia.edu/mediawiki/images/9/93/DCR_Raman.pdf.
Most commercial grade integrated solutions, include DACs in the Rx front end path, to perform a calibration (to null the DC offset presented at the ADC).
You can in software calculate the average of the signal and subtract it, but it's a non-ideal solution.

[RobCoding]

I suggest the following article which explains these fenomena in more detail http://venividiwiki.ee.virginia.edu/mediawiki/images/9/93/DCR_Raman.pdf.

That website no longer exists, try: https://web.archive.org/web/20170808211704/http://venividiwiki.ee.virginia.edu/mediawiki/images/9/93/DCR_Raman.pdf