RISC-V core::arch?

[tommythorn]

core::arch is missing RISC-V support, I'm specifically interested in adding support for the equivalent of rdtsc.

This was spun off #40
It was mentioned there "We generally try to stick to vendor-specified intrinsics" which is an understandable but insurmountably heavy requirement.

[lu-zero]

IF there isn't a vendor-specified set of intrinsics documented and the vendor accepts to use the ones in stdarch as part of their official documentation the problem goes away.

[luojia65]

Ref: https://github.com/riscv/rvv-intrinsic-doc

[lu-zero]

We are at https://github.com/riscv/rvv-intrinsic-doc/tree/v0.10 now, to be noted that the specification is still changing often
https://github.com/riscv-non-isa/rvv-intrinsic-doc/commits/master, but they are getting near to 1.0 now.
so either we came up with a way to feed the generator available for aarch64 in an automated way or the churn would kill any number of volunteers.

[Amanieu]

We should wait for Clang to implement these builtins first, and then hope they use some form of templating that we can reuse.

[lu-zero]

The current git seems to have them https://github.com/llvm/llvm-project/tree/main/clang/test/CodeGen/RISCV/rvv-intrinsics

[Amanieu]

We could try adapting Clang's TableGen to emit our intrinsics from the same source file as Clang: https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/riscv_vector.td

[tommythorn]

The discussion lately seems to focus on the vector extension but that seems unrelated the "rdtsc"-like features that prompted this filing.

[lu-zero]

I guess we could split the discussion, is the rdtsc-like feature documented somewhere?

[luojia65]

We should figure out a way to handle LLVM's vscale in Rust, which Rust team should we consult with on this issue?

[Amanieu]

You would have to talk to the lang team about that. Scalable vectors are similar to an unsized type in that you can't read/write it directly since it has an unknown size, but on the other hand you can pass it to functions as an argument.

[lu-zero]

https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/rvv-intrinsic-generator now is public

[lu-zero]

We have to be careful since I think we could trip in something similar to #1479 if we take the C intrinsics as-they-are.