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msr.rs
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msr.rs
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//! MSR value list and function to read and write them.
#![allow(missing_docs)]
// pub use instructions::{rdmsr, wrmsr};
// What follows is a long list of all MSR register taken from Intel's manual.
// Some of the register values appear duplicated as they may be
// called differently for different architectures or they just have
// different meanings on different platforms. It's a mess.
/// See Section 35.16, MSRs in Pentium Processors, and see Table 35-2.
pub const P5_MC_ADDR: u32 = 0x0;
/// See Section 35.16, MSRs in Pentium Processors.
pub const IA32_P5_MC_ADDR: u32 = 0x0;
/// See Section 35.16, MSRs in Pentium Processors, and see Table 35-2.
pub const P5_MC_TYPE: u32 = 0x1;
/// See Section 35.16, MSRs in Pentium Processors.
pub const IA32_P5_MC_TYPE: u32 = 0x1;
/// See Section 8.10.5, Monitor/Mwait Address Range Determination, and see Table 35-2.
pub const IA32_MONITOR_FILTER_SIZE: u32 = 0x6;
/// See Section 8.10.5, Monitor/Mwait Address Range Determination.
pub const IA32_MONITOR_FILTER_LINE_SIZE: u32 = 0x6;
/// See Section 17.13, Time-Stamp Counter, and see Table 35-2.
pub const IA32_TIME_STAMP_COUNTER: u32 = 0x10;
/// See Section 17.13, Time-Stamp Counter.
pub const TSC: u32 = 0x10;
/// Model Specific Platform ID (R)
pub const MSR_PLATFORM_ID: u32 = 0x17;
/// Platform ID (R) See Table 35-2. The operating system can use this MSR to determine slot information for the processor and the proper microcode update to load.
pub const IA32_PLATFORM_ID: u32 = 0x17;
/// Section 10.4.4, Local APIC Status and Location.
pub const APIC_BASE: u32 = 0x1b;
/// APIC Location and Status (R/W) See Table 35-2. See Section 10.4.4, Local APIC Status and Location.
pub const IA32_APIC_BASE: u32 = 0x1b;
/// Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.
pub const EBL_CR_POWERON: u32 = 0x2a;
/// Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.
pub const MSR_EBL_CR_POWERON: u32 = 0x2a;
/// Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.
pub const MSR_EBC_HARD_POWERON: u32 = 0x2a;
/// Processor Soft Power-On Configuration (R/W) Enables and disables processor features.
pub const MSR_EBC_SOFT_POWERON: u32 = 0x2b;
/// Processor Frequency Configuration The bit field layout of this MSR varies according to the MODEL value in the CPUID version information. The following bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding equal or greater than 2. (R) The field Indicates the current processor frequency configuration.
pub const MSR_EBC_FREQUENCY_ID: u32 = 0x2c;
/// Test Control Register
pub const TEST_CTL: u32 = 0x33;
/// SMI Counter (R/O)
pub const MSR_SMI_COUNT: u32 = 0x34;
/// Control Features in IA-32 Processor (R/W) See Table 35-2 (If CPUID.01H:ECX.[bit 5])
pub const IA32_FEATURE_CONTROL: u32 = 0x3a;
/// Per-Logical-Processor TSC ADJUST (R/W) See Table 35-2.
pub const IA32_TSC_ADJUST: u32 = 0x3b;
/// Last Branch Record 0 From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction for one of the last eight branches, exceptions, or interrupts taken by the processor. See also: Last Branch Record Stack TOS at 1C9H Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors).
pub const MSR_LASTBRANCH_0_FROM_IP: u32 = 0x40;
/// Last Branch Record 1 (R/W) See description of MSR_LASTBRANCH_0.
pub const MSR_LASTBRANCH_1: u32 = 0x41;
/// Last Branch Record 1 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
pub const MSR_LASTBRANCH_1_FROM_IP: u32 = 0x41;
/// Last Branch Record 2 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
pub const MSR_LASTBRANCH_2_FROM_IP: u32 = 0x42;
/// Last Branch Record 3 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
pub const MSR_LASTBRANCH_3_FROM_IP: u32 = 0x43;
/// Last Branch Record 4 (R/W) See description of MSR_LASTBRANCH_0.
pub const MSR_LASTBRANCH_4: u32 = 0x44;
/// Last Branch Record 4 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
pub const MSR_LASTBRANCH_4_FROM_IP: u32 = 0x44;
/// Last Branch Record 5 (R/W) See description of MSR_LASTBRANCH_0.
pub const MSR_LASTBRANCH_5: u32 = 0x45;
/// Last Branch Record 5 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
pub const MSR_LASTBRANCH_5_FROM_IP: u32 = 0x45;
/// Last Branch Record 6 (R/W) See description of MSR_LASTBRANCH_0.
pub const MSR_LASTBRANCH_6: u32 = 0x46;
/// Last Branch Record 6 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
pub const MSR_LASTBRANCH_6_FROM_IP: u32 = 0x46;
/// Last Branch Record 7 (R/W) See description of MSR_LASTBRANCH_0.
pub const MSR_LASTBRANCH_7: u32 = 0x47;
/// Last Branch Record 7 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.
pub const MSR_LASTBRANCH_7_FROM_IP: u32 = 0x47;
/// Last Branch Record 0 (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.9, Last Branch, Interrupt, and Exception Recording (Processors based on Intel NetBurst® Microarchitecture).
pub const MSR_LASTBRANCH_0_TO_IP: u32 = 0x6c0;
/// Last Branch Record 1 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
pub const MSR_LASTBRANCH_1_TO_IP: u32 = 0x61;
/// Last Branch Record 2 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
pub const MSR_LASTBRANCH_2_TO_IP: u32 = 0x62;
/// Last Branch Record 3 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
pub const MSR_LASTBRANCH_3_TO_IP: u32 = 0x63;
/// Last Branch Record 4 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
pub const MSR_LASTBRANCH_4_TO_IP: u32 = 0x64;
/// Last Branch Record 5 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
pub const MSR_LASTBRANCH_5_TO_IP: u32 = 0x65;
/// Last Branch Record 6 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
pub const MSR_LASTBRANCH_6_TO_IP: u32 = 0x66;
/// Last Branch Record 7 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.
pub const MSR_LASTBRANCH_7_TO_IP: u32 = 0x67;
/// BIOS Update Trigger Register (W) See Table 35-2.
pub const IA32_BIOS_UPDT_TRIG: u32 = 0x79;
/// BIOS Update Trigger Register.
pub const BIOS_UPDT_TRIG: u32 = 0x79;
/// BIOS Update Signature ID (R/W) See Table 35-2.
pub const IA32_BIOS_SIGN_ID: u32 = 0x8b;
/// SMM Monitor Configuration (R/W) See Table 35-2.
pub const IA32_SMM_MONITOR_CTL: u32 = 0x9b;
/// If IA32_VMX_MISC[bit 15])
pub const IA32_SMBASE: u32 = 0x9e;
/// System Management Mode Physical Address Mask register (WO in SMM) Model-specific implementation of SMRR-like interface, read visible and write only in SMM..
pub const MSR_SMRR_PHYSMASK: u32 = 0xa1;
/// Performance Counter Register See Table 35-2.
pub const IA32_PMC0: u32 = 0xc1;
/// Performance Counter Register See Table 35-2.
pub const IA32_PMC1: u32 = 0xc2;
/// Performance Counter Register See Table 35-2.
pub const IA32_PMC2: u32 = 0xc3;
/// Performance Counter Register See Table 35-2.
pub const IA32_PMC3: u32 = 0xc4;
/// Performance Counter Register See Table 35-2.
pub const IA32_PMC4: u32 = 0xc5;
/// Performance Counter Register See Table 35-2.
pub const IA32_PMC5: u32 = 0xc6;
/// Performance Counter Register See Table 35-2.
pub const IA32_PMC6: u32 = 0xc7;
/// Performance Counter Register See Table 35-2.
pub const IA32_PMC7: u32 = 0xc8;
/// Scaleable Bus Speed(RO) This field indicates the intended scaleable bus clock speed for processors based on Intel Atom microarchitecture:
pub const MSR_FSB_FREQ: u32 = 0xcd;
/// see http://biosbits.org.
pub const MSR_PLATFORM_INFO: u32 = 0xce;
/// C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States. See http://biosbits.org.
pub const MSR_PKG_CST_CONFIG_CONTROL: u32 = 0xe2;
/// Power Management IO Redirection in C-state (R/W) See http://biosbits.org.
pub const MSR_PMG_IO_CAPTURE_BASE: u32 = 0xe4;
/// Maximum Performance Frequency Clock Count (RW) See Table 35-2.
pub const IA32_MPERF: u32 = 0xe7;
/// Actual Performance Frequency Clock Count (RW) See Table 35-2.
pub const IA32_APERF: u32 = 0xe8;
/// MTRR Information See Section 11.11.1, MTRR Feature Identification. .
pub const IA32_MTRRCAP: u32 = 0xfe;
pub const MSR_BBL_CR_CTL: u32 = 0x119;
pub const MSR_BBL_CR_CTL3: u32 = 0x11e;
/// CS register target for CPL 0 code (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.
pub const IA32_SYSENTER_CS: u32 = 0x174;
/// CS register target for CPL 0 code
pub const SYSENTER_CS_MSR: u32 = 0x174;
/// Stack pointer for CPL 0 stack (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.
pub const IA32_SYSENTER_ESP: u32 = 0x175;
/// Stack pointer for CPL 0 stack
pub const SYSENTER_ESP_MSR: u32 = 0x175;
/// CPL 0 code entry point (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.
pub const IA32_SYSENTER_EIP: u32 = 0x176;
/// CPL 0 code entry point
pub const SYSENTER_EIP_MSR: u32 = 0x176;
pub const MCG_CAP: u32 = 0x179;
/// Machine Check Capabilities (R) See Table 35-2. See Section 15.3.1.1, IA32_MCG_CAP MSR.
pub const IA32_MCG_CAP: u32 = 0x179;
/// Machine Check Status. (R) See Table 35-2. See Section 15.3.1.2, IA32_MCG_STATUS MSR.
pub const IA32_MCG_STATUS: u32 = 0x17a;
pub const MCG_STATUS: u32 = 0x17a;
pub const MCG_CTL: u32 = 0x17b;
/// Machine Check Feature Enable (R/W) See Table 35-2. See Section 15.3.1.3, IA32_MCG_CTL MSR.
pub const IA32_MCG_CTL: u32 = 0x17b;
/// Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.
pub const MSR_SMM_MCA_CAP: u32 = 0x17d;
/// MC Bank Error Configuration (R/W)
pub const MSR_ERROR_CONTROL: u32 = 0x17f;
/// Machine Check EAX/RAX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_RAX: u32 = 0x180;
/// Machine Check EBX/RBX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_RBX: u32 = 0x181;
/// Machine Check ECX/RCX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_RCX: u32 = 0x182;
/// Machine Check EDX/RDX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_RDX: u32 = 0x183;
/// Machine Check ESI/RSI Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_RSI: u32 = 0x184;
/// Machine Check EDI/RDI Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_RDI: u32 = 0x185;
/// Machine Check EBP/RBP Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_RBP: u32 = 0x186;
/// Performance Event Select for Counter 0 (R/W) Supports all fields described inTable 35-2 and the fields below.
pub const IA32_PERFEVTSEL0: u32 = 0x186;
/// Performance Event Select for Counter 1 (R/W) Supports all fields described inTable 35-2 and the fields below.
pub const IA32_PERFEVTSEL1: u32 = 0x187;
/// Performance Event Select for Counter 2 (R/W) Supports all fields described inTable 35-2 and the fields below.
pub const IA32_PERFEVTSEL2: u32 = 0x188;
/// Machine Check EFLAGS/RFLAG Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_RFLAGS: u32 = 0x188;
/// Performance Event Select for Counter 3 (R/W) Supports all fields described inTable 35-2 and the fields below.
pub const IA32_PERFEVTSEL3: u32 = 0x189;
/// Machine Check EIP/RIP Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_RIP: u32 = 0x189;
/// Machine Check Miscellaneous See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_MISC: u32 = 0x18a;
/// See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
pub const IA32_PERFEVTSEL4: u32 = 0x18a;
/// See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
pub const IA32_PERFEVTSEL5: u32 = 0x18b;
/// See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
pub const IA32_PERFEVTSEL6: u32 = 0x18c;
/// See Table 35-2; If CPUID.0AH:EAX[15:8] = 8
pub const IA32_PERFEVTSEL7: u32 = 0x18d;
/// Machine Check R8 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_R8: u32 = 0x190;
/// Machine Check R9D/R9 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_R9: u32 = 0x191;
/// Machine Check R10 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_R10: u32 = 0x192;
/// Machine Check R11 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_R11: u32 = 0x193;
/// Machine Check R12 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_R12: u32 = 0x194;
/// Machine Check R13 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_R13: u32 = 0x195;
/// Machine Check R14 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.
pub const MSR_MCG_R14: u32 = 0x196;
pub const MSR_PERF_STATUS: u32 = 0x198;
/// See Table 35-2. See Section 14.1, Enhanced Intel Speedstep® Technology.
pub const IA32_PERF_STATUS: u32 = 0x198;
/// See Table 35-2. See Section 14.1, Enhanced Intel Speedstep® Technology.
pub const IA32_PERF_CTL: u32 = 0x199;
/// Clock Modulation (R/W) See Table 35-2. IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.
pub const IA32_CLOCK_MODULATION: u32 = 0x19a;
/// Thermal Interrupt Control (R/W) See Section 14.5.2, Thermal Monitor, and see Table 35-2.
pub const IA32_THERM_INTERRUPT: u32 = 0x19b;
/// Thermal Monitor Status (R/W) See Section 14.5.2, Thermal Monitor, and see Table 35-2.
pub const IA32_THERM_STATUS: u32 = 0x19c;
/// Thermal Monitor 2 Control.
pub const MSR_THERM2_CTL: u32 = 0x19d;
pub const IA32_MISC_ENABLE: u32 = 0x1a0;
/// Platform Feature Requirements (R)
pub const MSR_PLATFORM_BRV: u32 = 0x1a1;
pub const MSR_TEMPERATURE_TARGET: u32 = 0x1a2;
/// Offcore Response Event Select Register (R/W)
pub const MSR_OFFCORE_RSP_0: u32 = 0x1a6;
/// Offcore Response Event Select Register (R/W)
pub const MSR_OFFCORE_RSP_1: u32 = 0x1a7;
/// See http://biosbits.org.
pub const MSR_MISC_PWR_MGMT: u32 = 0x1aa;
/// See http://biosbits.org.
pub const MSR_TURBO_POWER_CURRENT_LIMIT: u32 = 0x1ac;
/// Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1
pub const MSR_TURBO_RATIO_LIMIT: u32 = 0x1ad;
/// if CPUID.6H:ECX[3] = 1
pub const IA32_ENERGY_PERF_BIAS: u32 = 0x1b0;
/// If CPUID.06H: EAX[6] = 1
pub const IA32_PACKAGE_THERM_STATUS: u32 = 0x1b1;
/// If CPUID.06H: EAX[6] = 1
pub const IA32_PACKAGE_THERM_INTERRUPT: u32 = 0x1b2;
/// Last Branch Record Filtering Select Register (R/W) See Section 17.6.2, Filtering of Last Branch Records.
pub const MSR_LBR_SELECT: u32 = 0x1c8;
/// Last Branch Record Stack TOS (R/W) Contains an index (0-3 or 0-15) that points to the top of the last branch record stack (that is, that points the index of the MSR containing the most recent branch record). See Section 17.9.2, LBR Stack for Processors Based on Intel NetBurst® Microarchitecture ; and addresses 1DBH-1DEH and 680H-68FH.
pub const MSR_LASTBRANCH_TOS: u32 = 0x1da;
pub const DEBUGCTLMSR: u32 = 0x1d9;
/// Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.9.1, MSR_DEBUGCTLA MSR.
pub const MSR_DEBUGCTLA: u32 = 0x1d9;
/// Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors).
pub const MSR_DEBUGCTLB: u32 = 0x1d9;
/// Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section.
pub const IA32_DEBUGCTL: u32 = 0x1d9;
pub const LASTBRANCHFROMIP: u32 = 0x1db;
/// Last Branch Record 0 (R/W) One of four last branch record registers on the last branch record stack. It contains pointers to the source and destination instruction for one of the last four branches, exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models 0H-02H. They have been replaced by the MSRs at 680H- 68FH and 6C0H-6CFH.
pub const MSR_LASTBRANCH_0: u32 = 0x1db;
pub const LASTBRANCHTOIP: u32 = 0x1dc;
pub const LASTINTFROMIP: u32 = 0x1dd;
/// Last Branch Record 2 See description of the MSR_LASTBRANCH_0 MSR at 1DBH.
pub const MSR_LASTBRANCH_2: u32 = 0x1dd;
/// Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors) and Section 17.12.2, Last Branch and Last Exception MSRs.
pub const MSR_LER_FROM_LIP: u32 = 0x1de;
pub const LASTINTTOIP: u32 = 0x1de;
/// Last Branch Record 3 See description of the MSR_LASTBRANCH_0 MSR at 1DBH.
pub const MSR_LASTBRANCH_3: u32 = 0x1de;
/// Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors) and Section 17.12.2, Last Branch and Last Exception MSRs.
pub const MSR_LER_TO_LIP: u32 = 0x1dd;
pub const ROB_CR_BKUPTMPDR6: u32 = 0x1e0;
/// See Table 35-2.
pub const IA32_SMRR_PHYSBASE: u32 = 0x1f2;
/// If IA32_MTRR_CAP[SMRR] = 1
pub const IA32_SMRR_PHYSMASK: u32 = 0x1f3;
/// 06_0FH
pub const IA32_PLATFORM_DCA_CAP: u32 = 0x1f8;
pub const IA32_CPU_DCA_CAP: u32 = 0x1f9;
/// 06_2EH
pub const IA32_DCA_0_CAP: u32 = 0x1fa;
/// Power Control Register. See http://biosbits.org.
pub const MSR_POWER_CTL: u32 = 0x1fc;
/// Variable Range Base MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSBASE0: u32 = 0x200;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSMASK0: u32 = 0x201;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSBASE1: u32 = 0x202;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSMASK1: u32 = 0x203;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSBASE2: u32 = 0x204;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs .
pub const IA32_MTRR_PHYSMASK2: u32 = 0x205;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSBASE3: u32 = 0x206;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSMASK3: u32 = 0x207;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSBASE4: u32 = 0x208;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSMASK4: u32 = 0x209;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSBASE5: u32 = 0x20a;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSMASK5: u32 = 0x20b;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSBASE6: u32 = 0x20c;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSMASK6: u32 = 0x20d;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSBASE7: u32 = 0x20e;
/// Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.
pub const IA32_MTRR_PHYSMASK7: u32 = 0x20f;
/// if IA32_MTRR_CAP[7:0] > 8
pub const IA32_MTRR_PHYSBASE8: u32 = 0x210;
/// if IA32_MTRR_CAP[7:0] > 8
pub const IA32_MTRR_PHYSMASK8: u32 = 0x211;
/// if IA32_MTRR_CAP[7:0] > 9
pub const IA32_MTRR_PHYSBASE9: u32 = 0x212;
/// if IA32_MTRR_CAP[7:0] > 9
pub const IA32_MTRR_PHYSMASK9: u32 = 0x213;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
pub const IA32_MTRR_FIX64K_00000: u32 = 0x250;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
pub const IA32_MTRR_FIX16K_80000: u32 = 0x258;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
pub const IA32_MTRR_FIX16K_A0000: u32 = 0x259;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
pub const IA32_MTRR_FIX4K_C0000: u32 = 0x268;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs .
pub const IA32_MTRR_FIX4K_C8000: u32 = 0x269;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs .
pub const IA32_MTRR_FIX4K_D0000: u32 = 0x26a;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
pub const IA32_MTRR_FIX4K_D8000: u32 = 0x26b;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
pub const IA32_MTRR_FIX4K_E0000: u32 = 0x26c;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
pub const IA32_MTRR_FIX4K_E8000: u32 = 0x26d;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
pub const IA32_MTRR_FIX4K_F0000: u32 = 0x26e;
/// Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.
pub const IA32_MTRR_FIX4K_F8000: u32 = 0x26f;
/// Page Attribute Table See Section 11.11.2.2, Fixed Range MTRRs.
pub const IA32_PAT: u32 = 0x277;
/// See Table 35-2.
pub const IA32_MC0_CTL2: u32 = 0x280;
/// See Table 35-2.
pub const IA32_MC1_CTL2: u32 = 0x281;
/// See Table 35-2.
pub const IA32_MC2_CTL2: u32 = 0x282;
/// See Table 35-2.
pub const IA32_MC3_CTL2: u32 = 0x283;
/// See Table 35-2.
pub const IA32_MC4_CTL2: u32 = 0x284;
/// Always 0 (CMCI not supported).
pub const MSR_MC4_CTL2: u32 = 0x284;
/// See Table 35-2.
pub const IA32_MC5_CTL2: u32 = 0x285;
/// See Table 35-2.
pub const IA32_MC6_CTL2: u32 = 0x286;
/// See Table 35-2.
pub const IA32_MC7_CTL2: u32 = 0x287;
/// See Table 35-2.
pub const IA32_MC8_CTL2: u32 = 0x288;
/// See Table 35-2.
pub const IA32_MC9_CTL2: u32 = 0x289;
/// See Table 35-2.
pub const IA32_MC10_CTL2: u32 = 0x28a;
/// See Table 35-2.
pub const IA32_MC11_CTL2: u32 = 0x28b;
/// See Table 35-2.
pub const IA32_MC12_CTL2: u32 = 0x28c;
/// See Table 35-2.
pub const IA32_MC13_CTL2: u32 = 0x28d;
/// See Table 35-2.
pub const IA32_MC14_CTL2: u32 = 0x28e;
/// See Table 35-2.
pub const IA32_MC15_CTL2: u32 = 0x28f;
/// See Table 35-2.
pub const IA32_MC16_CTL2: u32 = 0x290;
/// See Table 35-2.
pub const IA32_MC17_CTL2: u32 = 0x291;
/// See Table 35-2.
pub const IA32_MC18_CTL2: u32 = 0x292;
/// See Table 35-2.
pub const IA32_MC19_CTL2: u32 = 0x293;
/// See Table 35-2.
pub const IA32_MC20_CTL2: u32 = 0x294;
/// See Table 35-2.
pub const IA32_MC21_CTL2: u32 = 0x295;
/// Default Memory Types (R/W) Sets the memory type for the regions of physical memory that are not mapped by the MTRRs. See Section 11.11.2.1, IA32_MTRR_DEF_TYPE MSR.
pub const IA32_MTRR_DEF_TYPE: u32 = 0x2ff;
/// See Section 18.12.2, Performance Counters.
pub const MSR_BPU_COUNTER0: u32 = 0x300;
pub const MSR_GQ_SNOOP_MESF: u32 = 0x301;
/// See Section 18.12.2, Performance Counters.
pub const MSR_BPU_COUNTER1: u32 = 0x301;
/// See Section 18.12.2, Performance Counters.
pub const MSR_BPU_COUNTER2: u32 = 0x302;
/// See Section 18.12.2, Performance Counters.
pub const MSR_BPU_COUNTER3: u32 = 0x303;
/// See Section 18.12.2, Performance Counters.
pub const MSR_MS_COUNTER0: u32 = 0x304;
/// See Section 18.12.2, Performance Counters.
pub const MSR_MS_COUNTER1: u32 = 0x305;
/// See Section 18.12.2, Performance Counters.
pub const MSR_MS_COUNTER2: u32 = 0x306;
/// See Section 18.12.2, Performance Counters.
pub const MSR_MS_COUNTER3: u32 = 0x307;
/// See Section 18.12.2, Performance Counters.
pub const MSR_FLAME_COUNTER0: u32 = 0x308;
/// Fixed-Function Performance Counter Register 0 (R/W)
pub const MSR_PERF_FIXED_CTR0: u32 = 0x309;
/// Fixed-Function Performance Counter Register 0 (R/W) See Table 35-2.
pub const IA32_FIXED_CTR0: u32 = 0x309;
/// See Section 18.12.2, Performance Counters.
pub const MSR_FLAME_COUNTER1: u32 = 0x309;
/// Fixed-Function Performance Counter Register 1 (R/W)
pub const MSR_PERF_FIXED_CTR1: u32 = 0x30a;
/// Fixed-Function Performance Counter Register 1 (R/W) See Table 35-2.
pub const IA32_FIXED_CTR1: u32 = 0x30a;
/// See Section 18.12.2, Performance Counters.
pub const MSR_FLAME_COUNTER2: u32 = 0x30a;
/// Fixed-Function Performance Counter Register 2 (R/W)
pub const MSR_PERF_FIXED_CTR2: u32 = 0x30b;
/// Fixed-Function Performance Counter Register 2 (R/W) See Table 35-2.
pub const IA32_FIXED_CTR2: u32 = 0x30b;
/// See Section 18.12.2, Performance Counters.
pub const MSR_FLAME_COUNTER3: u32 = 0x30b;
/// See Section 18.12.2, Performance Counters.
pub const MSR_IQ_COUNTER4: u32 = 0x310;
/// See Section 18.12.2, Performance Counters.
pub const MSR_IQ_COUNTER5: u32 = 0x311;
/// See Table 35-2. See Section 17.4.1, IA32_DEBUGCTL MSR.
pub const IA32_PERF_CAPABILITIES: u32 = 0x345;
/// RO. This applies to processors that do not support architectural perfmon version 2.
pub const MSR_PERF_CAPABILITIES: u32 = 0x345;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_BPU_CCCR0: u32 = 0x360;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_BPU_CCCR1: u32 = 0x361;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_BPU_CCCR2: u32 = 0x362;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_BPU_CCCR3: u32 = 0x363;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_MS_CCCR0: u32 = 0x364;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_MS_CCCR1: u32 = 0x365;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_MS_CCCR2: u32 = 0x366;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_MS_CCCR3: u32 = 0x367;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_FLAME_CCCR0: u32 = 0x368;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_FLAME_CCCR1: u32 = 0x369;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_FLAME_CCCR2: u32 = 0x36a;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_FLAME_CCCR3: u32 = 0x36b;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_IQ_CCCR0: u32 = 0x36c;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_IQ_CCCR1: u32 = 0x36d;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_IQ_CCCR2: u32 = 0x36e;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_IQ_CCCR3: u32 = 0x36f;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_IQ_CCCR4: u32 = 0x370;
/// See Section 18.12.3, CCCR MSRs.
pub const MSR_IQ_CCCR5: u32 = 0x371;
/// Fixed-Function-Counter Control Register (R/W)
pub const MSR_PERF_FIXED_CTR_CTRL: u32 = 0x38d;
/// Fixed-Function-Counter Control Register (R/W) See Table 35-2.
pub const IA32_FIXED_CTR_CTRL: u32 = 0x38d;
/// See Section 18.4.2, Global Counter Control Facilities.
pub const MSR_PERF_GLOBAL_STAUS: u32 = 0x38e;
/// See Table 35-2. See Section 18.4.2, Global Counter Control Facilities.
pub const IA32_PERF_GLOBAL_STAUS: u32 = 0x38e;
/// See Section 18.4.2, Global Counter Control Facilities.
pub const MSR_PERF_GLOBAL_CTRL: u32 = 0x38f;
/// See Table 35-2. See Section 18.4.2, Global Counter Control Facilities.
pub const IA32_PERF_GLOBAL_CTRL: u32 = 0x38f;
/// See Section 18.4.2, Global Counter Control Facilities.
pub const MSR_PERF_GLOBAL_OVF_CTRL: u32 = 0x390;
/// See Table 35-2. See Section 18.4.2, Global Counter Control Facilities.
pub const IA32_PERF_GLOBAL_OVF_CTRL: u32 = 0x390;
/// See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.
pub const MSR_UNCORE_PERF_GLOBAL_CTRL: u32 = 0x391;
/// Uncore PMU global control
pub const MSR_UNC_PERF_GLOBAL_CTRL: u32 = 0x391;
/// See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.
pub const MSR_UNCORE_PERF_GLOBAL_STATUS: u32 = 0x392;
/// Uncore PMU main status
pub const MSR_UNC_PERF_GLOBAL_STATUS: u32 = 0x392;
/// See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.
pub const MSR_UNCORE_PERF_GLOBAL_OVF_CTRL: u32 = 0x393;
/// See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.
pub const MSR_UNCORE_FIXED_CTR0: u32 = 0x394;
/// Uncore W-box perfmon fixed counter
pub const MSR_W_PMON_FIXED_CTR: u32 = 0x394;
/// Uncore fixed counter control (R/W)
pub const MSR_UNC_PERF_FIXED_CTRL: u32 = 0x394;
/// See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.
pub const MSR_UNCORE_FIXED_CTR_CTRL: u32 = 0x395;
/// Uncore U-box perfmon fixed counter control MSR
pub const MSR_W_PMON_FIXED_CTR_CTL: u32 = 0x395;
/// Uncore fixed counter
pub const MSR_UNC_PERF_FIXED_CTR: u32 = 0x395;
/// See Section 18.7.2.3, Uncore Address/Opcode Match MSR.
pub const MSR_UNCORE_ADDR_OPCODE_MATCH: u32 = 0x396;
/// Uncore C-Box configuration information (R/O)
pub const MSR_UNC_CBO_CONFIG: u32 = 0x396;
pub const MSR_PEBS_NUM_ALT: u32 = 0x39c;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_BSU_ESCR0: u32 = 0x3a0;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_BSU_ESCR1: u32 = 0x3a1;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_FSB_ESCR0: u32 = 0x3a2;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_FSB_ESCR1: u32 = 0x3a3;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_FIRM_ESCR0: u32 = 0x3a4;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_FIRM_ESCR1: u32 = 0x3a5;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_FLAME_ESCR0: u32 = 0x3a6;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_FLAME_ESCR1: u32 = 0x3a7;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_DAC_ESCR0: u32 = 0x3a8;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_DAC_ESCR1: u32 = 0x3a9;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_MOB_ESCR0: u32 = 0x3aa;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_MOB_ESCR1: u32 = 0x3ab;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_PMH_ESCR0: u32 = 0x3ac;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_PMH_ESCR1: u32 = 0x3ad;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_SAAT_ESCR0: u32 = 0x3ae;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_SAAT_ESCR1: u32 = 0x3af;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_U2L_ESCR0: u32 = 0x3b0;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PMC0: u32 = 0x3b0;
/// Uncore Arb unit, performance counter 0
pub const MSR_UNC_ARB_PER_CTR0: u32 = 0x3b0;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_U2L_ESCR1: u32 = 0x3b1;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PMC1: u32 = 0x3b1;
/// Uncore Arb unit, performance counter 1
pub const MSR_UNC_ARB_PER_CTR1: u32 = 0x3b1;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_BPU_ESCR0: u32 = 0x3b2;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PMC2: u32 = 0x3b2;
/// Uncore Arb unit, counter 0 event select MSR
pub const MSR_UNC_ARB_PERFEVTSEL0: u32 = 0x3b2;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_BPU_ESCR1: u32 = 0x3b3;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PMC3: u32 = 0x3b3;
/// Uncore Arb unit, counter 1 event select MSR
pub const MSR_UNC_ARB_PERFEVTSEL1: u32 = 0x3b3;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_IS_ESCR0: u32 = 0x3b4;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PMC4: u32 = 0x3b4;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_IS_ESCR1: u32 = 0x3b5;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PMC5: u32 = 0x3b5;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_ITLB_ESCR0: u32 = 0x3b6;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PMC6: u32 = 0x3b6;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_ITLB_ESCR1: u32 = 0x3b7;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PMC7: u32 = 0x3b7;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_CRU_ESCR0: u32 = 0x3b8;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_CRU_ESCR1: u32 = 0x3b9;
/// See Section 18.12.1, ESCR MSRs. This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H.
pub const MSR_IQ_ESCR0: u32 = 0x3ba;
/// See Section 18.12.1, ESCR MSRs. This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H.
pub const MSR_IQ_ESCR1: u32 = 0x3bb;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_RAT_ESCR0: u32 = 0x3bc;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_RAT_ESCR1: u32 = 0x3bd;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_SSU_ESCR0: u32 = 0x3be;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_MS_ESCR0: u32 = 0x3c0;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PERFEVTSEL0: u32 = 0x3c0;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_MS_ESCR1: u32 = 0x3c1;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PERFEVTSEL1: u32 = 0x3c1;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_TBPU_ESCR0: u32 = 0x3c2;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PERFEVTSEL2: u32 = 0x3c2;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_TBPU_ESCR1: u32 = 0x3c3;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PERFEVTSEL3: u32 = 0x3c3;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_TC_ESCR0: u32 = 0x3c4;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PERFEVTSEL4: u32 = 0x3c4;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_TC_ESCR1: u32 = 0x3c5;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PERFEVTSEL5: u32 = 0x3c5;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PERFEVTSEL6: u32 = 0x3c6;
/// See Section 18.7.2.2, Uncore Performance Event Configuration Facility.
pub const MSR_UNCORE_PERFEVTSEL7: u32 = 0x3c7;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_IX_ESCR0: u32 = 0x3c8;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_ALF_ESCR0: u32 = 0x3ca;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_ALF_ESCR1: u32 = 0x3cb;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_CRU_ESCR2: u32 = 0x3cc;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_CRU_ESCR3: u32 = 0x3cd;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_CRU_ESCR4: u32 = 0x3e0;
/// See Section 18.12.1, ESCR MSRs.
pub const MSR_CRU_ESCR5: u32 = 0x3e1;
pub const IA32_PEBS_ENABLE: u32 = 0x3f1;
/// Precise Event-Based Sampling (PEBS) (R/W) Controls the enabling of precise event sampling and replay tagging.
pub const MSR_PEBS_ENABLE: u32 = 0x3f1;
/// See Table 19-26.
pub const MSR_PEBS_MATRIX_VERT: u32 = 0x3f2;
/// see See Section 18.7.1.2, Load Latency Performance Monitoring Facility.
pub const MSR_PEBS_LD_LAT: u32 = 0x3f6;
/// Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
pub const MSR_PKG_C3_RESIDENCY: u32 = 0x3f8;
/// Package C2 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States
pub const MSR_PKG_C2_RESIDENCY: u32 = 0x3f8;
/// Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
pub const MSR_PKG_C6C_RESIDENCY: u32 = 0x3f9;
/// Package C4 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States
pub const MSR_PKG_C4_RESIDENCY: u32 = 0x3f9;
/// Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.
pub const MSR_PKG_C7_RESIDENCY: u32 = 0x3fa;