/
jelly_vsync_adjust_de_core.v
151 lines (121 loc) · 5.1 KB
/
jelly_vsync_adjust_de_core.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
// ---------------------------------------------------------------------------
// Jelly -- The platform for real-time computing
// image processing
//
// Copyright (C) 2008-2020 by Ryuz
// https://github.com/ryuz/jelly.git
// ---------------------------------------------------------------------------
`timescale 1ns / 1ps
`default_nettype none
module jelly_vsync_adjust_de_core
#(
parameter USER_WIDTH = 0,
parameter H_COUNT_WIDTH = 14,
parameter V_COUNT_WIDTH = 14,
parameter USER_BITS = USER_WIDTH > 0 ? USER_WIDTH : 1
)
(
input wire reset,
input wire clk,
output wire update_trig,
input wire enable,
output wire busy,
input wire [H_COUNT_WIDTH-1:0] param_hsize,
input wire [V_COUNT_WIDTH-1:0] param_vsize,
input wire [H_COUNT_WIDTH-1:0] param_hstart,
input wire [V_COUNT_WIDTH-1:0] param_vstart,
input wire param_vpol,
input wire param_hpol,
input wire in_vsync,
input wire in_hsync,
input wire [USER_BITS-1:0] in_user,
output wire out_vsync,
output wire out_hsync,
output wire out_de,
output wire [USER_BITS-1:0] out_user
);
// sync detect
wire pol_vsync = out_vsync ^ param_vpol;
wire pol_hsync = out_hsync ^ param_hpol;
reg prev_vsync;
reg prev_hsync;
always @(posedge clk) begin
prev_vsync <= pol_vsync;
prev_hsync <= pol_hsync;
end
wire frame_start = ({prev_vsync, pol_vsync} == 2'b01);
wire frame_end = ({prev_vsync, pol_vsync} == 2'b10);
wire line_start = ({prev_hsync, pol_hsync} == 2'b01);
wire line_end = ({prev_hsync, pol_hsync} == 2'b10);
reg reg_enable;
reg [V_COUNT_WIDTH-1:0] reg_v_count;
reg [H_COUNT_WIDTH-1:0] reg_h_count;
reg [V_COUNT_WIDTH-1:0] reg_v_de_count;
reg [H_COUNT_WIDTH-1:0] reg_h_de_count;
reg reg_v_de;
reg reg_h_de;
reg reg_de;
always @(posedge clk) begin
if ( reset ) begin
reg_enable <= 1'b0;
reg_v_count <= {V_COUNT_WIDTH{1'bx}};
reg_h_count <= {H_COUNT_WIDTH{1'bx}};
reg_v_de_count <= {V_COUNT_WIDTH{1'bx}};
reg_h_de_count <= {H_COUNT_WIDTH{1'bx}};
reg_v_de <= 1'bx;
reg_h_de <= 1'bx;
reg_de <= 1'b0;
end
else begin
// V-Sync
if ( frame_start ) begin
reg_enable <= enable;
reg_v_count <= 0;
reg_v_de_count <= 0;
reg_v_de <= 1'b0;
end
else if ( line_end ) begin
reg_v_count <= reg_v_count + 1'b1;
if ( reg_v_de_count > 0 ) begin
reg_v_de_count <= reg_v_de_count - 1'b1;
end
else begin
reg_v_de <= 1'b0;
end
if ( reg_v_count == param_vstart ) begin
reg_v_de_count <= param_vsize;
reg_v_de <= 1'b1;
end
end
// H-Sync
if ( line_end ) begin
reg_h_count <= 0;
reg_h_de_count <= 0;
reg_h_de <= 1'b0;
end
else begin
reg_h_count <= reg_h_count + 1'b1;
if ( reg_h_de_count > 0 ) begin
reg_h_de_count <= reg_h_de_count - 1'b1;
end
else begin
reg_h_de <= 1'b0;
end
if ( reg_h_count == param_hstart ) begin
reg_h_de_count <= param_hsize;
reg_h_de <= 1'b1;
end
end
// H-sync
reg_de <= (reg_enable && reg_v_de && reg_h_de);
end
end
assign update_trig = frame_end;
assign busy = (pol_vsync && reg_enable);
assign out_vsync = in_vsync;
assign out_hsync = in_hsync;
assign out_de = reg_de;
assign out_user = in_user;
endmodule
`default_nettype wire
// end of file