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It contains all module of Big Assignment that is topic2 - A digital clock

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sandangt/BTL_Topic2_VerilogDesign

 
 

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BTL_Topic2_VerilogDesign

This project contains all module of Big Assignment that is topic2 - A digital clock

Set top file: MiniProjectTopic2.v (it only call MainManager.v to pass the input, output suitable with the De2i-150)
Testbench: MiniProjectTopic2_tb.v

Manage all module: MainManager.v

Screen 1 - The seconds, minutes, hours display (include SecondCounter.v, MinuteCounter.v, HourCounter.v, Clk24toClk12.v)
Screen 2 - The days, months, years display (include DayCounter.v, MonthCounter.v, YearCounter.v, DayOfWeekCounter.v)
Screen 3 - The time zone display (include TimeZoneMinutes.v, TimeZoneHours.v, TimeZonePlusMinus.v)
Screen 4 - Manage Mode24t12 Signal (Mode24to12Signal.v)

Display 7-Segment module: HexDisp.v
Manage signal of edit mode, screen, edit position: KeysManage.v
Manage signal of switch reverse: SwitchReverseSignal.v
Manage signal of reset: ResetSignal.v
For flicker effect when in edit mode: FlickerCounter.v

Todo:

  • Read all file begin at file MiniProjectTopic2.v

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It contains all module of Big Assignment that is topic2 - A digital clock

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  • Verilog 100.0%