introduction.rst

Introduction

RISC-V Atom is an open-source soft-core processor platform targeted for FPGAs. It is complete hardware prototyping and software development environment based around Atom, which is a 32-bit embedded-class processor based on the RISC-V Instruction Set Architecture (ISA).

Key Highlights

Key highlights of the RISC-V Atom projects are are listed below:

1. Atom implements RV32IC_Zicsr ISA as defined in the RISC-V unprivileged ISA manual.
2. Simple 2-stage pipelined architecture, ideal for smaller FPGAs.
3. Optional support for RISC-V exceptions and interrupts.
4. Wishbone ready CPU interface.
5. Interactive RTL simulator - AtomSim</pages/documentation/atomsim/atomsim>.
6. In-house verification framework - SCAR</pages/documentation/scar>.
7. Multiple SoC configurations.
8. Tiny libc like standard library - Libcatom</pages/documentation/libcatom>.
9. Wide range of example programs.
10. Open source under MIT License.

Tip

To get started, Check out the getting started guide</pages/getting_started/prerequisites>.

Components

Following is list of various components of the RISC-V Atom project.

RISC-V Atom CPU

A simple 32-bit RISC-V processor.

SoC Targets

RISC-V Atom project provides several configurable SoC targets that can be built around the Atom CPU.

AtomSim

AtomSim is the interactive RTL simulator for RISC-V Atom SoCs.

SCAR

SCAR (Search, Compile Assert, and Run) is an in-house processor verification framework written in python.