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RCA16bit.lvs.report
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RCA16bit.lvs.report
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##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: RCA16bit.lvs.report
LAYOUT NAME: /home/ywang3325/Desktop/ece3150/RCA16bit.sp ('RCA16bit')
SOURCE NAME: /home/ywang3325/Desktop/ece3150/RCA16bit.src.net ('RCA16bit')
RULE FILE: /home/ywang3325/Desktop/ece3150/_calibreLVS.rul_
RULE FILE TITLE: LVS Rule File for FreePDK45
CREATION TIME: Fri May 22 00:30:23 2020
CURRENT DIRECTORY: /home/ywang3325/Desktop/ece3150
USER NAME: ywang3325
CALIBRE VERSION: v2017.3_29.23 Fri Sep 1 13:55:54 PDT 2017
OVERALL COMPARISON RESULTS
# ################### _ _
# # # * *
# # # CORRECT # |
# # # # \___/
# ###################
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
CORRECT RCA16bit RCA16bit
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
LVS COMPONENT TYPE PROPERTY element
LVS COMPONENT SUBTYPE PROPERTY model
// LVS PIN NAME PROPERTY
LVS POWER NAME "VDD"
LVS GROUND NAME "VSS" "GROUND"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES NO
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS NO
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
// LVS SPICE EXCLUDE CELL SOURCE
// LVS SPICE EXCLUDE CELL LAYOUT
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// LVS IGNORE DEVICE PIN
// Reduction
LVS REDUCE SERIES MOS YES
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS YES
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY mn(nmos_vtl) l l 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_vtl) w w 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vtl) l l 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vtl) w w 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_vth) l l 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_vth) w w 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vth) l l 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vth) w w 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_vtg) l l 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_vtg) w w 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vtg) l l 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_vtg) w w 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_thkox) l l 4e-09 ABSOLUTE
TRACE PROPERTY mn(nmos_thkox) w w 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_thkox) l l 4e-09 ABSOLUTE
TRACE PROPERTY mp(pmos_thkox) w w 4e-09 ABSOLUTE
CELL COMPARISON RESULTS ( TOP LEVEL )
# ################### _ _
# # # * *
# # # CORRECT # |
# # # # \___/
# ###################
LAYOUT CELL NAME: RCA16bit
SOURCE CELL NAME: RCA16bit
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 52 52
Nets: 259 259
Instances: 224 224 MN (4 pins)
224 224 MP (4 pins)
------ ------
Total Inst: 448 448
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 52 52
Nets: 99 99
Instances: 16 16 SPUP_2_1 (4 pins)
16 16 SPUP_3_1 (5 pins)
16 16 SPMN_2_1 (5 pins)
16 16 SPMN_3_1 (6 pins)
32 32 _invv (4 pins)
16 16 _smn2v (4 pins)
16 16 _smn3v (5 pins)
16 16 _smp3v (5 pins)
16 16 _sup2v (4 pins)
------ ------
Total Inst: 160 160
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 52 52 0 0
Nets: 99 99 0 0
Instances: 16 16 0 0 SPUP_2_1
16 16 0 0 SPUP_3_1
16 16 0 0 SPMN_2_1
16 16 0 0 SPMN_3_1
32 32 0 0 _invv
16 16 0 0 _smn2v
16 16 0 0 _smn3v
16 16 0 0 _smp3v
16 16 0 0 _sup2v
------- ------- --------- ---------
Total Inst: 160 160 0 0
o Initial Correspondence Points:
Ports: VDD GND SUM<15> SUM<7> A<8> A<0> B<0> B<8> COUT CIN B<7> B<15> A<7> A<15>
SUM<0> SUM<8> SUM<6> SUM<14> A<9> A<1> B<1> B<9> B<6> B<14> A<6> A<14> SUM<1>
SUM<9> SUM<5> SUM<13> A<10> A<2> B<10> B<2> B<13> B<5> A<5> A<13> SUM<2>
SUM<10> SUM<4> SUM<12> A<11> A<3> B<3> B<11> B<12> B<4> A<4> A<12>
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec