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mycpu.par
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mycpu.par
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Release 14.2 par P.28xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
SDLUF6F6:: Mon Feb 24 16:57:42 2014
par -w -intstyle ise -ol high -t 1 mycpu_map.ncd mycpu.ncd mycpu.pcf
Constraints file: mycpu.pcf.
Loading device for application Rf_Device from file '3s100e.nph' in environment C:\Xilinx\14.2\ISE_DS\ISE\.
"mycpu" is an NCD, version 3.2, device xc3s100e, package cp132, speed -5
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.27 2012-07-09".
Design Summary Report:
Number of External IOBs 35 out of 83 42%
Number of External Input IOBs 8
Number of External Input IBUFs 8
Number of LOCed External Input IBUFs 7 out of 8 87%
Number of External Output IOBs 27
Number of External Output IOBs 27
Number of LOCed External Output IOBs 7 out of 27 25%
Number of External Bidir IOBs 0
Number of BUFGMUXs 2 out of 24 8%
Number of Slices 20 out of 960 2%
Number of SLICEMs 0 out of 480 0%
Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 0 secs
Finished initial Timing Analysis. REAL time: 0 secs
WARNING:Par:288 - The signal index<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal index<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal index<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal index<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal index<4>_IBUF has no load. PAR will not attempt to route this signal.
Starting Placer
Total REAL time at the beginning of Placer: 0 secs
Total CPU time at the beginning of Placer: 1 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:21c0053e) REAL time: 1 secs
Phase 2.7 Design Feasibility Check
WARNING:Place:837 - Partially locked IO Bus is found.
Following components of the bus are not locked:
Comp: b2d<7>
INFO:Place:834 - Only a subset of IOs are locked. Out of 27 IOs, 7 are locked and 20 are not locked. If you would like
to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:21c0053e) REAL time: 1 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:21c0053e) REAL time: 1 secs
Phase 4.2 Initial Clock and IO Placement
...........
Phase 4.2 Initial Clock and IO Placement (Checksum:256ad945) REAL time: 1 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:256ad945) REAL time: 1 secs
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:256ad945) REAL time: 1 secs
Phase 7.3 Local Placement Optimization
..........
Phase 7.3 Local Placement Optimization (Checksum:410f8962) REAL time: 1 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:410f8962) REAL time: 1 secs
Phase 9.8 Global Placement
...
Phase 9.8 Global Placement (Checksum:878eeed2) REAL time: 2 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:878eeed2) REAL time: 2 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:8760f866) REAL time: 2 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:8760f866) REAL time: 2 secs
Total REAL time to Placer completion: 2 secs
Total CPU time to Placer completion: 2 secs
Writing design to file mycpu.ncd
Starting Router
Phase 1 : 177 unrouted; REAL time: 3 secs
Phase 2 : 171 unrouted; REAL time: 3 secs
Phase 3 : 45 unrouted; REAL time: 3 secs
Phase 4 : 51 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Updating file: mycpu.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Updating file: mycpu.ncd with current fully routed design.
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 12 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Total REAL time to Router completion: 3 secs
Total CPU time to Router completion: 3 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| nextStage_BUFGP | BUFGMUX_X2Y10| No | 2 | 0.000 | 0.053 |
+---------------------+--------------+------+------+------------+-------------+
| clk_BUFGP | BUFGMUX_X2Y11| No | 2 | 0.002 | 0.051 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net nex | SETUP | N/A| 1.785ns| N/A| 0
tStage_BUFGP | HOLD | 1.187ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 1.802ns| N/A| 0
_BUFGP | HOLD | 1.216ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 3 secs
Total CPU time to PAR completion: 3 secs
Peak Memory Usage: 254 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 8
Number of info messages: 2
Writing design to file mycpu.ncd
PAR done!