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vivado_96806.backup.log
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vivado_96806.backup.log
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#-----------------------------------------------------------
# Vivado v2020.1 (64-bit)
# SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
# IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
# Start of session at: Tue Nov 15 22:03:05 2022
# Process ID: 96806
# Current directory: /home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed
# Command line: vivado
# Log file: /home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/vivado.log
# Journal file: /home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.xpr
Scanning sources...
Finished scanning sources
WARNING: [filemgmt 56-3] IP Repository Path: Could not find the directory '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/user_ip_repo'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/user_ip_repo'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/Xilinx/Vivado/2020.1/data/ip'.
WARNING: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
open_project: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 7255.164 ; gain = 37.039 ; free physical = 55687 ; free virtual = 122069
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'top_tb'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.std_logic_textio
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling module xil_defaultlib.glbl
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_ap_fixed_ap_fixed_config11_0_0_0 [dense_latency_ap_fixed_ap_fixed_...]
Compiling architecture behav of entity xil_defaultlib.normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s [normalize_0_0_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.relu_ap_fixed_24_8_5_3_0_ap_uint_8_relu_config12_s [relu_ap_fixed_24_8_5_3_0_ap_uint...]
Compiling architecture behav of entity xil_defaultlib.emtfptnn [emtfptnn_default]
Compiling architecture behavioral of entity xil_defaultlib.top_tb
Built simulation snapshot top_tb_behav
run_program: Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 7406.230 ; gain = 0.000 ; free physical = 55714 ; free virtual = 122096
INFO: [USF-XSim-69] 'elaborate' step finished in '11' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "top_tb_behav -key {Behavioral:sim_1:Functional:top_tb} -tclbatch {top_tb.tcl} -view {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top_tb_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.1
Time resolution is 1 ps
open_wave_config /home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top_tb_behav.wcfg
source top_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
Stopped at time : 0 fs : File "/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd" Line 136
xsim: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 7585.090 ; gain = 178.859 ; free physical = 55663 ; free virtual = 122045
INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:35 ; elapsed = 00:00:29 . Memory (MB): peak = 7585.090 ; gain = 178.859 ; free physical = 55663 ; free virtual = 122045
add_bp {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} 173
add_bp {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} 170
add_bp {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} 137
add_bp {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} 138
add_bp {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} 140
add_bp {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} 141
remove_bps -file {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} -line 136
remove_bps -file {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} -line 137
remove_bps -file {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} -line 138
remove_bps -file {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} -line 140
remove_bps -file {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} -line 141
remove_bps -file {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} -line 170
remove_bps -file {/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd} -line 173
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
Vivado Simulator 2020.1
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 7613.098 ; gain = 28.008 ; free physical = 55583 ; free virtual = 121965
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
Vivado Simulator 2020.1
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 7615.098 ; gain = 2.000 ; free physical = 55573 ; free virtual = 121955
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
Vivado Simulator 2020.1
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 7615.098 ; gain = 0.000 ; free physical = 55604 ; free virtual = 121987
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'top_tb'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.std_logic_textio
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling module xil_defaultlib.glbl
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_ap_fixed_ap_fixed_config11_0_0_0 [dense_latency_ap_fixed_ap_fixed_...]
Compiling architecture behav of entity xil_defaultlib.normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s [normalize_0_0_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.relu_ap_fixed_24_8_5_3_0_ap_uint_8_relu_config12_s [relu_ap_fixed_24_8_5_3_0_ap_uint...]
Compiling architecture behav of entity xil_defaultlib.emtfptnn [emtfptnn_default]
Compiling architecture behavioral of entity xil_defaultlib.top_tb
Built simulation snapshot top_tb_behav
run_program: Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 7615.098 ; gain = 0.000 ; free physical = 55610 ; free virtual = 121992
INFO: [USF-XSim-69] 'elaborate' step finished in '10' seconds
launch_simulation: Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 7615.098 ; gain = 0.000 ; free physical = 55610 ; free virtual = 121992
Vivado Simulator 2020.1
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:22 ; elapsed = 00:00:19 . Memory (MB): peak = 7634.105 ; gain = 19.008 ; free physical = 55605 ; free virtual = 121988
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
Vivado Simulator 2020.1
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 7634.105 ; gain = 0.000 ; free physical = 54373 ; free virtual = 120759
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
Vivado Simulator 2020.1
Time resolution is 1 ps
relaunch_xsim_kernel: Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:05 . Memory (MB): peak = 7634.105 ; gain = 0.000 ; free physical = 54866 ; free virtual = 121252
relaunch_sim: Time (s): cpu = 00:00:08 ; elapsed = 00:00:15 . Memory (MB): peak = 7634.105 ; gain = 0.000 ; free physical = 54866 ; free virtual = 121252
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'top_tb'
ERROR: [VRFC 10-3758] type 'std_logic' does not match with a string literal [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd:130]
ERROR: [VRFC 10-3758] type 'std_logic' does not match with a string literal [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd:173]
ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd:39]
INFO: [VRFC 10-3070] VHDL file '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd' ignored due to errors
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/xvhdl.log'
ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/xvhdl.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'top_tb'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.std_logic_textio
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling module xil_defaultlib.glbl
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_ap_fixed_ap_fixed_config11_0_0_0 [dense_latency_ap_fixed_ap_fixed_...]
Compiling architecture behav of entity xil_defaultlib.normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s [normalize_0_0_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.relu_ap_fixed_24_8_5_3_0_ap_uint_8_relu_config12_s [relu_ap_fixed_24_8_5_3_0_ap_uint...]
Compiling architecture behav of entity xil_defaultlib.emtfptnn [emtfptnn_default]
Compiling architecture behavioral of entity xil_defaultlib.top_tb
Built simulation snapshot top_tb_behav
run_program: Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 7634.105 ; gain = 0.000 ; free physical = 55581 ; free virtual = 121966
INFO: [USF-XSim-69] 'elaborate' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 7634.105 ; gain = 0.000 ; free physical = 55581 ; free virtual = 121966
Vivado Simulator 2020.1
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:21 ; elapsed = 00:00:18 . Memory (MB): peak = 7652.113 ; gain = 18.008 ; free physical = 55576 ; free virtual = 121962
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'top_tb'
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.std_logic_textio
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling module xil_defaultlib.glbl
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_ap_fixed_ap_fixed_config11_0_0_0 [dense_latency_ap_fixed_ap_fixed_...]
Compiling architecture behav of entity xil_defaultlib.normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s [normalize_0_0_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.relu_ap_fixed_24_8_5_3_0_ap_uint_8_relu_config12_s [relu_ap_fixed_24_8_5_3_0_ap_uint...]
Compiling architecture behav of entity xil_defaultlib.emtfptnn [emtfptnn_default]
Compiling architecture behavioral of entity xil_defaultlib.top_tb
Built simulation snapshot top_tb_behav
run_program: Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 7652.113 ; gain = 0.000 ; free physical = 55577 ; free virtual = 121963
INFO: [USF-XSim-69] 'elaborate' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:16 ; elapsed = 00:00:10 . Memory (MB): peak = 7652.113 ; gain = 0.000 ; free physical = 55577 ; free virtual = 121963
Vivado Simulator 2020.1
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:21 ; elapsed = 00:00:19 . Memory (MB): peak = 7660.117 ; gain = 8.004 ; free physical = 55572 ; free virtual = 121957
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'top_tb'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.std_logic_textio
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling module xil_defaultlib.glbl
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_ap_fixed_ap_fixed_config11_0_0_0 [dense_latency_ap_fixed_ap_fixed_...]
Compiling architecture behav of entity xil_defaultlib.normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s [normalize_0_0_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.relu_ap_fixed_24_8_5_3_0_ap_uint_8_relu_config12_s [relu_ap_fixed_24_8_5_3_0_ap_uint...]
Compiling architecture behav of entity xil_defaultlib.emtfptnn [emtfptnn_default]
Compiling architecture behavioral of entity xil_defaultlib.top_tb
Built simulation snapshot top_tb_behav
run_program: Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 7660.117 ; gain = 0.000 ; free physical = 54836 ; free virtual = 121319
INFO: [USF-XSim-69] 'elaborate' step finished in '12' seconds
launch_simulation: Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 7660.117 ; gain = 0.000 ; free physical = 54836 ; free virtual = 121319
Vivado Simulator 2020.1
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 7660.117 ; gain = 0.000 ; free physical = 54622 ; free virtual = 121105
relaunch_sim
suspend_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 7660.117 ; gain = 0.000 ; free physical = 54222 ; free virtual = 120705
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim/data1.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sim_1/new/emtfnn_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'top_tb'
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/behav/xsim'
xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /data/Xilinx/Vivado/2020.1/bin/unwrapped/lnx64.o/xelab -wto 6a5e91db9ae84fe7ab347d870930052e --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot top_tb_behav xil_defaultlib.top_tb xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.std_logic_textio
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling module xil_defaultlib.glbl
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 [dense_latency_0_0_0_0_0_0_0_0_0_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture rtl of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud_rom [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture arch of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s [tanh_ap_fixed_ap_fixed_24_8_5_3_...]
Compiling architecture behav of entity xil_defaultlib.dense_latency_ap_fixed_ap_fixed_config11_0_0_0 [dense_latency_ap_fixed_ap_fixed_...]
Compiling architecture behav of entity xil_defaultlib.normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s [normalize_0_0_0_0_0_0_0_0_0_0_0_...]
Compiling architecture behav of entity xil_defaultlib.relu_ap_fixed_24_8_5_3_0_ap_uint_8_relu_config12_s [relu_ap_fixed_24_8_5_3_0_ap_uint...]
Compiling architecture behav of entity xil_defaultlib.emtfptnn [emtfptnn_default]
Compiling architecture behavioral of entity xil_defaultlib.top_tb
Built simulation snapshot top_tb_behav
run_program: Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 7660.117 ; gain = 0.000 ; free physical = 54097 ; free virtual = 120580
INFO: [USF-XSim-69] 'elaborate' step finished in '11' seconds
launch_simulation: Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 7660.117 ; gain = 0.000 ; free physical = 54097 ; free virtual = 120580
Vivado Simulator 2020.1
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 7676.125 ; gain = 16.008 ; free physical = 53998 ; free virtual = 120481
launch_simulation -mode post-synthesis -type functional
Command: launch_simulation -mode post-synthesis -type functional
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7vx690tffg1927-2
INFO: [Device 21-403] Loading part xc7vx690tffg1927-2
INFO: [Project 1-454] Reading design checkpoint '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/usrclk_mmcm/usrclk_mmcm.dcp' for cell 'usrclk_mmcm_'
INFO: [Project 1-454] Reading design checkpoint '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_ififo/ctoc_ififo.dcp' for cell 'ctoc/ctoc_ififo_'
INFO: [Project 1-454] Reading design checkpoint '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm_in/ctoc_mmcm_in.dcp' for cell 'ctoc/ctoc_mmcm_in_'
INFO: [Project 1-454] Reading design checkpoint '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm/ctoc_mmcm.dcp' for cell 'ctoc/ctoc_mmcm_out'
INFO: [Project 1-454] Reading design checkpoint '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/inject_mem_64/inject_mem_64.dcp' for cell 'imem/im64_0'
INFO: [Project 1-454] Reading design checkpoint '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sources_1/ip/eleven2two_lut/eleven2two_lut.dcp' for cell 'my_test_algo/my_11_2_lut'
INFO: [Project 1-454] Reading design checkpoint '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.srcs/sources_1/ip/eleven2nine_lut/eleven2nine_lut.dcp' for cell 'my_test_algo/my_11_9_lut'
INFO: [Project 1-454] Reading design checkpoint '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/cgn/blk_mem_gen_0/blk_mem_gen_0.dcp' for cell 'my_test_algo/my_bram_label'
Netlist sorting complete. Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.54 . Memory (MB): peak = 7676.125 ; gain = 0.000 ; free physical = 54585 ; free virtual = 121069
INFO: [Netlist 29-17] Analyzing 4982 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2020.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_ififo/ctoc_ififo.xdc] for cell 'ctoc/ctoc_ififo_/U0'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_ififo/ctoc_ififo.xdc] for cell 'ctoc/ctoc_ififo_/U0'
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm_in/ctoc_mmcm_in_board.xdc] for cell 'ctoc/ctoc_mmcm_in_/inst'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm_in/ctoc_mmcm_in_board.xdc] for cell 'ctoc/ctoc_mmcm_in_/inst'
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm_in/ctoc_mmcm_in.xdc] for cell 'ctoc/ctoc_mmcm_in_/inst'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm_in/ctoc_mmcm_in.xdc] for cell 'ctoc/ctoc_mmcm_in_/inst'
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/usrclk_mmcm/usrclk_mmcm_board.xdc] for cell 'usrclk_mmcm_/inst'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/usrclk_mmcm/usrclk_mmcm_board.xdc] for cell 'usrclk_mmcm_/inst'
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/usrclk_mmcm/usrclk_mmcm.xdc] for cell 'usrclk_mmcm_/inst'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/usrclk_mmcm/usrclk_mmcm.xdc] for cell 'usrclk_mmcm_/inst'
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm/ctoc_mmcm_board.xdc] for cell 'ctoc/ctoc_mmcm_out/inst'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm/ctoc_mmcm_board.xdc] for cell 'ctoc/ctoc_mmcm_out/inst'
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm/ctoc_mmcm.xdc] for cell 'ctoc/ctoc_mmcm_out/inst'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm/ctoc_mmcm.xdc] for cell 'ctoc/ctoc_mmcm_out/inst'
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/mtf7_core_impl.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/mtf7_core_impl.xdc:60]
INFO: [Timing 38-2] Deriving generated clocks [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/mtf7_core_impl.xdc:60]
get_clocks: Time (s): cpu = 00:00:28 ; elapsed = 00:00:20 . Memory (MB): peak = 8712.434 ; gain = 891.465 ; free physical = 53670 ; free virtual = 120153
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/mtf7_core_impl.xdc]
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/mtf7_core_synth.xdc]
WARNING: [Constraints 18-619] A clock with name 'pcie_clk' already exists, overwriting the previous clock with the same name. [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/mtf7_core_synth.xdc:1]
WARNING: [Constraints 18-619] A clock with name 'ext_clk_in' already exists, overwriting the previous clock with the same name. [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/mtf7_core_synth.xdc:3]
WARNING: [Constraints 18-619] A clock with name 'clk40_in_p' already exists, overwriting the previous clock with the same name. [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/mtf7_core_synth.xdc:5]
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/mtf7_core_synth.xdc]
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_ififo/ctoc_ififo_clocks.xdc] for cell 'ctoc/ctoc_ififo_/U0'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_ififo/ctoc_ififo_clocks.xdc] for cell 'ctoc/ctoc_ififo_/U0'
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm_in/ctoc_mmcm_in_late.xdc] for cell 'ctoc/ctoc_mmcm_in_/inst'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm_in/ctoc_mmcm_in_late.xdc] for cell 'ctoc/ctoc_mmcm_in_/inst'
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/usrclk_mmcm/usrclk_mmcm_late.xdc] for cell 'usrclk_mmcm_/inst'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/usrclk_mmcm/usrclk_mmcm_late.xdc] for cell 'usrclk_mmcm_/inst'
Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm/ctoc_mmcm_late.xdc] for cell 'ctoc/ctoc_mmcm_out/inst'
Finished Parsing XDC File [/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/hdl/emtf/ctoc_mmcm/ctoc_mmcm_late.xdc] for cell 'ctoc/ctoc_mmcm_out/inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 8712.434 ; gain = 0.000 ; free physical = 53870 ; free virtual = 120353
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
open_run: Time (s): cpu = 00:01:07 ; elapsed = 00:01:13 . Memory (MB): peak = 9035.422 ; gain = 1359.297 ; free physical = 53567 ; free virtual = 120052
INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'...
INFO: [SIM-utils-26] write_vhdl -mode funcsim -nolib -force -file "/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/top_tb_func_synth.vhd"
INFO: [SIM-utils-36] Netlist generated:/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/top_tb_func_synth.vhd
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/data/Xilinx/Vivado/2020.1/data/xsim/xsim.ini' copied to run dir:'/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'top_tb' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/blk_mem_gen_0.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/coe_i39_30_25_20.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/eleven2nine_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/eleven2two_lut.mif'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/my_coe.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/my_coe_10mu.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/my_coe_10mu_Nov13.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/conv11to8.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/conv11to2.coe'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/data1.dat'
INFO: [SIM-utils-43] Exported '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/data1.dat'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim'
xvlog --incr --relax -prj top_tb_vlog.prj
xvhdl --incr --relax -prj top_tb_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/sergo/cms-phase2-muon-trigger/projects/dnn_emtf_displayed/top/top.sim/sim_1/synth/func/xsim/top_tb_func_synth.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'axi_or_mux'
INFO: [VRFC 10-3107] analyzing entity 'core_params_axi'
INFO: [VRFC 10-3107] analyzing entity 'ctoc_mmcm_ctoc_mmcm_clk_wiz'
INFO: [VRFC 10-3107] analyzing entity 'ctoc_mmcm_in_ctoc_mmcm_in_clk_wiz'
INFO: [VRFC 10-3107] analyzing entity 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0'
INFO: [VRFC 10-3107] analyzing entity 'dense_latency_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0'
INFO: [VRFC 10-3107] analyzing entity 'dense_latency_ap_fixed_ap_fixed_config11_0_0_0'
INFO: [VRFC 10-3107] analyzing entity 'normalize_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_s'
INFO: [VRFC 10-3107] analyzing entity 'register_bank'
INFO: [VRFC 10-3107] analyzing entity 'tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud_rom'
INFO: [VRFC 10-3107] analyzing entity 'tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb_rom'
INFO: [VRFC 10-3107] analyzing entity 'usrclk_mmcm_usrclk_mmcm_clk_wiz'
INFO: [VRFC 10-3107] analyzing entity 'blk_mem_gen_0_blk_mem_gen_prim_wrapper_init'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_wrapper_init__parameterized0\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_wrapper_init__parameterized1\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_wrapper_init__parameterized2\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_wrapper_init__parameterized3\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_wrapper_init__parameterized4\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_wrapper_init__parameterized5\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_wrapper_init__parameterized6\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_wrapper_init__parameterized7\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_wrapper_init__parameterized8\'
INFO: [VRFC 10-3107] analyzing entity 'ctoc_ififo_builtin_prim_v6'
INFO: [VRFC 10-3107] analyzing entity 'ctoc_ififo_reset_builtin'
INFO: [VRFC 10-3107] analyzing entity 'eleven2nine_lut_blk_mem_gen_prim_wrapper_init'
INFO: [VRFC 10-3107] analyzing entity 'eleven2two_lut_blk_mem_gen_prim_wrapper_init'
INFO: [VRFC 10-3107] analyzing entity 'inject_mem_64_blk_mem_gen_prim_wrapper'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized0\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized1\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized10\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized11\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized12\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized13\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized14\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized15\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized16\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized17\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized18\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized19\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized2\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized20\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized21\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized22\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized23\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized24\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized25\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized26\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized27\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized28\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized29\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized3\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized30\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized31\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized32\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized33\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized34\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized35\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized36\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized37\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized38\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized39\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized4\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized40\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized41\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized42\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized43\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized44\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized45\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized46\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized47\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized48\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized49\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized5\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized50\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized51\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized52\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized53\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized54\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized55\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized56\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized57\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized58\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized59\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized6\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized60\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized61\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized62\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized7\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized8\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_wrapper__parameterized9\'
INFO: [VRFC 10-3107] analyzing entity 'ctoc_mmcm'
INFO: [VRFC 10-3107] analyzing entity 'ctoc_mmcm_in'
INFO: [VRFC 10-3107] analyzing entity 'tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config10_s_tanh_tacud'
INFO: [VRFC 10-3107] analyzing entity 'tanh_ap_fixed_ap_fixed_24_8_5_3_0_tanh_config6_s_tanh_tabbkb'
INFO: [VRFC 10-3107] analyzing entity 'usrclk_mmcm'
INFO: [VRFC 10-3107] analyzing entity 'blk_mem_gen_0_blk_mem_gen_prim_width'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized0\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized1\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized2\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized3\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized4\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized5\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized6\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized7\'
INFO: [VRFC 10-3107] analyzing entity '\blk_mem_gen_0_blk_mem_gen_prim_width__parameterized8\'
INFO: [VRFC 10-3107] analyzing entity 'ctoc_ififo_builtin_extdepth_v6'
INFO: [VRFC 10-3107] analyzing entity 'eleven2nine_lut_blk_mem_gen_prim_width'
INFO: [VRFC 10-3107] analyzing entity 'eleven2two_lut_blk_mem_gen_prim_width'
INFO: [VRFC 10-3107] analyzing entity 'inject_mem_64_blk_mem_gen_prim_width'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_width__parameterized0\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_width__parameterized1\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_width__parameterized10\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_width__parameterized11\'
INFO: [VRFC 10-3107] analyzing entity '\inject_mem_64_blk_mem_gen_prim_width__parameterized12\'