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Kunlunxin
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sl_uart_vip
sl_uart_vip PublicThis is a simple uart vip, which supports baud_divisor and line control register.
SystemVerilog 1
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tinyriscv-uvm
tinyriscv-uvm PublicForked from liangkangnan/tinyriscv
A very simple and easy to understand RISC-V core with uvm verification environment.
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tiny-gpu-uvm
tiny-gpu-uvm PublicForked from adam-maj/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up, with UVM.
SystemVerilog 1
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